gallium: add scalar isa shader cap
authorChristian Gmeiner <christian.gmeiner@gmail.com>
Fri, 15 Jun 2018 10:29:58 +0000 (12:29 +0200)
committerChristian Gmeiner <christian.gmeiner@gmail.com>
Wed, 20 Jun 2018 15:55:39 +0000 (17:55 +0200)
v1 -> v2:
 - nv30 is _NOT_ scalar as suggested by Ilia Mirkin.
 - Change from a screen cap to a shader cap as suggested
   by Eric Anholt.
 - radeonsi is scalar as suggested by Marek Olšák.
 - Change missing ones to be scalar.

v2 -> v3:
 - r600 prefers vec4 as suggested by Marek Olšák.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
15 files changed:
src/gallium/auxiliary/gallivm/lp_bld_limits.h
src/gallium/auxiliary/tgsi/tgsi_exec.h
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_get.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/v3d/v3d_screen.c
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h

index c7755bfe1df28095b49f00481641276b5d42e423..7b66b758729e31f7191b632e9a5aed9917f284f2 100644 (file)
@@ -143,6 +143,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
+   case PIPE_SHADER_CAP_SCALAR_ISA:
+      return 1;
    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
       return 32;
    }
index 0fac7ea4567bf9febdf79e0ff149ca9e5d972a7e..ed8b9e88693d7ebdd38677a143c222cb44913dd8 100644 (file)
@@ -544,6 +544,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
+   case PIPE_SHADER_CAP_SCALAR_ISA:
+      return 1;
    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
       return PIPE_MAX_SHADER_BUFFERS;
    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
index a41c421ec47fec3d8afe424f3725ef1d4fd72a2c..d7ce521c2c37a60480986ef47a553037fe6cfa3f 100644 (file)
@@ -549,6 +549,7 @@ MOV OUT[0], CONST[0][3]  # copy vector 3 of constbuf 0
   how many HW counters are available for this stage. (0 uses SSBO atomics).
 * ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS``: If atomic counters are
   separate, how many atomic counter buffers are available for this stage.
+* ``PIPE_SHADER_CAP_SCALAR_ISA``: Whether the ISA is a scalar one.
 
 .. _pipe_compute_cap:
 
index 36b86e5f36d28cbe117412a757e717c408587674..04c7a873de651a447adc5e15c81b9199f18a2598 100644 (file)
@@ -474,6 +474,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+   case PIPE_SHADER_CAP_SCALAR_ISA:
       return 0;
    }
 
index 93f3214c3c2f64c7e219694510f6ce7a7ae7de8f..4d8307121654ad5298d00c90eb0b9672407a8ff6 100644 (file)
@@ -593,7 +593,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
        case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
-               return 0;
+       case PIPE_SHADER_CAP_SCALAR_ISA:
+               return 1;
        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
                if (is_a5xx(screen)) {
index 470625ba54239e125f94b468a69803f850a65910..95de832f6c71c001b4f5ecf25fc5ef93ad880b7c 100644 (file)
@@ -344,6 +344,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+      case PIPE_SHADER_CAP_SCALAR_ISA:
          return 0;
       default:
          debug_printf("unknown vertex shader param %d\n", param);
@@ -396,6 +397,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+      case PIPE_SHADER_CAP_SCALAR_ISA:
          return 0;
       default:
          debug_printf("unknown fragment shader param %d\n", param);
index bdb2a8e31c7d96361f4c1c45494057af655eb850..3a3c43b7749e562d9a739d3df078945bcd461d43 100644 (file)
@@ -387,6 +387,8 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
+   case PIPE_SHADER_CAP_SCALAR_ISA:
+      return 1;
    default:
       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
       return 0;
index 0efa5840207fc78d918a4ed03fa221a2f6f5c9bf..02890c71652b12a7e8b219deb27a0a4830f6bdea 100644 (file)
@@ -426,6 +426,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
+   case PIPE_SHADER_CAP_SCALAR_ISA:
+      return 1;
    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
       return NVC0_MAX_BUFFERS;
    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
index 12960ed5373bd0ecc0ae40f05efe6528fc0d4c90..bc5660d6d1127fad88c3b35a8d4412d969b21163 100644 (file)
@@ -653,6 +653,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
                        return EG_MAX_ATOMIC_BUFFERS;
                }
                return 0;
+       case PIPE_SHADER_CAP_SCALAR_ISA:
+               return 0;
        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
                /* due to a bug in the shader compiler, some loops hang
                 * if they are not unrolled, see:
index f33da90f38651d457cc9b57194506a96655ca0d6..0e8617d0fee8448b07f89f5f56a5691856845690 100644 (file)
@@ -493,6 +493,8 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
                return 0;
+       case PIPE_SHADER_CAP_SCALAR_ISA:
+               return 1;
        }
        return 0;
 }
index 9e3e3e26a3c10bf0ad335e7b927e2314fadfc46f..9d9b7971b4683c7df8b9f3bd02db28d917a70a19 100644 (file)
@@ -556,6 +556,8 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
          return 0;
+      case PIPE_SHADER_CAP_SCALAR_ISA:
+         return 1;
       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
          return 32;
       }
@@ -623,6 +625,8 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
          return 0;
+      case PIPE_SHADER_CAP_SCALAR_ISA:
+         return 1;
       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
          return 32;
       }
@@ -724,6 +728,8 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
+   case PIPE_SHADER_CAP_SCALAR_ISA:
+      return 1;
    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
       return 32;
    default:
index cd84e61f2770c097eae94a66d52dab3a646bc209..2eba557a64fe74480984f3b7737e2ffede7b69c0 100644 (file)
@@ -411,6 +411,8 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
                 return 0;
+        case PIPE_SHADER_CAP_SCALAR_ISA:
+                return 1;
         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
index 286263bf001f6d0abd123c4c8b9c18ede123f067..527ebeb2f48c5c01cfcc70957acf6a6d04dc646a 100644 (file)
@@ -465,6 +465,8 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
                 return 0;
+        case PIPE_SHADER_CAP_SCALAR_ISA:
+                return 1;
         default:
                 fprintf(stderr, "unknown shader param %d\n", param);
                 return 0;
index fa02907392c16b0304711dffb553371a03785cc2..1eefbd6519f7b1f8caab5e8dbdee24f00b2c0f29 100644 (file)
@@ -373,6 +373,9 @@ virgl_get_shader_param(struct pipe_screen *screen,
       case PIPE_SHADER_CAP_FP16:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+         return 0;
+      case PIPE_SHADER_CAP_SCALAR_ISA:
+         return 1;
       default:
          return 0;
       }
index 43db9f8fbaaa4efeb6df30a0914a1435f1f6ae53..02e0c80f1933ee8f54ea3c33af0b88f77838b17f 100644 (file)
@@ -898,6 +898,7 @@ enum pipe_shader_cap
    PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED,
    PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS,
    PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS,
+   PIPE_SHADER_CAP_SCALAR_ISA,
 };
 
 /**