r600g: add support for NI (Northern Islands) GPUs
authorAlex Deucher <alexdeucher@gmail.com>
Thu, 6 Jan 2011 23:05:16 +0000 (18:05 -0500)
committerAlex Deucher <alexdeucher@gmail.com>
Thu, 6 Jan 2011 23:05:16 +0000 (18:05 -0500)
This adds support for Barts, Turks, and Caicos asics.

src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600.h
src/gallium/drivers/r600/r600_asm.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/winsys/r600/drm/r600_drm.c
src/gallium/winsys/r600/drm/radeon_pciid.c

index c6f3669c9a3e61c83a78a7180df04eaccdafdec8..c4675fedad217cc29a4949d3adbf3f42eaaae272 100644 (file)
@@ -1067,12 +1067,76 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
                num_hs_stack_entries = 42;
                num_ls_stack_entries = 42;
                break;
+       case CHIP_BARTS:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 128;
+               num_vs_threads = 20;
+               num_gs_threads = 20;
+               num_es_threads = 20;
+               num_hs_threads = 20;
+               num_ls_threads = 20;
+               num_ps_stack_entries = 85;
+               num_vs_stack_entries = 85;
+               num_gs_stack_entries = 85;
+               num_es_stack_entries = 85;
+               num_hs_stack_entries = 85;
+               num_ls_stack_entries = 85;
+               break;
+       case CHIP_TURKS:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 128;
+               num_vs_threads = 20;
+               num_gs_threads = 20;
+               num_es_threads = 20;
+               num_hs_threads = 20;
+               num_ls_threads = 20;
+               num_ps_stack_entries = 42;
+               num_vs_stack_entries = 42;
+               num_gs_stack_entries = 42;
+               num_es_stack_entries = 42;
+               num_hs_stack_entries = 42;
+               num_ls_stack_entries = 42;
+               break;
+       case CHIP_CAICOS:
+               num_ps_gprs = 93;
+               num_vs_gprs = 46;
+               num_temp_gprs = 4;
+               num_gs_gprs = 31;
+               num_es_gprs = 31;
+               num_hs_gprs = 23;
+               num_ls_gprs = 23;
+               num_ps_threads = 128;
+               num_vs_threads = 10;
+               num_gs_threads = 10;
+               num_es_threads = 10;
+               num_hs_threads = 10;
+               num_ls_threads = 10;
+               num_ps_stack_entries = 42;
+               num_vs_stack_entries = 42;
+               num_gs_stack_entries = 42;
+               num_es_stack_entries = 42;
+               num_hs_stack_entries = 42;
+               num_ls_stack_entries = 42;
+               break;
        }
 
        tmp = 0x00000000;
        switch (family) {
        case CHIP_CEDAR:
        case CHIP_PALM:
+       case CHIP_CAICOS:
                break;
        default:
                tmp |= S_008C00_VC_ENABLE(1);
index 578ac40ba983951ec1d5d1efe14f3ef9a01b5b94..335f282b06f1c43d00a412c7af0325d2844e5a86 100644 (file)
@@ -92,6 +92,9 @@ enum radeon_family {
        CHIP_CYPRESS,
        CHIP_HEMLOCK,
        CHIP_PALM,
+       CHIP_BARTS,
+       CHIP_TURKS,
+       CHIP_CAICOS,
        CHIP_LAST,
 };
 
index 894d0d2fcd0f6907b03ecba49100d3488d0a6c38..9b9f033cbe42686fef805c1952627722c24fb680 100644 (file)
@@ -155,6 +155,9 @@ int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
        case CHIP_CYPRESS:
        case CHIP_HEMLOCK:
        case CHIP_PALM:
+       case CHIP_BARTS:
+       case CHIP_TURKS:
+       case CHIP_CAICOS:
                bc->chiprev = CHIPREV_EVERGREEN;
                break;
        default:
index 8f6836a573012c17a8a1d9a0101ebfbd1e539a85..0bf87607b5bc5a2d6676949d7f6044ef14f82fab 100644 (file)
@@ -148,6 +148,9 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
        case CHIP_CYPRESS:
        case CHIP_HEMLOCK:
        case CHIP_PALM:
+       case CHIP_BARTS:
+       case CHIP_TURKS:
+       case CHIP_CAICOS:
                rctx->context.draw_vbo = evergreen_draw;
                evergreen_init_state_functions(rctx);
                if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
@@ -230,6 +233,9 @@ static const char *r600_get_family_name(enum radeon_family family)
        case CHIP_CYPRESS: return "AMD CYPRESS";
        case CHIP_HEMLOCK: return "AMD HEMLOCK";
        case CHIP_PALM: return "AMD PALM";
+       case CHIP_BARTS: return "AMD BARTS";
+       case CHIP_TURKS: return "AMD TURKS";
+       case CHIP_CAICOS: return "AMD CAICOS";
        default: return "AMD unknown";
        }
 }
index 58aacb77c9ebbd815f448197a3cd18298d14bdcb..36ec583ccee7e2768dd549df11aab0bea8701b32 100644 (file)
@@ -177,6 +177,9 @@ static struct radeon *radeon_new(int fd, unsigned device)
        case CHIP_CYPRESS:
        case CHIP_HEMLOCK:
        case CHIP_PALM:
+       case CHIP_BARTS:
+       case CHIP_TURKS:
+       case CHIP_CAICOS:
                radeon->chip_class = EVERGREEN;
                /* set default group bytes, overridden by tiling info ioctl */
                radeon->tiling_info.group_bytes = 512;
index 92560a488ae5637981021e90f52581f95191a2ce..e2622abd46855b5b42d977c32787e772cedefc6e 100644 (file)
@@ -445,6 +445,42 @@ struct pci_id radeon_pci_id[] = {
        {0x1002, 0x9803, CHIP_PALM},
        {0x1002, 0x9804, CHIP_PALM},
        {0x1002, 0x9805, CHIP_PALM},
+       {0x1002, 0x6720, CHIP_BARTS},
+       {0x1002, 0x6721, CHIP_BARTS},
+       {0x1002, 0x6722, CHIP_BARTS},
+       {0x1002, 0x6723, CHIP_BARTS},
+       {0x1002, 0x6724, CHIP_BARTS},
+       {0x1002, 0x6725, CHIP_BARTS},
+       {0x1002, 0x6726, CHIP_BARTS},
+       {0x1002, 0x6727, CHIP_BARTS},
+       {0x1002, 0x6728, CHIP_BARTS},
+       {0x1002, 0x6729, CHIP_BARTS},
+       {0x1002, 0x6738, CHIP_BARTS},
+       {0x1002, 0x6739, CHIP_BARTS},
+       {0x1002, 0x6740, CHIP_TURKS},
+       {0x1002, 0x6741, CHIP_TURKS},
+       {0x1002, 0x6742, CHIP_TURKS},
+       {0x1002, 0x6743, CHIP_TURKS},
+       {0x1002, 0x6744, CHIP_TURKS},
+       {0x1002, 0x6745, CHIP_TURKS},
+       {0x1002, 0x6746, CHIP_TURKS},
+       {0x1002, 0x6747, CHIP_TURKS},
+       {0x1002, 0x6748, CHIP_TURKS},
+       {0x1002, 0x6749, CHIP_TURKS},
+       {0x1002, 0x6750, CHIP_TURKS},
+       {0x1002, 0x6758, CHIP_TURKS},
+       {0x1002, 0x6759, CHIP_TURKS},
+       {0x1002, 0x6760, CHIP_CAICOS},
+       {0x1002, 0x6761, CHIP_CAICOS},
+       {0x1002, 0x6762, CHIP_CAICOS},
+       {0x1002, 0x6763, CHIP_CAICOS},
+       {0x1002, 0x6764, CHIP_CAICOS},
+       {0x1002, 0x6765, CHIP_CAICOS},
+       {0x1002, 0x6766, CHIP_CAICOS},
+       {0x1002, 0x6767, CHIP_CAICOS},
+       {0x1002, 0x6768, CHIP_CAICOS},
+       {0x1002, 0x6770, CHIP_CAICOS},
+       {0x1002, 0x6779, CHIP_CAICOS},
        {0, 0},
 };