i965: Fix the response len of masked sampler messages for 8-wide dispatch.

The bad response length would hang the GPU with a masked sample in a
shader using control flow.  For 8-wide, the response length is always
4, and masked slots are just not written to.  brw_wm_glsl.c already
allocates registers in the right locations.

Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f69d529613724e03bff34e92d691326659f36f6e..40c1b719984e33ebb96f5565397f6b079024457f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1290,7 +1290,11 @@ void brw_SAMPLE(struct brw_compile *p,
                GLuint simd_mode)
 {
    GLboolean need_stall = 0;
-   
+   GLboolean dispatch_16 = GL_FALSE;
+
+   if (p->current->header.execution_size == BRW_EXECUTE_16)
+      dispatch_16 = GL_TRUE;
+
    if (writemask == 0) {
       /*printf("%s: zero writemask??\n", __FUNCTION__); */
       return;
@@ -1343,7 +1347,13 @@ void brw_SAMPLE(struct brw_compile *p,
 
         src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); 
         dest = offset(dest, dst_offset);
-        response_length = len * 2;
+
+        /* For 16-wide dispatch, masked channels are skipped in the
+         * response.  For 8-wide, masked channels still take up slots,
+         * and are just not written to.
+         */
+        if (dispatch_16)
+           response_length = len * 2;
       }
    }