freedreno/a6xx: split up gmem/tile alignment requirements
authorJonathan Marek <jonathan@marek.ca>
Wed, 13 May 2020 01:56:53 +0000 (21:56 -0400)
committerMarge Bot <eric+marge@anholt.net>
Wed, 20 May 2020 18:24:28 +0000 (18:24 +0000)
RB_BLIT has a granularity of 16x4, but tile sizes must be 32x16 aligned.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

src/gallium/drivers/freedreno/freedreno_gmem.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/freedreno/freedreno_screen.h

index bbffda66e470792afe28b07391e0d40c0d5579b4..b3ef0978f9ed8c1e1af116ce23c79b631744e0bd 100644 (file)
@@ -184,8 +184,8 @@ layout_gmem(struct gmem_key *key, uint32_t nbins_x, uint32_t nbins_y,
                return false;
 
        uint32_t bin_w, bin_h;
-       bin_w = div_align(key->width, nbins_x, screen->gmem_alignw);
-       bin_h = div_align(key->height, nbins_y, screen->gmem_alignh);
+       bin_w = div_align(key->width, nbins_x, screen->tile_alignw);
+       bin_h = div_align(key->height, nbins_y, screen->tile_alignh);
 
        gmem->bin_w = bin_w;
        gmem->bin_h = bin_h;
@@ -244,7 +244,7 @@ gmem_stateobj_init(struct fd_screen *screen, struct gmem_key *key)
        /* first, find a bin width that satisfies the maximum width
         * restrictions:
         */
-       while (div_align(key->width, nbins_x, screen->gmem_alignw) > max_width) {
+       while (div_align(key->width, nbins_x, screen->tile_alignw) > max_width) {
                nbins_x++;
        }
 
index d19f6483e5f1d27e92ee3989a061d71170571cc5..d2ad24fb7c05266978fcd8a280be84c9530e5d1c 100644 (file)
@@ -944,16 +944,18 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
        }
 
        if (screen->gpu_id >= 600) {
-               screen->gmem_alignw = 32;
-               screen->gmem_alignh = 32;
+               screen->gmem_alignw = 16;
+               screen->gmem_alignh = 4;
+               screen->tile_alignw = 32;
+               screen->tile_alignh = 32;
                screen->num_vsc_pipes = 32;
        } else if (screen->gpu_id >= 500) {
-               screen->gmem_alignw = 64;
-               screen->gmem_alignh = 32;
+               screen->gmem_alignw = screen->tile_alignw = 64;
+               screen->gmem_alignh = screen->tile_alignh = 32;
                screen->num_vsc_pipes = 16;
        } else {
-               screen->gmem_alignw = 32;
-               screen->gmem_alignh = 32;
+               screen->gmem_alignw = screen->tile_alignw = 32;
+               screen->gmem_alignh = screen->tile_alignh = 32;
                screen->num_vsc_pipes = 8;
        }
 
index d6bd17daffc63500fa8dba48e3e3c97cc2fcf1e7..13e48dd5d3dbcf1df5348902fdeb40c84289033c 100644 (file)
@@ -70,7 +70,8 @@ struct fd_screen {
        uint32_t max_freq;
        uint32_t ram_size;
        uint32_t max_rts;        /* max # of render targets */
-       uint32_t gmem_alignw, gmem_alignh;
+       uint32_t gmem_alignw, gmem_alignh; /* gmem load/store granularity */
+       uint32_t tile_alignw, tile_alignh; /* alignment for tile sizes */
        uint32_t num_vsc_pipes;
        uint32_t priority_mask;
        bool has_timestamp;