radeonsi: simplify logic around vi_separate_dcc_try_enable

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 5cbbc89b60e1f7022ffa7ed24c3bea8635ea7f3d..6313f904b4190daefe8b533b0887f59536752f92 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -435,19 +435,16 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                /* Fast clear is the most appropriate place to enable DCC for
                 * displayable surfaces.
                 */
-               if (sctx->chip_class >= VI &&
-                   !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
-                       vi_separate_dcc_try_enable(sctx, tex);
-
-                       /* RB+ isn't supported with a CMASK clear only on Stoney,
-                        * so all clears are considered to be hypothetically slow
-                        * clears, which is weighed when determining whether to
-                        * enable separate DCC.
-                        */
-                       if (tex->dcc_gather_statistics &&
-                           sctx->family == CHIP_STONEY)
-                               tex->num_slow_clears++;
-               }
+               vi_separate_dcc_try_enable(sctx, tex);
+
+               /* RB+ isn't supported with a CMASK clear only on Stoney,
+                * so all clears are considered to be hypothetically slow
+                * clears, which is weighed when determining whether to
+                * enable separate DCC.
+                */
+               if (tex->dcc_gather_statistics &&
+                   sctx->family == CHIP_STONEY)
+                       tex->num_slow_clears++;
 
                bool need_decompress_pass = false;
 

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index bbfac7cc4be172eceac22f61c5fd392b44b308c7..46df4aecf09de626a896d841f3552e15382ca33b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -2231,9 +2231,13 @@ void vi_separate_dcc_try_enable(struct si_context *sctx,
            !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) ||
            tex->buffer.b.b.target != PIPE_TEXTURE_2D ||
            tex->buffer.b.b.last_level > 0 ||
-           !tex->surface.dcc_size)
+           !tex->surface.dcc_size ||
+           sctx->screen->debug_flags & DBG(NO_DCC) ||
+           sctx->screen->debug_flags & DBG(NO_DCC_FB))
                return;
 
+       assert(sctx->chip_class >= VI);
+
        if (tex->dcc_offset)
                return; /* already enabled */