gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsi
authorMarek Olšák <marek.olsak@amd.com>
Wed, 22 Aug 2018 02:00:11 +0000 (22:00 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Fri, 7 Sep 2018 01:53:00 +0000 (21:53 -0400)
22 files changed:
docs/relnotes/18.3.0.html
src/gallium/auxiliary/util/u_screen.c
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/radeonsi/si_get.c
src/gallium/drivers/radeonsi/si_state.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h
src/mesa/state_tracker/st_extensions.c

index 71fb41ca86fd6e76a0f5117c25613c1bdf44f248..5874d3fa330145156271b14b937407d4e5fb57c6 100644 (file)
@@ -51,6 +51,7 @@ Note: some of the new features are only available with certain drivers.
 </p>
 
 <ul>
+<li>GL_AMD_depth_clamp_separate on r600, radeonsi.</li>
 <li>GL_AMD_framebuffer_multisample_advanced on radeonsi.</li>
 <li>GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.</li>
 <li>GL_AMD_multi_draw_indirect on all GL 4.x drivers.</li>
index f0290d04cc559f714abb565e38ca33db462e74bf..4843ba57567477ab7189799395cc31347a714687 100644 (file)
@@ -69,6 +69,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
    case PIPE_CAP_DEPTH_CLIP_DISABLE:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
    case PIPE_CAP_SHADER_STENCIL_EXPORT:
    case PIPE_CAP_TGSI_INSTANCEID:
    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
index cb9d0e2a15a305c982d82f00994a1ee473c679c5..e2b09d7b9c54e6dfc63b66ed66e2436a284775de 100644 (file)
@@ -69,6 +69,10 @@ The integer capabilities:
   property FS_COORD_PIXEL_CENTER with value INTEGER is supported.
 * ``PIPE_CAP_DEPTH_CLIP_DISABLE``: Whether the driver is capable of disabling
   depth clipping (through pipe_rasterizer_state)
+* ``PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE``: Whether the driver is capable of
+  disabling depth clipping (through pipe_rasterizer_state) separately for
+  the near and far plane. If not, depth_clip_near and depth_clip_far will be
+  equal.
 * ``PIPE_CAP_SHADER_STENCIL_EXPORT``: Whether a stencil reference value can be
   written from a fragment shader.
 * ``PIPE_CAP_TGSI_INSTANCEID``: Whether TGSI_SEMANTIC_INSTANCEID is supported
index 9ddba62855041369d4c7692069e095d994f73f12..cafc8bf1f5b488e0a5b45e9a590d01bfba1fcbb6 100644 (file)
@@ -186,6 +186,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_INDEP_BLEND_ENABLE:
    case PIPE_CAP_INDEP_BLEND_FUNC:
    case PIPE_CAP_DEPTH_CLIP_DISABLE:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
index 4e972aea1b0616761571fbe6801a04ae00d978bc..33f14b8f24828867336f505f120ede0aa30111ad 100644 (file)
@@ -215,6 +215,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_PCI_BUS:
        case PIPE_CAP_PCI_DEVICE:
        case PIPE_CAP_PCI_FUNCTION:
+       case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
                return 0;
 
        case PIPE_CAP_SM3:
index 1d98625f81256e7b0a18a05af44b3ab341d0aa7d..5926d3555080bfe3e6d81275012a025dd406f519 100644 (file)
@@ -211,6 +211,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
    /* Unsupported features (boolean caps). */
    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
    case PIPE_CAP_DEPTH_CLIP_DISABLE:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
    case PIPE_CAP_INDEP_BLEND_ENABLE:
    case PIPE_CAP_INDEP_BLEND_FUNC:
    case PIPE_CAP_SHADER_STENCIL_EXPORT:
index 93bdd4262631daff571ef9ec8fd6bbf7fb01cdc1..15ddaf5333b4a9a14c5fc2ab14894b95f0f102cc 100644 (file)
@@ -158,6 +158,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
       return 1;
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
       return 0;
    case PIPE_CAP_PRIMITIVE_RESTART:
       return 1;
index 719a4a84fc33cddf5f31910094e549ffb6b43dab..1e0b5728ddfc9e07ccdc760b14ec55b47a1fc70b 100644 (file)
@@ -109,6 +109,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_PRIMITIVE_RESTART:
       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
    /* unsupported */
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
    case PIPE_CAP_SM3:
    case PIPE_CAP_INDEP_BLEND_ENABLE:
index d36305f3a6942a1a90ee9828721c7fd72ea8a976..210ce18a8c8b3201a4f6e9450c7b2c0a9bca740e 100644 (file)
@@ -219,6 +219,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return class_3d >= NVA3_3D_CLASS;
 
    /* unsupported caps */
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
index 252cb466e0714c2e40629af3412625215818f501..6ad99ed6d65995b7d45993b0e3ee38ed8082e26b 100644 (file)
@@ -281,6 +281,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return class_3d >= NVE4_3D_CLASS;
 
    /* unsupported caps */
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
    case PIPE_CAP_SHADER_STENCIL_EXPORT:
index 2531479b53a5aed301dc958be598a78c9d4143b0..0c95acdad4b8c3c20628837fa7f77c957973975c 100644 (file)
@@ -147,6 +147,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_INDEP_BLEND_ENABLE:
         case PIPE_CAP_INDEP_BLEND_FUNC:
         case PIPE_CAP_DEPTH_CLIP_DISABLE:
+        case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
         case PIPE_CAP_SHADER_STENCIL_EXPORT:
         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
         case PIPE_CAP_TGSI_INSTANCEID:
index 49c9ad9ee4ab364c93e22e14e05a2f510363570d..3aff0124037a3315e2356793d9c91c1799119552 100644 (file)
@@ -493,7 +493,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
        rs->pa_cl_clip_cntl =
                S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
-               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
+               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
                S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
        rs->multisample_enable = state->multisample;
index c6311bf8c39fdaa2589bf1544e356f4a2ec93361..e7ad2ee39a821b7223ab7c703f898d05210d7475 100644 (file)
@@ -265,6 +265,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_BLEND_EQUATION_SEPARATE:
        case PIPE_CAP_TEXTURE_SWIZZLE:
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
+       case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
        case PIPE_CAP_SHADER_STENCIL_EXPORT:
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
        case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
index 9a49ba065f40697f3f104825b31154ee82180834..f86764f522019fe515f5013b7ea0c96fdf9dd171 100644 (file)
@@ -480,7 +480,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
        rs->pa_cl_clip_cntl =
                S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
-               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
+               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
        if (rctx->b.chip_class == R700) {
                rs->pa_cl_clip_cntl |=
index 60f4b07113f391aef0f2218c2a61bae1236e7183..5d9061e49e9e1160a38afb2f52e3775a0ca03479 100644 (file)
@@ -71,6 +71,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_BLEND_EQUATION_SEPARATE:
        case PIPE_CAP_TEXTURE_SWIZZLE:
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
+       case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
        case PIPE_CAP_SHADER_STENCIL_EXPORT:
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
        case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
index 18024a9f77dc14f2578d9415e385b0f24dca4476..40c478f0a46e3ee907f30d990b57812be7ba55c5 100644 (file)
@@ -870,7 +870,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
        rs->pa_cl_clip_cntl =
                S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
-               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
+               S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
                S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 
index 183aaae09eb125c2a5152585e0c830d6b8d7d216..61a4133d30d35776a42f9a896343928ebeca9cb4 100644 (file)
@@ -144,6 +144,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_CONDITIONAL_RENDER:
       return 1;
    case PIPE_CAP_TEXTURE_BARRIER:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
       return 0;
    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: /* draw module */
index 247c88d515c8a3d4fe6608f76b1ce1c149877b6b..ea22a4fe7d48aa114fd07dc9aed2f66c928abda3 100644 (file)
@@ -283,6 +283,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return sws->have_vgpu10 ? 140 : 120;
 
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
       return 0;
 
    case PIPE_CAP_SM3:
index 706ed5621cd6193414514d4b957aa374f3c7e483..2190be4b571a1a5a915e125ab32a949b64b6c898 100644 (file)
@@ -203,6 +203,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return PIPE_ENDIAN_NATIVE;
    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
       return 0;
 
       /* supported features */
index 8a78091a0f3cd611170a624a9c3dd47b8fadf6f0..a72ea3a3a1a1cff7bc01ff3a9e190026771368e0 100644 (file)
@@ -150,6 +150,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
       return 0;
    case PIPE_CAP_COMPUTE:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
index 3cff4d9fda5a043a05f4fe492793b1383d938577..22515504f6cfee20dfaa41aa0dfed1bee566c60a 100644 (file)
@@ -668,6 +668,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
    PIPE_CAP_DEPTH_CLIP_DISABLE,
+   PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE,
    PIPE_CAP_SHADER_STENCIL_EXPORT,
    PIPE_CAP_TGSI_INSTANCEID,
    PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
index 319eef6a729066441b158aedd567dd8c8815e170..661b2e499fe06b9f14a8d674198a082a437db2e5 100644 (file)
@@ -743,6 +743,7 @@ void st_init_extensions(struct pipe_screen *screen,
       { o(EXT_transform_feedback),           PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS        },
       { o(EXT_window_rectangles),            PIPE_CAP_MAX_WINDOW_RECTANGLES            },
 
+      { o(AMD_depth_clamp_separate),         PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE      },
       { o(AMD_framebuffer_multisample_advanced), PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS },
       { o(AMD_pinned_memory),                PIPE_CAP_RESOURCE_FROM_USER_MEMORY        },
       { o(ATI_meminfo),                      PIPE_CAP_QUERY_MEMORY_INFO                },