vc4: Make sure we don't overflow texture input/output FIFOs when threaded.

I dropped the first hunk of this change last minute when I decided it
wasn't actually needed, and apparently failed to piglit it in simulation.
The simulator threw an an assertion in gl-1.0-drawpixels-color-index,
which queued up 5 coordinates (3 before a switch, two after) before
loading the result.

diff --git a/src/gallium/drivers/vc4/vc4_qir_schedule.c b/src/gallium/drivers/vc4/vc4_qir_schedule.c
index 4f17733486a746f1d35ead09388632b87bf38781..6eaa2e075acb2064b237008984b8e71074066c49 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_qir_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qir_schedule.c
@@ -344,7 +344,7 @@ calculate_forward_deps(struct vc4_compile *c, void *mem_ctx,
                          * If the texture coordinate fifo is full, block this
                          * on the last QOP_TEX_RESULT.
                          */
-                        if (state.tfreq_count == 8) {
+                        if (state.tfreq_count == (c->fs_threaded ? 4 : 8)) {
                                 block_until_tex_result(&state, n);
                         }
 
@@ -366,7 +366,8 @@ calculate_forward_deps(struct vc4_compile *c, void *mem_ctx,
                          */
                         if (inst->op == QOP_TEX_S ||
                             inst->op == QOP_TEX_DIRECT) {
-                                if (state.tfrcv_count == 4)
+                                if (state.tfrcv_count ==
+                                    (c->fs_threaded ? 2 : 4))
                                         block_until_tex_result(&state, n);
                                 state.tfrcv_count++;
                         }