From: H.J. Lu <hjl.tools@gmail.com>
Date: Thu, 27 Feb 2020 17:18:37 +0000 (-0800)
Subject: x86_init_func_common: Add ENDBR at function entry
X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=commitdiff_plain;h=007e623025bfc1f66686d1e1cd6a3efeff863f69

x86_init_func_common: Add ENDBR at function entry

Intel Control-flow Enforcement Technology (CET):

https://software.intel.com/en-us/articles/intel-sdm

when IBT is enabled, all indirect branch targets must start with ENDBR
instruction which is a NOP on non-CET processors.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2575

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
---

diff --git a/src/gallium/auxiliary/rtasm/rtasm_x86sse.c b/src/gallium/auxiliary/rtasm/rtasm_x86sse.c
index 3e7d699627a..ad687f32853 100644
--- a/src/gallium/auxiliary/rtasm/rtasm_x86sse.c
+++ b/src/gallium/auxiliary/rtasm/rtasm_x86sse.c
@@ -2165,6 +2165,11 @@ static void x86_init_func_common( struct x86_function *p )
    if(util_cpu_caps.has_sse4_1)
       p->caps |= X86_SSE4_1;
    p->csr = p->store;
+#if defined(PIPE_ARCH_X86)
+   emit_1i(p, 0xfb1e0ff3);
+#else
+   emit_1i(p, 0xfa1e0ff3);
+#endif
    DUMP_START();
 }