From: Qiang Yu <yuq825@gmail.com>
Date: Thu, 3 Sep 2020 03:30:28 +0000 (+0800)
Subject: radeonsi: fix user fence space when MCBP is enabled
X-Git-Url: https://git.libre-soc.org/?p=mesa.git;a=commitdiff_plain;h=caf2ff491e64033e0a9cd7f399c99a90c0d49a3b

radeonsi: fix user fence space when MCBP is enabled

When MCBP is enabled, IB maybe preempted which will also update
the preempted fence field of the user fence. So we need to reserve
enough space for each user fence.

Fixes: 89d2dac5548 "radeonsi: enable preemption if the kernel enabled it"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6577>
---

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index f51c7782033..c531d72ca45 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1683,8 +1683,14 @@ finalize:
       /* Success. */
       uint64_t *user_fence = NULL;
 
+      /* Need to reserve 4 QWORD for user fence:
+       *   QWORD[0]: completed fence
+       *   QWORD[1]: preempted fence
+       *   QWORD[2]: reset fence
+       *   QWORD[3]: preempted then reset
+       **/
       if (has_user_fence)
-         user_fence = acs->ctx->user_fence_cpu_address_base + acs->ring_type;
+         user_fence = acs->ctx->user_fence_cpu_address_base + acs->ring_type * 4;
       amdgpu_fence_submitted(cs->fence, seq_no, user_fence);
    }