git.libre-soc.org Git - mesa.git/history - src/broadcom/compiler/vir_register

2019-01-14	Eric Anholt	v3d: Add support for CS workgroup/invocation id intrinsics.	blob \| commitdiff \| raw
2018-08-06	Eric Anholt	v3d: Avoid spilling that breaks the r5 usage after...	blob \| commitdiff \| raw \| diff to current
2018-08-06	Eric Anholt	v3d: Wait for TMU writes to complete before continuing...	blob \| commitdiff \| raw \| diff to current
2018-08-06	Eric Anholt	v3d: Add some debug code for forcing register spilling.	blob \| commitdiff \| raw \| diff to current
2018-07-23	Eric Anholt	v3d: Switch to using the new SFU instructions on V3D...	blob \| commitdiff \| raw \| diff to current
2018-07-23	Eric Anholt	v3d: Rotate through registers to improve post-RA schedu...	blob \| commitdiff \| raw \| diff to current
2018-03-19	Eric Anholt	broadcom/vc5: Add support for register spilling.	blob \| commitdiff \| raw \| diff to current
2018-01-13	Eric Anholt	broadcom/vc5: Use THRSW to enable multi-threaded shaders.	blob \| commitdiff \| raw \| diff to current
2018-01-13	Eric Anholt	broadcom/vc5: Use a physical-reg-only register class...	blob \| commitdiff \| raw \| diff to current
2018-01-13	Eric Anholt	broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D...	blob \| commitdiff \| raw \| diff to current
2018-01-13	Eric Anholt	broadcom/vc5: Add support for V3Dv4 signal bits.	blob \| commitdiff \| raw \| diff to current
2017-10-10	Eric Anholt	broadcom: Add VC5 NIR compiler.	blob \| commitdiff \| raw \| diff to current