v3d: Fix detection of the last ldtmu before a new TMU op.
[mesa.git] / src / broadcom / compiler / vir_register_allocate.c
2019-04-26 Eric Anholtv3d: Fix detection of the last ldtmu before a new TMU op.
2019-04-12 Eric Anholtv3d: Use the new lower_to_scratch implementation for...
2019-04-12 Eric Anholtv3d: Replace the old shader-db env var output with...
2019-04-12 Eric Anholtv3d: Add and use a define for the number of channels...
2019-03-05 Eric Anholtv3d: Use ldunif instructions for uniforms.
2019-03-05 Eric Anholtv3d: Add support for register-allocating a ldunif to...
2019-03-05 Eric Anholtv3d: Drop the old class bits splitting up the accumulators.
2019-03-05 Eric Anholtv3d: Do uniform rematerialization spilling before dropp...
2019-03-05 Eric Anholtv3d: Fix temporary leaks of temp_registers and when...
2019-02-26 Eric Anholtv3d: Rematerialize MOVs of uniforms instead of spilling...
2019-01-14 Eric Anholtv3d: Add support for CS workgroup/invocation id intrinsics.
2018-08-06 Eric Anholtv3d: Avoid spilling that breaks the r5 usage after...
2018-08-06 Eric Anholtv3d: Wait for TMU writes to complete before continuing...
2018-08-06 Eric Anholtv3d: Add some debug code for forcing register spilling.
2018-07-23 Eric Anholtv3d: Switch to using the new SFU instructions on V3D...
2018-07-23 Eric Anholtv3d: Rotate through registers to improve post-RA schedu...
2018-03-19 Eric Anholtbroadcom/vc5: Add support for register spilling.
2018-01-13 Eric Anholtbroadcom/vc5: Use THRSW to enable multi-threaded shaders.
2018-01-13 Eric Anholtbroadcom/vc5: Use a physical-reg-only register class...
2018-01-13 Eric Anholtbroadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D...
2018-01-13 Eric Anholtbroadcom/vc5: Add support for V3Dv4 signal bits.
2017-10-10 Eric Anholtbroadcom: Add VC5 NIR compiler.