freedreno/ir3: Avoid {0} initializer for struct reginfo
[mesa.git] / src / freedreno / ir3 / disasm-a3xx.c
2020-05-26 Kristian H. Kristensenfreedreno/ir3: Avoid {0} initializer for struct reginfo
2020-05-26 Eric Anholtfreedreno: Set the immediate flag in a4/a5xx resinfos.
2020-05-26 Eric Anholtfreedreno: Fix printing of unused src in disasm of...
2020-05-04 Eric Anholtfreedreno/ir3: Define the bindful uniform/nonuniform...
2020-05-04 Eric Anholtfreedreno/ir3: Sync some new changes from envytools.
2020-04-27 Eric Anholtfreedreno/ir3: Add support for disasm of cat2 float32...
2020-04-27 Eric Anholtfreedreno/ir3: Refactor out print_reg_src().
2020-04-27 Eric Anholtfreedreno/ir3: Convert remaining disasm src prints...
2020-04-27 Eric Anholtfreedreno/ir3: Print a space after nop counts, like...
2020-04-27 Eric Anholtfreedreno/ir3: Fix the disasm of half-float STG dests.
2020-04-24 Jonathan Marekfreedreno/ir3: fix 16-bit ssbo access
2020-04-15 Connor Abbottir3: Fix LDC offset units
2020-04-13 Rob Clarkfreedreno/ir3: spiff out disasm a bit
2020-04-09 Connor Abbottir3: Add bindless instruction encoding
2020-02-07 Hyunjun Kofreedreno/ir3: fix printing half constant registers.
2020-01-15 Rob Clarkfreedreno/ir3: rename instructions
2019-11-09 Rob Clarkfreedreno/ir3: sync disasm changes from envytools
2019-11-08 Kristian H. Kristensenfreedreno/ir3: Add new synchronization opcodes
2019-11-08 Kristian H. Kristensenfreedreno/a6xx: Add register offset for STG/LDG
2019-10-18 Rob Clarkfreedreno/ir3: rename mul.s/mul.u
2019-04-25 Rob Clarkfreedreno/ir3: fix rgetpos decoding
2019-03-21 Rob Clarkfreedreno/ir3: fix sam.s2en decoding
2019-03-21 Rob Clarkfreedreno/ir3 better cat6 encoding detection
2019-02-20 Rob Clarkfreedreno/ir3: sync instr/disasm and add ldib encoding
2018-12-07 Rob Clarkfreedreno/ir3: sync instr/disasm
2018-11-27 Rob Clarkfreedreno: move ir3 to common location