intel/disasm: Label support in shader disassembly for UIP/JIP
[mesa.git] / src / intel / compiler / brw_disasm.c
2020-09-02 Danylo Piliaievintel/disasm: Label support in shader disassembly for...
2020-09-02 Danylo Piliaievintel/disasm: Change visibility of has_uip and has_jip
2020-07-02 Timothy Arceriintel/compiler: add and fix up fallthrough comments...
2020-05-30 Jason Ekstrandintel/fs: Emit HALT for discard on Gen4-5
2020-02-18 Caio Marcelo de... intel/gen12: Take into account opcode when decoding...
2020-01-24 Jason Ekstrandintel/disasm: Properly disassemble indirect SENDs
2020-01-22 Matt Turnerintel/compiler: Don't disassemble align1 3-src operands...
2020-01-08 Jason Ekstrandintel/disasm: Fix decoding of src0 of SENDS
2019-10-22 Sagar Ghugeintel/compiler: Refactor disassembly of sources in...
2019-10-11 Francisco Jerezintel/disasm: Disassemble register file of split SEND...
2019-10-11 Francisco Jerezintel/disasm: Don't disassemble saturate control on...
2019-10-11 Francisco Jerezintel/disasm/gen12: Disassemble Gen12 SEND instructions.
2019-10-11 Francisco Jerezintel/disasm/gen12: Disassemble Gen12 SYNC instruction.
2019-10-11 Francisco Jerezintel/disasm/gen12: Disassemble three-source instructio...
2019-10-11 Francisco Jerezintel/disasm/gen12: Fix disassembly of some common...
2019-10-11 Francisco Jerezintel/disasm/gen12: Disassemble software scoreboard...
2019-10-11 Francisco Jerezintel/eu: Split brw_inst ex_desc accessors for SEND...
2019-05-07 Sagar Ghugeintel/disasm: Disassemble immediate value properly...
2019-05-07 Sagar Ghugeintel/disasm: Disassemble JIP offset for while
2019-05-07 Sagar Ghugeintel/compiler: Print quad value in hex format
2019-02-01 Jason Ekstrandintel/fs: Implement nir_intrinsic_global_atomic_*
2019-02-01 Jason Ekstrandintel/fs: Implement load/store_global with A64 untyped...
2019-01-29 Jason Ekstrandintel/disasm: Properly disassemble split sends
2019-01-29 Jason Ekstrandintel/disasm: Rework SEND decoding to use descriptors
2018-12-10 Sagar Ghugeintel/compiler: Always print flag subregister number
2018-11-15 Sagar Ghugeintel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_...
2018-10-26 Sagar Ghugeintel/compiler: Print message descriptor as immediate...
2018-10-26 Sagar Ghugeintel/compiler: Print hex representation along with...
2018-08-23 Ian Romanickintel/compiler: Implement untyped atomic float min...
2018-08-23 Ian Romanickintel/compiler: Expand untyped atomic message type...
2018-08-23 Ian Romanickintel/compiler: Silence unused parameter warnings
2018-03-08 Kenneth Graunkei965/fs: Add infrastructure for generating CSEL instruc...
2018-02-28 Matt Turnerintel/compiler: Add Gen11+ native float type
2018-02-10 Grazvydas Ignotasintel/compiler: fix 64bit value prints on 32bit
2017-10-20 Matt Turneri965: Add align1 ternary instruction disassembler support
2017-10-20 Matt Turneri965: Add align1 ternary instruction support to convers...
2017-10-20 Matt Turneri965: Rename brw_inst's functions that access the 3src...
2017-10-20 Matt Turneri965: Rename brw_inst 3src functions in preparation...
2017-10-20 Matt Turneri965: Print subreg in units of type-size on ternary...
2017-10-04 Matt Turneri965: Fix support for disassembling 64-bit integer...
2017-08-21 Matt Turneri965: Stop using hardware register types directly
2017-08-21 Matt Turneri965: Add brw_hw_reg_type_to_letters() and use it in...
2017-08-21 Matt Turneri965: Rename brw_inst's functions that access the regis...
2017-08-21 Matt Turneri965: Reverse file/type arguments to register type...
2017-08-21 Matt Turneri965: Add support for disassembling 64-bit integer...
2017-08-21 Matt Turneri965: Use separate enums for register vs immediate...
2017-08-02 Matt Turneri965: Fix indentation
2017-05-26 Jason Ekstrandintel/compiler: Make brw_disasm take const assembly
2017-04-14 Iago Toral Quirogai965/disasm: also print nibctrl in IVB for execsize=8
2017-03-13 Jason Ekstrandi965: Move the back-end compiler to src/intel/compiler