git.libre-soc.org Git - mesa.git/history - src/intel/genxml/gen10.xml

2018-01-09	Kenneth Graunke	genxml: Add missing INSTDONE_1 bits on Gen7.5+.	blob \| commitdiff \| raw
2017-11-14	Anuj Phogat	intel/genxml: Add Cache Mode SubSlice Register to gen10.xml	blob \| commitdiff \| raw \| diff to current
2017-08-15	Scott D Phillips	intel/genxml: Fix gen10 BLEND_STATE variable length...	blob \| commitdiff \| raw \| diff to current
2017-07-01	Lionel Landwerlin	intel: genxml: make a couple of enums show up in aubinator	blob \| commitdiff \| raw \| diff to current
2017-06-22	Anuj Phogat	intel/genxml: Add Gen10 CACHE_MODE_1 definitions	blob \| commitdiff \| raw \| diff to current
2017-06-22	Anuj Phogat	intel/genxml: Rename StartInstanceLocation to StartingI...	blob \| commitdiff \| raw \| diff to current
2017-06-22	Anuj Phogat	intel/genxml: Rename IndirectStatePointer to BorderColo...	blob \| commitdiff \| raw \| diff to current
2017-06-22	Anuj Phogat	intel/genxml: Combine DataDWord{0, 1} fields in to...	blob \| commitdiff \| raw \| diff to current
2017-06-22	Anuj Phogat	intel/genxml: Add INSTDONE registers in gen10	blob \| commitdiff \| raw \| diff to current
2017-06-22	Anuj Phogat	intel/genxml: Add better support for MI_MATH in gen10	blob \| commitdiff \| raw \| diff to current
2017-06-09	Jason Ekstrand	i965/genxml: Add gen10.xml	blob \| commitdiff \| raw \| diff to current