spirv: Use nir_bany/ball for OpAny/All

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5278>

spirv: Clean up OpSignBitSet

For some reason, we were doing a signed shift vectors and an unsigned
shift for scalars.  We then plug it into i2b so it should make no
difference whatsoever.  The fact that we're doing different things for
vectors vs. scalars is bonkers.  Let's simplify the code a bit.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5278>

spirv: Fix indentation in vtn_handle_ptr

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5278>

spirv: Drop the void *ptr from vtn_value

It isn't being used for anything.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5278>

spirv: Simplify our handling of NonUniform

The original implementation of SPV_EXT_descriptor_indexing was extremely
paranoid about the NonUniform qualifier, trying to fetch it from every
possible location and propagate it through access chains etc.  However,
the Vulkan spec is quite nice to us on this and has very strict rules
for where the NonUniform decoration has to be placed.  For image and
texture operations, we can search for the decoration on the spot when we
process the image or texture op.  For pointers, we continue putting it
on the pointer but we don't bother trying to do anything silly like
propagate it through casts.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5278>

nir/vtn: Add support for 8 and 16 vector ball/bany

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6030>

nir: Support 8 and 16 component vectors for reduceable intrinsics

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6030>

nir: Support algebraic opts on vectors larger than 4

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6030>

nir: Support vec8/vec16 in nir_lower_bit_size

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6030>

freedreno: sync registers from envytools

Pull in a bunch of fixes and updates.. mostly using varset correctly,
and fixes for implicit bools.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6052>

tu: Enable VK_EXT_depth_clip_enable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6047>

aco: ensure readfirstlane subdword operands are always dword aligned

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6024>

aco: prevent infinite recursion in RA for subdword variables

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6024>

aco: don't split store data if it was already split into more elements

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6024>

aco: ensure to not extract more components than have been fetched

Fixes: 7015d2c249e1f7814bf5681ccd049e49e4d6495c ('aco: fix scratch loads which cross element_size boundaries')
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6024>

radv: Add timeline syncobj for timeline semaphores.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>

radv: Add winsys functions for timeline syncobj.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>

radv: Add winsys support for submitting timeline syncobj.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>

radv: Add thread for timeline syncobj submission.

For cross-process timelines we have to have a thread to wait
till the requested points become available.

The functions actually dealing with timeline semaphores stubbed out, to
implement in the next patch. As such the thread code shouldn't trigger
yet.

The core idea is that we still use the refcount mechanism that we use with
emulated timelines, though the native timeline syncobj don't participate
in the refcounting. This way we keep the ordering of submission in a queue
as each submission is also blocked by its predecessor.

Where we change behavior is when the number of blockers reaches 0. In the
new code we check if we need to wait for the timeline semaphores to
be available and if so we won't execute the submission immediately but
pass it to the submission thread.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>

radv/winsys: Add binary syncobj ABI changes for timeline semaphores.

To facilitate cross-process timeline semaphores we have to deal with
the fact that the syncobj signal operation might be submitted a
small finite time after the wait operation.

For that we start using DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT during
the wait operation so we properly wait instead of returning an error.

Furthermore, to make this effective for syncobjs that get reused we
actually have to reset them after the wait. Otherwise the wait before
submit would get the previous fence instead of waiting for the new
thing to submit.

The obvious choice, resetting the syncobj after the CS submission
has 2 issues though:

1) If the same semaphore is used for wait and signal we can't reset it.
   This is solvable by only resetting the semaphores that are not in the
   signal list.
2) The submitted work might be complete before we get to resetting the
   syncobj. If there is a cycle of submissions that signals it again and
   finishes before we get to the reset we are screwed.

Solution:
Copy the fence into a new syncobj and reset the old syncobj before
submission. Yes I know it is more syscalls :( At least I reduced the
alloc/free overhead by keeping a cache of temporary syncobjs.

This also introduces a syncobj_reset_count as we don't want to reset
syncobjs that are part of an emulated timeline semaphore. (yes, if
the kernel supports timeline syncobjs we should use those instead,
but those still need to be implemented and if we depend on them in
this patch ordering dependencies get hard ...)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>

amd: Add detection of timeline semaphore support.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>

nir/ lower_int_to_float: Handle umax and umin

8e1b75b3 introduced umax/umin in order to lower iand/ior for (n)eq zero.
That breaks the lower_int_to_float pass, because umax and umin weren't
handled there.

Tested with lima. The other users of nir_lower_int_to_float
(etnaviv, freedreno) should also have that issue.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6043>

ci: Use half as many parallel softpipe / virgl test jobs

We're now using at least twice as many CPU cores per job (on shared
runners), so they only take about half as long, and should still be
under 10 minutes.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6011>

ci: Do not mark container / pages jobs as interruptible

If another MR was merged while these were still running for the main
project, the result could be no updated images in the main project
registry (forcing a rebuild of the new images in all forked projects) or
an outdated Mesa website.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6011>

ci: Use FDO_CI_CONCURRENT in run-shader-db.sh as well

Noticed while checking job logs for it being used elsewhere.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6011>

ci: Namespace trace artifacts to the job number

Put artifacts in a per-job folder, because if a job is retried then it
will try to upload a file to the same key and fail with the following
error:

403 Client Error: Forbidden for url:
https://minio-packet.freedesktop.org/artifacts/daenzer/mesa/180609/gl-panfrost-t860/results.yml

Also, to prevent in the future similar clashes if several trace files
share the same name, upload the images with their checksums as their
names. This will also make it easier to fetch images for comparison with
the references.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6029>

nir_ allow nir_lower_clip_halfz to run in tess eval shader

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6027>

nir: allow lower_psiz_mov to run in tessellation stages

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6027>

Revert "llvmpipe: Use the default behavior of ALLOW_MAPPED_BUFFERS."

This reverts commit 6ec49066498097c2647d030ebe1b99a00bc38734.

This broke:
GTF-GL45.gtf21.GL3Tests.texture_lod_bias.*

not sure why but revert for now.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6042>

llvmpipe/ms: fix sign extension bug in rasterizer.

/glcts --deqp-surface-width=1024 --deqp-surface-height=64  --deqp-case=KHR-GL45.texture_view.view_sampling  --deqp-surface-type=fbo
was failing but only for width 1024.

The test was filling a 4x4 ms texture, but leaving the viewport set to 1024x64.

This was resulting in this code incorrectly sign extending a value, and passing
it into the mask generator and getting the wrong values. Explicit cast
avoids the sign extension and fixes the above test.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6006>

intel/ir/gen12+: Work around FS performance regressions due to SIMD32 discard divergence.

This avoids some performance regressions on Gen12 platforms caused by
SIMD32 fragment shaders reported in titles like Dota2, TF2, Xonotic,
and GFXBench5 Car Chase and Aztec Ruins.

The most obvious pattern in the regressing shaders I identified among
these workloads is that they all had non-uniform discard statements,
which are handled rather optimistically by the current IR analysis
pass: No penalty is currently applied to the SIMD32 variant of the
shader in the form of differing branching weights like we do for other
control flow instructions in order to account for the greater
likelihood of divergence of a SIMD32 shader.

Simply changing that by giving the same treatment to discard
statements as we give to other branching instructions seemed to hurt
more than it helped on platforms earlier than Gen12, since it reversed
most of the improvement obtained from SIMD32 fragment shaders in
Manhattan for no measurable benefit in other workloads (Manhattan has
a handful of shaders with statically non-uniform discard statements
which actually perform better in SIMD32 mode due to their approximate
dynamic uniformity).  For that reason this change is applied to Gen12+
platforms only.

I've been running a number of tests trying to understand the
difference in behavior between Gen12 and earlier platforms, and most
of the evidence I've gathered seems to point at EU fusion being the
culprit: Unlike previous generations, on Gen12 EUs are arranged in
pairs which execute instructions in lockstep, giving an effective warp
size of 64 threads in SIMD32 mode, which seems to increase the
likelihood for control flow divergence in some of the affected shaders
significantly.

Fixes: 188a3659aea6dec9acf1 "intel/ir: Import shader performance analysis pass."
Reported-by: Caleb Callaway <caleb.callaway@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5910>

glx: Fix build and warnings with -Dglx=dri -Dglx-direct=false

Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5958>

softpipe: Enable PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS;

tgsi_exec.c uses the generic src load path for indirects, so we don't
actually need addr regs.  Saves extra intructions.

shader-db results:
total instructions in shared programs: 3346685 -> 3249052 (-2.92%)
instructions in affected programs: 961832 -> 864199 (-10.15%)

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6018>

softpipe: Enable PIPE_CAP_TGSI_TEXCOORD.

The tgsi_exec path can handle it, and otherwise when we start using NIR
our MAX_VARYINGS value will cause us to have VARYING_SLOT_VARx above the
maximum.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6018>

softpipe: Add support for reporting shader-db output.

In doing the softpipe NIR and NIR-to-TGSI transition, I want to make sure
I don't make shaders significantly worse, so I need shader-db output.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6018>

softpipe: Convert to comma-separated SOFTPIPE_DEBUG for debug options.

This makes us more like other drivers, and avoids having tons of different
names (particularly when you want to dump vs and fs in debugging).  In the
process, having a debug flag for vertex shaders just falls out.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6018>

softpipe: Refactor pipe_shader_state setup.

We had repeated code that I want to repeatedly change for adding
nir-to-tgsi.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6018>

llvmpipe: enable robust buffer access + GL 4.3, GLES 3.2 and robust buffer access behaviour

Turning on robust buffer access enables GLES 3.2, also
finished GL 4.3 support.

The post depth coverage fail is expected, it's a test bug
This also introduce a fail in the invalid flag test that I can't reproduce out of CI.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5971>

llvmpipe: add device reset query context hook.

Add the device reset query hook needed for robustness

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5971>

glx/drisw: add robustness support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5971>

drisw: add robustness extension support.

Port the code from dri2 so that drisw drivers can support the
robustness extension

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5971>

llvmpipe/draw: handle constant buffer limits and robustness (v1.1)

TGSI expect vec4 of constants for it's current code paths, and when
doing indirect accesses it does the comparison on vec4 indexes,
however NIR does the indexing on packed float indexes.

This also align the compute path with the other shaders, and
should improve robustness (at least under Vulkan)

Fixes:
KHR-NoContext.gl43.robust_buffer_access_behavior.uniform_buffer

v1.1:
rename variable to something more meaningful (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5971>

llvmpipe: enable EXT_texture_shadow_lod

The driver passes all the CTS tests for this.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5971>

nir/lower_io: Add support for global scratch addressing

This provides an alternate lowering for scratch in which it uses global
reads/writes and bases scratch addresses on a base pointer.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5927>

nir/lower_io: Use b2b for shader and function temporaries

This way we can avoid some unnecessary conversions because there's no
need to sanitize to 0/1 for scratch.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5927>

nir/lower_io: Choose to set access based on intrinsic metadata

This should be far more reliable than trying to keep opcode lists
up-to-date.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5927>

nir: Allow for system values with variable numbers of destination components

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5927>

docs/releasing: improve wording

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5833>

bin/gen_release_notes: automatically commit release notes

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5833>

post_version.py: fix relnotes links

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5928>

post_version.py: update the files in the current worktree, not the one with the script that we run

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5928>

post_version.py: stop using non-existent functions and fix commit message

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5928>

post_version.py: drop incorrect conf.py changes

This needs to be done in the mesa3d.org repo; see
https://gitlab.freedesktop.org/mesa/mesa3d.org/-/merge_requests/19

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5928>

post_version.py: don't generate relnotes twice

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5928>

docs: update calendar and link releases notes for 20.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6034>

docs: add release notes for 20.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6034>

gitlab-ci: Test AMD's Raven with traces

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6014>

i915: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.
The exception is the texel/gather offsets and stream output
components, which will not be exposed since we don't expose the
corresponding GLSL version.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

svga: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

swr: Use the default behavior of ALLOW_MAPPED_BUFFERS.

Since this is a software rasterizer, we really don't care whether the
buffers are "mapped" since it's just malloc.  This will drop a bit of
pointless CPU overhead to throw errors.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

swr: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

virgl: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by Gert Wollny <gert.wollny@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

softpipe: Use the default behavior of ALLOW_MAPPED_BUFFERS.

Since this is a software rasterizer, we really don't care whether the
buffers are "mapped" since it's just malloc.  This will drop a bit of
pointless CPU overhead to throw errors.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

softpipe: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

llvmpipe: Use the default behavior of ALLOW_MAPPED_BUFFERS.

Since this is a software rasterizer, we really don't care whether the
buffers are "mapped" since it's just malloc.  This will drop a bit of
pointless CPU overhead to throw errors.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

llvmpipe: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who uses a cap.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3298>

ci: Fix the overwriting of traces.yml for baremetal

When the lava files were moved out of the container, this stopped
working which caused the traces job for Freedreno to not run any traces
at all.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes: dcd171f5e9bd ("gitlab-ci: More stable URL for kernel and ramdisk artifacts, for LAVA")
Acked-by: Andres Gomez <agomez@igalia.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6021>

ci: Update checksums for freedreno traces.

Hand-verified by looking at our artifacts compared to an i965 capture I
had.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6021>

radeon/vcn: increase render_pic_list size

Increase the maximum number of possible decoder reference picture
frames from 16 to 32.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6016>

radeonsi: enable preemption if the kernel enabled it

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: set up IBs for preemption

- Execute cs_preamble_state as a separate IB with different flags.
- Set the PREEMPT flag for the main IB.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: don't restore states at the beginning of IBs if they're shadowed

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: add debug code for register shadowing

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: add reg shadowing codepaths to GS and tess ring setup

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: implement CP register shadowing

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: reorder code in update_gs_ring_buffers and init_tess_factor_ring

to reduce the churn when adding codepaths for shadowed registers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: make cs_preamble_state optional

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

winsys/amdgpu: make amdgpu_bo_unmap non-static

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

ac: add tables for CP register shadowing

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

ac: add helper ac_get_register_name

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: sort registers in si_init_cs_preamble_state according to GPU gen

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: sort registers in si_emit_initial_compute_regs according to GPU gen

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING

Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7f82b4f16fbcbb05a1ae47f7930e189 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

radeonsi: add missing initialization of registers

(random initial gfx10 commit:)
Fixes: 78cdf9a99f0 - amd/addrlib: add gfx10 support
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

docs: add some very basic documentation about zink

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5967>

radv/winsys: be more robust when a CS failed during recording

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5872>

radv/winsys: return a Vulkan error code when binding virtual buffers/images

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5872>

radv/winsys: remove useless check when binding virtual buffers/images

Size must be greater than 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5872>

radv/winsys: check more allocation failures

While we are at it, use local variables first to make sure to
not leak memory if something bad happens.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5872>

radv: add missing return values check for some winsys calls

Make sure to handle errors properly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5872>

nir/tests: Add tests for opt_if_simplification

Test cases:

opt_if_simplification - the most trivial test case.

opt_if_simplification_single_source_phi_after_if - tests that
opt_if_simplification correctly handles single-source phis after
the if, found in https://gitlab.freedesktop.org/mesa/mesa/-/issues/3282

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5945>

nir/opt_if: Fix opt_if_simplification when else branch has jump

Consider the following case:

 if ssa_1 {
    block block_2:
    /* succs: block_4 */
 } else {
    block block_3:
    ...
    break
    /* succs: block_5 */
 }

 block block_4:
 vec1 32 ssa_100 = phi block_2: ssa_2

After block_3 extraction and reinsertion, phi->pred becomes invalid
and isn't updated by reinsertion since it is unreachable from block_3.

Call nir_opt_remove_phis_block before moving block to eliminate single
source phis after the if.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3282
Fixes: e3e929f8c342b32dc8f5296adf8fb337866fa40a
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5945>

zink: omit Lod image operand in ntv when not using an image texture dim

according to spec, this is invalid (and it's not being used anyway)

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>

zink: add some asserts for building access chains in ntv

we're never going to pass a 0 here, and it's going to be an error if we do

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>

zink: handle texelFetchOffset with offsets

we need to explicitly add the offset in this case since it's not available
as a spirv param

fixes spec@glsl-1.30@execution@fs-texelfetchoffset-2d

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>

zink: use helper function to handle uvec/bvec types

bit_size of 1 means we use a bool type here, 32 means uint, so we can just
handle that automatically for all relevant cases

ref shaders@glsl-vs-continue-in-switch-in-do-while

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>

aco: fix scratch loads which cross element_size boundaries

Previously, we've set element_size == 16 which causes loads from
packed vec3 arrays to cross the boundary and return wrong data.
This patch sets element_size = 4 and splits loads into single channel.
Fixes all of dEQP-VK.subgroups.ballot_broadcast.*

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5977>

mesa/program: fix shadow property for samplers

When creating a sampler-type, we need to pass the correct vaclue for
the "is_shadow"-parameter to glsl_sampler_type(), otherwise the compiler
backend will have no clue about this being a shadow-sampler.

Fixes: 1c0f92d8a8c ("nir: Create sampler variables in prog_to_nir.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5986>

ci: Disable trace testing on Mali T760

The machine is showing random mis-renderings and we don't have time now
to investigate. Comment it out for now so CI pipelines don't fail due to
it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6023>

radv: advertise VK_EXT_shader_atomic_float

No hw support for float atomic add for buffer and (sparse) images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6000>