mesa.git
3 years agomeson: Be a bit more helpful when arch or OS is unknown
Guido Günther [Sun, 26 Aug 2018 20:23:59 +0000 (22:23 +0200)]
meson: Be a bit more helpful when arch or OS is unknown

V2: Add one missing @0@

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agointel/eu: print bytes instead of 32 bit hex value
Sagar Ghuge [Mon, 27 Aug 2018 17:23:19 +0000 (10:23 -0700)]
intel/eu: print bytes instead of 32 bit hex value

INTEL_DEBUG=hex prints 32 bit hex value and due to endianness of CPU
byte order is reversed. In order to disassemble binary files, print
each byte instead of 32 bit hex value.

v2: Print blank spaces in order to vertically align output of compacted
    instructions hex value with uncompacted instructions hex value.
    (Matt Turner)

v3: Fix line wrap at correct length

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel: decoder: handle 0 sized structs
Lionel Landwerlin [Sat, 25 Aug 2018 17:22:00 +0000 (18:22 +0100)]
intel: decoder: handle 0 sized structs

Gen7.5 has a BLEND_STATE of size 0 which includes a variable length
group. We did not deal with that very well, leading to an endless
loop.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107544
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonv50/ir,nvc0: use constant buffers for compute when possible on Kepler+
Rhys Perry [Fri, 3 Aug 2018 21:11:28 +0000 (22:11 +0100)]
nv50/ir,nvc0: use constant buffers for compute when possible on Kepler+

Gives a +7.79% increase in FPS with Hitman on lowest quality settings on
my GTX 1060.

total instructions in shared programs : 5787979 -> 5748677 (-0.68%)
total gprs used in shared programs    : 669901 -> 669373 (-0.08%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21068 -> 21064 (-0.02%)

                local     shared        gpr       inst      bytes
    helped           1           0         152         274         274
      hurt           0           0           0           0           0

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agonv50/ir: optimize multiplication by 16-bit immediates into two xmads
Rhys Perry [Sat, 18 Aug 2018 14:06:50 +0000 (15:06 +0100)]
nv50/ir: optimize multiplication by 16-bit immediates into two xmads

Rather than the usual three that would be created.

total instructions in shared programs : 5796385 -> 5786560 (-0.17%)
total gprs used in shared programs    : 670103 -> 669968 (-0.02%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21164 -> 21068 (-0.45%)

                local     shared        gpr       inst      bytes
    helped           1           0          64        1040        1040
      hurt           0           0          27           0           0

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agonv50/ir: optimize near power-of-twos into shladd
Rhys Perry [Sat, 18 Aug 2018 14:06:01 +0000 (15:06 +0100)]
nv50/ir: optimize near power-of-twos into shladd

total instructions in shared programs : 5819319 -> 5796385 (-0.39%)
total gprs used in shared programs    : 670571 -> 670103 (-0.07%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21164 -> 21164 (0.00%)

                local     shared        gpr       inst      bytes
    helped           0           0         318        1758        1758
      hurt           0           0          63           0           0

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agonv50/ir: move a * b -> a << log2(b) code into createMul()
Rhys Perry [Wed, 13 Jun 2018 15:30:01 +0000 (16:30 +0100)]
nv50/ir: move a * b -> a << log2(b) code into createMul()

With this commit, OP_MAD is handled on nv50 too. This commit is also
useful for later commits.

Also, instead of creating a shladd, it relies on LateAlgebraicOpt to
create one. This simplifies the code and helps shader-db slightly overall.

total instructions in shared programs : 5820882 -> 5819319 (-0.03%)
total gprs used in shared programs    : 670595 -> 670571 (-0.00%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21164 -> 21164 (0.00%)

                local     shared        gpr       inst      bytes
    helped           0           0          18         230         230
      hurt           0           0           8         263         263

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agonv50/ir: optimize imul/imad to xmads
Rhys Perry [Wed, 13 Jun 2018 15:25:23 +0000 (16:25 +0100)]
nv50/ir: optimize imul/imad to xmads

This hits the shader-db numbers a good bit, though a few xmads is way
faster than an imul or imad and the cost is mitigated by the next commit,
which optimizes many multiplications by immediates into shorter and less
register heavy instructions than the xmads.

total instructions in shared programs : 5768871 -> 5820882 (0.90%)
total gprs used in shared programs    : 669919 -> 670595 (0.10%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21068 -> 21164 (0.46%)

                local     shared        gpr       inst      bytes
    helped           0           0          38           0           0
      hurt           1           0         365        3076        3076

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agogm107/ir: add support for OP_XMAD on GM107+
Rhys Perry [Wed, 13 Jun 2018 15:21:56 +0000 (16:21 +0100)]
gm107/ir: add support for OP_XMAD on GM107+

v4: make the immediate field 16 bits
v5: don't ever emit h1 flags for immediates

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agonv50/ir: add preliminary support for OP_XMAD
Rhys Perry [Wed, 13 Jun 2018 15:21:20 +0000 (16:21 +0100)]
nv50/ir: add preliminary support for OP_XMAD

v4: remove uint16_t(...)
v4: don't allow immediates outside [0,65535] in insnCanLoad()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
3 years agoglsl/linker: Allow unused in blocks which are not declated on previous stage
vadym.shovkoplias [Thu, 23 Aug 2018 10:12:16 +0000 (13:12 +0300)]
glsl/linker: Allow unused in blocks which are not declated on previous stage

>From Section 4.3.4 (Inputs) of the GLSL 1.50 spec:

    "Only the input variables that are actually read need to be written
     by the previous stage; it is allowed to have superfluous
     declarations of input variables."

Fixes:
    * interstage-multiple-shader-objects.shader_test

v2:
  Update comment in ir.h since the usage of "used" field
  has been extended.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101247
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agonir: Pull block_ends_in_jump into nir.h
Jason Ekstrand [Fri, 24 Aug 2018 14:34:05 +0000 (09:34 -0500)]
nir: Pull block_ends_in_jump into nir.h

We had two different implementations in different files.  May as well
have one and put it in nir.h.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv: Add support for protected memory properties on anv_GetPhysicalDeviceProperties2()
Samuel Iglesias Gonsálvez [Fri, 24 Aug 2018 10:11:49 +0000 (12:11 +0200)]
anv: Add support for protected memory properties on anv_GetPhysicalDeviceProperties2()

VkPhysicalDeviceProtectedMemoryProperties structure is new on Vulkan 1.1.

Fixes Vulkan CTS CL#2849.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agointel/tools: Add 0x in front of a couple of hex values
Jason Ekstrand [Sat, 25 Aug 2018 22:34:17 +0000 (17:34 -0500)]
intel/tools: Add 0x in front of a couple of hex values

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agoanv: Fill holes in the VF VUE to zero
Jason Ekstrand [Sat, 25 Aug 2018 22:08:04 +0000 (17:08 -0500)]
anv: Fill holes in the VF VUE to zero

This fixes a GPU hang in DOOM 2016 running under wine.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104809
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agointel: tools: Fix aubinator_error's fprintf call (format-security)
Kai Wasserbäch [Sat, 25 Aug 2018 10:00:30 +0000 (12:00 +0200)]
intel: tools: Fix aubinator_error's fprintf call (format-security)

The recent commit 4616639b49b4bbc91e503c1c27632dccc1c2b5be introduced
the new function aubinator_error() which is a trivial wrapper around
fprintf() to STDERR. The call to fprintf() however is passed the message
msg directly:
  fprintf(stderr, msg);

This is a format-security violation and leads to an FTBFS with
-Werror=format-security (GCC 8):
  ../../../src/intel/tools/aubinator.c: In function 'aubinator_error':
  ../../../src/intel/tools/aubinator.c:74:4: error: format not a string literal and no format arguments [-Werror=format-security]
      fprintf(stderr, msg);
      ^~~~~~~

This patch fixes this trivially by introducing a catch-all "%s" format
argument.

Fixes: 4616639b49b ("intel: tools: split aub parsing from aubinator")
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agointel/batch_decoder: Print blend states properly
Jason Ekstrand [Fri, 24 Aug 2018 21:05:08 +0000 (16:05 -0500)]
intel/batch_decoder: Print blend states properly

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agointel/batch_decoder: Fix dynamic state printing
Jason Ekstrand [Fri, 24 Aug 2018 21:04:03 +0000 (16:04 -0500)]
intel/batch_decoder: Fix dynamic state printing

Instead of printing addresses like everyone else, we were accidentally
printing the offset from state base address.  Also, state_map is a void
pointer so we were incrementing in bytes instead of dwords and every
state other than the first was wrong.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agointel/decoder: Print ISL formats for vertex elements
Jason Ekstrand [Fri, 24 Aug 2018 20:27:38 +0000 (15:27 -0500)]
intel/decoder: Print ISL formats for vertex elements

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agointel/decoder: Clean up field iteration and fix sub-dword fields
Jason Ekstrand [Fri, 24 Aug 2018 20:23:04 +0000 (15:23 -0500)]
intel/decoder: Clean up field iteration and fix sub-dword fields

First of all, setting iter->name in advance_field is unnecessary because
it gets set by gen_decode_field which gets called immediately after
gen_decode_field in the one call-site.  Second, we weren't properly
initializing start_bit and end_bit in the initial condition of
gen_field_iterator_next so the first field of a struct would get printed
wrong if it doesn't start on the first bit.  This is fixed by adding a
iter_start_field helper which sets the field and also sets up the other
bits we need.  This fixes decoding of 3DSTATE_SBE_SWIZ.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agogallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.
Kenneth Graunke [Sun, 24 Jun 2018 00:26:47 +0000 (17:26 -0700)]
gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.

Some hardware can do PIPE_TEX_WRAP_MIRROR_REPEAT but not
PIPE_TEX_WRAP_MIRROR_CLAMP and PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER.

Drivers for such hardware would like to advertise support for
ARB_texture_mirror_clamp_to_edge but not EXT_texture_mirror_clamp.

This commit adds a new PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE bit,
changes the extension enable to be based on that, and enables it
in all upstream drivers which supported PIPE_CAP_TEXTURE_MIRROR_CLAMP
(so they continue supporting this mode).

3 years agointel: decoder: unify MI_BB_START field naming
Lionel Landwerlin [Tue, 14 Aug 2018 10:22:12 +0000 (11:22 +0100)]
intel: decoder: unify MI_BB_START field naming

The batch decoder looks for a field with a particular name to decide
whether an MI_BB_START leads into a second batch buffer level. Because
the names are different between Gen7.5/8 and the newer generation we
fail that test and keep on reading (invalid) instructions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107544
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agodocs: Update calendar, news, relnotes for 18.1.7
Dylan Baker [Fri, 24 Aug 2018 16:35:24 +0000 (09:35 -0700)]
docs: Update calendar, news, relnotes for 18.1.7

3 years agodocs: Add mesa 18.1.7 notes
Dylan Baker [Fri, 24 Aug 2018 16:29:07 +0000 (09:29 -0700)]
docs: Add mesa 18.1.7 notes

3 years agodocs: Add mesa 18.1.7 docs
Dylan Baker [Thu, 23 Aug 2018 16:39:20 +0000 (09:39 -0700)]
docs: Add mesa 18.1.7 docs

3 years agodocs: update calendar 18.2.0-rc4 is out, extend to 18.2.0-rc5
Andres Gomez [Fri, 24 Aug 2018 15:58:00 +0000 (18:58 +0300)]
docs: update calendar 18.2.0-rc4 is out, extend to 18.2.0-rc5

Signed-off-by: Andres Gomez <agomez@igalia.com>
3 years agodocs/relnotes: Mark NV_fragment_shader_interlock support in i965
Kevin Rogovin [Fri, 24 Aug 2018 06:00:46 +0000 (09:00 +0300)]
docs/relnotes: Mark NV_fragment_shader_interlock support in i965

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoegl/drm: use gbm_dri_bo() wrapper
Emil Velikov [Thu, 9 Aug 2018 14:13:07 +0000 (15:13 +0100)]
egl/drm: use gbm_dri_bo() wrapper

Remove the explicit cast, using the appropriate wrapper instead.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
3 years agoegl/drm: use gbm_dri_surface() wrapper
Emil Velikov [Thu, 9 Aug 2018 14:11:38 +0000 (15:11 +0100)]
egl/drm: use gbm_dri_surface() wrapper

Remove the explicit cast, using the appropriate wrapper instead.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
3 years agoegl/drm: use gbm_dri_device() wrapper
Emil Velikov [Thu, 9 Aug 2018 14:05:58 +0000 (15:05 +0100)]
egl/drm: use gbm_dri_device() wrapper

Remove the explicit cast, using the appropriate wrapper instead.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
3 years agoegl/android: simplify device open/probe
Emil Velikov [Wed, 8 Aug 2018 14:40:56 +0000 (15:40 +0100)]
egl/android: simplify device open/probe

Currently droid_probe_device, does not do any 'probing' but filtering
out a device if it doesn't match the vendor string given.

Rename the function, straighten the return type and call it only as
needed - an actual vendor string is provided.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
3 years agoegl/android: remove drmVersion::name NULL check
Emil Velikov [Wed, 8 Aug 2018 14:13:20 +0000 (15:13 +0100)]
egl/android: remove drmVersion::name NULL check

The name string is guaranteed to be non-NULL.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
3 years agoegl/android: remove droid_probe_driver()
Emil Velikov [Wed, 8 Aug 2018 14:05:56 +0000 (15:05 +0100)]
egl/android: remove droid_probe_driver()

The function name is misleading - it effectively checks if
loader_get_driver_for_fd fails. Which can happen only only on strdup
error - a close to impossible scenario.

Drop the function - we call the loader API at at later stage.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
3 years agoegl/android: use strcmp with drmVersion::name
Emil Velikov [Wed, 8 Aug 2018 13:56:00 +0000 (14:56 +0100)]
egl/android: use strcmp with drmVersion::name

The name string is guaranteed to be NULL terminated. Drop the explicit
length check that comes with strncmp().

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
3 years agoegl/android: use drmDevice instead of the manual /dev/dri iteration
Emil Velikov [Wed, 8 Aug 2018 13:19:05 +0000 (14:19 +0100)]
egl/android: use drmDevice instead of the manual /dev/dri iteration

Replace the manual handling of /dev/dri in favor of the drmDevice API.
The latter provides a consistent way of enumerating the devices,
providing device details as needed.

v2:
 - Use ARRAY_SIZE (Frank)
 - s/famour/favor/ typo (Frank)
 - Make MAX_DRM_DEVICES a macro - fix vla errors (RobF)
 - Remove left-over dev_path instance (RobF)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com> (v1)
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
3 years agoRevert "configure: allow building with python3"
Emil Velikov [Fri, 24 Aug 2018 10:14:15 +0000 (11:14 +0100)]
Revert "configure: allow building with python3"

This reverts commit ae7898dfdbe5c8dab7d11c71862353f1ae43feb0.

Turns out the python scripts are _not_ fully python 3 compatible.
As Ilia reported using get_xmlpool.py with LANG=C produces some weird
output - see the link for details.

Even though the issue was spotted with the autoconf build, it exposes a
genuine problem with the script (and lack of lang handling of the meson
build.)

https://lists.freedesktop.org/archives/mesa-dev/2018-August/203508.html

3 years agoRevert "travis: use python3 for the autoconf builds"
Emil Velikov [Fri, 24 Aug 2018 10:10:24 +0000 (11:10 +0100)]
Revert "travis: use python3 for the autoconf builds"

This reverts commit 855af9a5a209f061355513b92f3ba4576f48d091.

Turns out the python scripts are _not_ fully python 3 compatible.
As Ilia reported using get_xmlpool.py with LANG=C produces some weird
output - see the link for details.

Even though the issue was spotted with the autoconf build, it exposes a
genuine problem with the script (and lack of lang handling of the meson
build.)

https://lists.freedesktop.org/archives/mesa-dev/2018-August/203508.html

3 years agoRevert "mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES"
Kenneth Graunke [Fri, 24 Aug 2018 07:32:09 +0000 (00:32 -0700)]
Revert "mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES"

This reverts commit 095515e16ca3cb2c9f1813b6602ee57ae28325a8.

This breaks KHR-GL46.map_buffer_alignment.functional on i965.

This code was apparently not reviewed and I don't know why we would
move from a driver configurable constant to a hardcoded value for all
drivers.  This really looks like an accidental hack push.

3 years agoRevert recent changes about not including compute in combined limits.
Kenneth Graunke [Fri, 24 Aug 2018 03:58:32 +0000 (20:58 -0700)]
Revert recent changes about not including compute in combined limits.

As far as I can tell, no one reviewed these changes, they made i965
assert fail on driver load, and I am not certain they are correct.
(Hopefully reverting these does not break radeonsi too badly...)

The uniform related changes seem fine and reasonable, but the texture
image units change is possibly incorrect.  According to the
OES_tessellation_shader spec issue 5:

   (5) How are aggregate shader limits computed?

    RESOLVED: Following the GL 4.4 model, but we restrict uniform
    buffer bindings to 12/stage instead of 14, this results in

        MAX_UNIFORM_BUFFER_BINDINGS = 72
            This is 12 bindings/stage * 6 shader stages, allowing a static
            partitioning of the bindings even though at most 5 stages can
            appear in a program object).
        MAX_COMBINED_UNIFORM_BLOCKS = 60
            This is 12 blocks/stage * 5 stages, since compute shaders can't
            be mixed with other stages.
        MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
            This is 16 textures/stage * 6 stages.

which definitely is including compute shaders in that last limit.
Not including compute shaders breaks the following test:
dEQP-GLES31.functional.state_query.integer.max_combined_texture_image_units_getinteger

There was enough breakage that I figured we should just send this back
to the drawing board.

Revert "i965: don't include compute resources in "Combined" limits"
Revert "st/mesa: don't include compute resources in "Combined" limits"
Revert "mesa: don't include compute resources in MAX_COMBINED_* limits"

This reverts commit b03dcb1e5f507c5950d0de053a6f76e6306ee71f.
This reverts commit cff290df4c09547cd2cb3b129ec59bdebdadba90.
This reverts commit 45f87a48f94148b484961f18a4f1ccf86f066b1c.

3 years agogallivm: don't use saturated unsigned add/sub intrinsics for llvm 8.0
Roland Scheidegger [Thu, 23 Aug 2018 17:07:05 +0000 (19:07 +0200)]
gallivm: don't use saturated unsigned add/sub intrinsics for llvm 8.0

These have been removed. Unfortunately auto-upgrade doesn't work for
jit. (Worse, it seems we don't get a compilation error anymore when
compiling the shader, rather llvm will just do a call to a null
function in the jitted shaders making it difficult to detect when
intrinsics vanish.)

Luckily the signed ones are still there, I helped convincing llvm
removing them is a bad idea for now, since while the unsigned ones have
sort of agreed-upon simplest patterns to replace them with, this is not
the case for the signed ones, and they require _significantly_ more
complex patterns - to the point that the recognition is IMHO probably
unlikely to ever work reliably in practice (due to other optimizations
interfering). (Even for the relatively trivial unsigned patterns, llvm
already added test cases where recognition doesn't work, unsaturated
add followed by saturated add may produce atrocious code.)
Nevertheless, it seems there's a serious quest to squash all
cpu-specific intrinsics going on, so I'd expect patches to nuke them as
well to resurface.

Adapt the existing fallback code to match the simple patterns llvm uses
and hope for the best. I've verified with lp_test_blend that it does
produce the expected saturated assembly instructions. Though our
cmp/select build helpers don't use boolean masks, but it doesn't seem
to interfere with llvm's ability to recognize the pattern.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106231
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
3 years agost/mesa: expose KHR_texture_compression_astc_sliced_3d
Marek Olšák [Mon, 6 Aug 2018 02:16:48 +0000 (22:16 -0400)]
st/mesa: expose KHR_texture_compression_astc_sliced_3d

This is ASTC 2D LDR allowing texture arrays and 3D, compressing each
slice as a separate 2D image. Tested by piglit. Trivial.

3 years agost/mesa: expose EXT_disjoint_timer_query
Marek Olšák [Mon, 6 Aug 2018 01:41:11 +0000 (21:41 -0400)]
st/mesa: expose EXT_disjoint_timer_query

same cap as ARB_timer_query, no changes needed, tested by piglit

3 years agomesa: expose EXT_vertex_attrib_64bit
Marek Olšák [Mon, 6 Aug 2018 06:48:12 +0000 (02:48 -0400)]
mesa: expose EXT_vertex_attrib_64bit

because the closed driver exposes it.
It's the same as the ARB extension.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agomesa: expose AMD_query_buffer_object
Marek Olšák [Mon, 6 Aug 2018 06:26:09 +0000 (02:26 -0400)]
mesa: expose AMD_query_buffer_object

it's a subset of the ARB extension.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agomesa: expose AMD_multi_draw_indirect
Marek Olšák [Mon, 6 Aug 2018 05:55:59 +0000 (01:55 -0400)]
mesa: expose AMD_multi_draw_indirect

because the closed driver exposes it.
This is equivalent to the ARB extension.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agomesa: expose AMD_gpu_shader_int64
Marek Olšák [Mon, 6 Aug 2018 04:56:35 +0000 (00:56 -0400)]
mesa: expose AMD_gpu_shader_int64

because the closed driver exposes it.

It's equivalent to ARB_gpu_shader_int64.
In this patch, I did everything the same as we do for ARB_gpu_shader_int64.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agomesa: expose ARB_post_depth_coverage in the Compatibility profile
Marek Olšák [Mon, 6 Aug 2018 05:25:51 +0000 (01:25 -0400)]
mesa: expose ARB_post_depth_coverage in the Compatibility profile

It only contains GLSL changes.

v2: allow the layout qualifier on GLSL <= 1.30

3 years agointel/nir: Enable nir_opt_find_array_copies
Jason Ekstrand [Tue, 24 Jul 2018 05:20:41 +0000 (22:20 -0700)]
intel/nir: Enable nir_opt_find_array_copies

We have to be a bit careful with this one because we want it to run in
the optimization loop but only in the first brw_nir_optimize call.
Later calls assume that we've lowered away copy_deref instructions and
we don't want to introduce any more.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15176942 -> 15176942 (0.00%)
    instructions in affected programs: 0 -> 0
    helped: 0
    HURT: 0

In spite of the lack of any shader-db improvement, this patch completely
eliminates spilling in the Batman: Arkham City tessellation shaders.
This is because we are now able to detect that the temporary array
created by DXVK for storing TCS inputs is a copy of the input arrays and
use indirect URB reads instead of making a copy of 4.5 KiB of input data
and then indirecting on it with if-ladders.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir: Add an array copy optimization
Jason Ekstrand [Tue, 24 Jul 2018 02:16:56 +0000 (19:16 -0700)]
nir: Add an array copy optimization

This peephole optimization looks for a series of load/store_deref or
copy_deref instructions that copy an array from one variable to another
and turns it into a copy_deref that copies the entire array.  The
pattern it looks for is extremely specific but it's good enough to pick
up on the input array copies in DXVK and should also be able to pick up
the sequence generated by spirv_to_nir for a OpLoad of a large composite
followed by OpStore.  It can always be improved later if needed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agointel/nir: Use nir_shrink_vec_array_vars
Jason Ekstrand [Wed, 25 Jul 2018 15:54:09 +0000 (08:54 -0700)]
intel/nir: Use nir_shrink_vec_array_vars

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15177605 -> 15176765 (<.01%)
    instructions in affected programs: 4259 -> 3419 (-19.72%)
    helped: 1
    HURT: 0

    total spills in shared programs: 10954 -> 10855 (-0.90%)
    spills in affected programs: 295 -> 196 (-33.56%)
    helped: 1
    HURT: 0

    total fills in shared programs: 22222 -> 22117 (-0.47%)
    fills in affected programs: 417 -> 312 (-25.18%)
    helped: 1
    HURT: 0

The helped shader is from the OglCSDof synmark test.  On my Kaby Lake
laptop, the actual framerate of the benchmark didn't appear to improve
beyond the noise.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir: Add a array-of-vector variable shrinking pass
Jason Ekstrand [Wed, 25 Jul 2018 02:32:27 +0000 (19:32 -0700)]
nir: Add a array-of-vector variable shrinking pass

This pass looks for variables with vector or array-of-vector types and
narrows the type to only the components used.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agointel/nir: Use the new structure and array splitting passes
Jason Ekstrand [Tue, 24 Jul 2018 17:08:20 +0000 (10:08 -0700)]
intel/nir: Use the new structure and array splitting passes

We call structure splitting once because it is guaranteed to split all
the structures in the entire shader in one go.  We call array splitting
in the loop in case future optimizations turn indirects into direct
dereferences and we can split more arrays.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15177605 -> 15177605 (0.00%)
    instructions in affected programs: 0 -> 0
    helped: 0
    HURT: 0

This is unsurprising because nir_lower_vars_to_ssa already effectively
does structure and array splitting internally.  It doesn't actually
split the variables but it's ability to reason about aliasing in the
presence of arrays and structures and pick out scalars or vectors to be
lowered to SSA values is fairly advanced.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir: Add an array splitting pass
Jason Ekstrand [Tue, 24 Jul 2018 19:33:46 +0000 (12:33 -0700)]
nir: Add an array splitting pass

This pass looks for array variables where at least one level of the
array is never indirected and splits it into multiple smaller variables.

This pass doesn't really do much now because nir_lower_vars_to_ssa can
already see through arrays of arrays and can detect indirects on just
one level or even see that arr[i][0][5] does not alias arr[i][1][j].
This pass exists to help other passes more easily see through arrays of
arrays.  If a back-end does implement arrays using scratch or indirects
on registers, having more smaller arrays is likely to have better memory
efficiency.

v2 (Jason Ekstrand):
 - Better comments and naming (some from Caio)
 - Rework to use one hash map instead of two

v2.1 (Jason Ekstrand):
 - Fix a couple of bugs that were added in the rework including one
   which basically prevented it from running

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir: Add a structure splitting pass
Jason Ekstrand [Tue, 24 Jul 2018 17:08:06 +0000 (10:08 -0700)]
nir: Add a structure splitting pass

This pass doesn't really do much now because nir_lower_vars_to_ssa can
already see through structures and considers them to be "split".  This
pass exists to help other passes more easily see through structure
variables.  If a back-end does implement arrays using scratch or
indirects on registers, having more smaller arrays is likely to have
better memory efficiency.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir/types: Add array_or_matrix helpers
Jason Ekstrand [Wed, 25 Jul 2018 15:53:58 +0000 (08:53 -0700)]
nir/types: Add array_or_matrix helpers

Reviewed-by: Thomas Helland<thomashelland90@gmail.com>
3 years agoi965: don't include compute resources in "Combined" limits
Kenneth Graunke [Fri, 24 Aug 2018 00:24:19 +0000 (17:24 -0700)]
i965: don't include compute resources in "Combined" limits

The combined limits should only include shader stages that can be active
at the same time.  We don't need to include compute.

See also cff290df4c09547cd2cb3b129ec59bdebdadba90 for st/mesa.

Unbreaks i965 from assert failing on driver load since Marek's
45f87a48f94148b484961f18a4f1ccf86f066b1c, which dropped the core
Mesa capabilities before adjusting driver limits down to match.

3 years agoradeonsi: increase the maximum UBO size to 2 GB
Marek Olšák [Wed, 8 Aug 2018 19:37:21 +0000 (15:37 -0400)]
radeonsi: increase the maximum UBO size to 2 GB

Same as the closed driver.

This causes a failure in GL45-CTS.compute_shader.max, which has a trivial
bug.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: bump MAX_GS_INVOCATIONS
Marek Olšák [Mon, 6 Aug 2018 12:09:52 +0000 (08:09 -0400)]
radeonsi: bump MAX_GS_INVOCATIONS

same as the closed driver

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agogallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZE
Marek Olšák [Mon, 6 Aug 2018 12:38:54 +0000 (08:38 -0400)]
gallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZE

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agogallium: add PIPE_CAP_MAX_GS_INVOCATIONS
Marek Olšák [Mon, 6 Aug 2018 12:07:25 +0000 (08:07 -0400)]
gallium: add PIPE_CAP_MAX_GS_INVOCATIONS

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agotgsi/ureg: don't call tgsi_sanity when it's too slow
Marek Olšák [Wed, 8 Aug 2018 19:07:51 +0000 (15:07 -0400)]
tgsi/ureg: don't call tgsi_sanity when it's too slow

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agost/mesa: fix up uniform limits to be able to expose large UBOs
Marek Olšák [Wed, 8 Aug 2018 19:17:26 +0000 (15:17 -0400)]
st/mesa: fix up uniform limits to be able to expose large UBOs

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agost/mesa: don't include compute resources in "Combined" limits
Marek Olšák [Wed, 8 Aug 2018 19:21:05 +0000 (15:21 -0400)]
st/mesa: don't include compute resources in "Combined" limits

The combined limits should only include shader stages that can be active
at the same time.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agost/mesa: set ctx->Const.SubPixelBits
Marek Olšák [Mon, 6 Aug 2018 08:25:15 +0000 (04:25 -0400)]
st/mesa: set ctx->Const.SubPixelBits

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoglsl: fix error checking against MAX_UNIFORM_LOCATIONS
Marek Olšák [Wed, 8 Aug 2018 19:53:10 +0000 (15:53 -0400)]
glsl: fix error checking against MAX_UNIFORM_LOCATIONS

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agomesa: make MaxCombinedUniformComponents 64-bit to allow large UBOs
Marek Olšák [Wed, 8 Aug 2018 20:53:03 +0000 (16:53 -0400)]
mesa: make MaxCombinedUniformComponents 64-bit to allow large UBOs

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agomesa: add ctx->Const.MaxGeometryShaderInvocations
Marek Olšák [Mon, 6 Aug 2018 12:09:12 +0000 (08:09 -0400)]
mesa: add ctx->Const.MaxGeometryShaderInvocations

radeonsi wants to report a different value

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agomesa: don't include compute resources in MAX_COMBINED_* limits
Marek Olšák [Mon, 6 Aug 2018 12:32:23 +0000 (08:32 -0400)]
mesa: don't include compute resources in MAX_COMBINED_* limits

5 is the maximum number of shader stages that can be used by 1 execution
call at the same time (e.g. a draw call). The limit ensures that each
stage can use all of its binding points.

Compute is separate and doesn't need the 5x multiplier.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agomesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES
Marek Olšák [Mon, 6 Aug 2018 12:13:35 +0000 (08:13 -0400)]
mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES

same number as our closed GL driver

v2: don't use MaxArrayLockSize

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agomesa: remove incorrect change for EXT_disjoint_timer_query
Marek Olšák [Mon, 6 Aug 2018 01:39:00 +0000 (21:39 -0400)]
mesa: remove incorrect change for EXT_disjoint_timer_query

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoglapi: actually implement GL_EXT_robustness for GLES
Marek Olšák [Wed, 22 Aug 2018 21:28:26 +0000 (17:28 -0400)]
glapi: actually implement GL_EXT_robustness for GLES

The extension was exposed but not the functions.

This fixes:
    dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.readn_pixels
    dEQP-GLES31.functional.debug.negative_coverage.get_error.state.get_nuniformfv
    dEQP-GLES31.functional.debug.negative_coverage.get_error.state.get_nuniformiv

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/decoder: Decode SFIXED values.
Kenneth Graunke [Thu, 23 Aug 2018 08:06:53 +0000 (01:06 -0700)]
intel/decoder: Decode SFIXED values.

This lets us example SAMPLER_STATE's LOD Bias field, among other things.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agotravis: use python3 for the autoconf builds
Emil Velikov [Thu, 16 Aug 2018 12:01:05 +0000 (13:01 +0100)]
travis: use python3 for the autoconf builds

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoconfigure: allow building with python3
Emil Velikov [Thu, 16 Aug 2018 12:59:38 +0000 (13:59 +0100)]
configure: allow building with python3

Pretty much all of the scripts are python2+3 compatible.
Check and allow using python3, while adjusting the PYTHON2 refs.

Note:
 - python3.4 is used as it's the earliest supported version
 - python3 chosen prior to python2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agobin/git_sha1_gen.py: remove execute bit/shebang
Emil Velikov [Thu, 23 Aug 2018 13:44:19 +0000 (14:44 +0100)]
bin/git_sha1_gen.py: remove execute bit/shebang

The script is executed explicitly via the build system, that uses
PYTHON/prog_python and equivalent.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agovk/wsi: avoid reading uninitialised memory
Eric Engestrom [Tue, 17 Jul 2018 12:13:40 +0000 (13:13 +0100)]
vk/wsi: avoid reading uninitialised memory

It will be ignored by x11_swapchain_result() anyway (because reaching
the `fail` label without setting `result` means the swapchain status was
already a hard error), but the compiler still complains about reading
uninitialised memory.

While at it, drop the unused assignment right before returning.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoegl: drop unused _EGL_BUILT_IN_DRIVER_DRI2
Eric Engestrom [Mon, 9 Jul 2018 20:15:36 +0000 (21:15 +0100)]
egl: drop unused _EGL_BUILT_IN_DRIVER_DRI2

Unused since b174a1ae720cb404738c "egl: Simplify the "driver" interface".

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agoradv/gfx9: implement coherent shaders for VK_ACCESS_SHADER_READ_BIT
Samuel Pitoiset [Fri, 27 Jul 2018 14:14:28 +0000 (16:14 +0200)]
radv/gfx9: implement coherent shaders for VK_ACCESS_SHADER_READ_BIT

Single-sample color and single-sample depth (not stencil)
are coherent with shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
3 years agobin/install_megadrivers.py: Remove shebang and executable bit
Mathieu Bridon [Wed, 22 Aug 2018 16:58:26 +0000 (18:58 +0200)]
bin/install_megadrivers.py: Remove shebang and executable bit

Since the script is never executed directly, but launched by Meson as an
argument to the Python interpreter, those are not needed any more.

In addition, they are the reason this script was missed when I moved the
Meson buildsystem to Python 3, so removing them helps avoiding future
confusion.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
3 years agomeson: Run the install script with Python 3
Mathieu Bridon [Wed, 22 Aug 2018 12:09:49 +0000 (14:09 +0200)]
meson: Run the install script with Python 3

The script was being run directly as an executable, and it has a
Python 2 shebang.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
3 years agoglsl: remove execute bit and shebang from python tests
Emil Velikov [Fri, 17 Aug 2018 10:41:25 +0000 (11:41 +0100)]
glsl: remove execute bit and shebang from python tests

Just like the rest of the tree - these should be run either as part of
the build system check target, or at the very least with an explicitly
versioned python executable.

Fixes: db8cd8e3677 ("glcpp/tests: Convert shell scripts to a python script")
Fixes: 97c28cb0823 ("glsl/tests: Convert optimization-test.sh to pure python")
Fixes: 3b52d292273 ("glsl/tests: reimplement warnings-test in python")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agodocs: update required mako version
Emil Velikov [Thu, 16 Aug 2018 16:57:10 +0000 (17:57 +0100)]
docs: update required mako version

The requirement was bumped a while back, but we forgot to update the
docs.

Fixes: ed871af91c2 ("configure.ac: raise Mako required version to
0.8.0")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoconfigure: use distutils in ax_check_python_mako_module
Emil Velikov [Thu, 16 Aug 2018 12:36:05 +0000 (13:36 +0100)]
configure: use distutils in ax_check_python_mako_module

Handling the version comparison by hand is a bad idea. Python has a handy
module distutils for that - use it.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agoconfigure: enforce python 2.7 with AM_PATH_PYTHON
Emil Velikov [Thu, 16 Aug 2018 12:40:21 +0000 (13:40 +0100)]
configure: enforce python 2.7 with AM_PATH_PYTHON

Currently we use AC_CHECK_PROGS looking for python2.7, python2 and
finally python. That is due to the varying names used across the
different OS.

Use the handy AM_PATH_PYTHON which finds the correct name and checks for
the version.

Note: python2.7 has been an unofficial requirement for quite some time.
Update the docs to reflect that.

Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
3 years agoi965: Enable INTEL_shader_atomic_float_minmax on Gen9+
Ian Romanick [Wed, 18 Apr 2018 21:08:48 +0000 (14:08 -0700)]
i965: Enable INTEL_shader_atomic_float_minmax on Gen9+

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoi965: Sort Gen9+ extension enables
Ian Romanick [Wed, 18 Apr 2018 21:06:27 +0000 (14:06 -0700)]
i965: Sort Gen9+ extension enables

This is a strictly alphabetic sort, as is done in extensions_table.h
There are other options.  We should pick one and document it.  Right
now, this file is chaos.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agointel/compiler: Implement untyped atomic float min, max, and compare-swap dataport...
Ian Romanick [Wed, 18 Apr 2018 21:02:33 +0000 (14:02 -0700)]
intel/compiler: Implement untyped atomic float min, max, and compare-swap dataport messages

v2: Split changes to the message type field to another patch.  Suggested
by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agointel/compiler: Expand untyped atomic message type field by a bit
Ian Romanick [Wed, 18 Apr 2018 21:02:33 +0000 (14:02 -0700)]
intel/compiler: Expand untyped atomic message type field by a bit

This is necessary for a new Gen9 message type that will be added in the
next patch.  There are also Gen8 message types that need the extra bit
(mostly for bindless).

v2: Split off from the next patch.  Suggested by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agointel/compiler: Silence unused parameter warnings
Ian Romanick [Tue, 10 Apr 2018 17:37:42 +0000 (10:37 -0700)]
intel/compiler: Silence unused parameter warnings

src/intel/compiler/brw_disasm_info.c: In function ‘nir_print_instr’:
src/intel/compiler/brw_disasm_info.c:30:61: warning: unused parameter ‘instr’ [-Wunused-parameter]
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
                                                             ^~~~~
src/intel/compiler/brw_disasm_info.c:30:74: warning: unused parameter ‘fp’ [-Wunused-parameter]
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
                                                                          ^~
src/intel/compiler/brw_disasm.c: In function ‘src_ia1’:
src/intel/compiler/brw_disasm.c:850:18: warning: unused parameter ‘_reg_file’ [-Wunused-parameter]
         unsigned _reg_file,
                  ^~~~~~~~~
src/intel/compiler/brw_fs_surface_builder.cpp: In function ‘void brw::surface_access::emit_byte_scattered_write(const brw::fs_builder&, const fs_reg&, const fs_reg&, const fs_reg&, unsigned int, unsigned int, unsigned int, brw_predicate)’:
src/intel/compiler/brw_fs_surface_builder.cpp:193:57: warning: unused parameter ‘size’ [-Wunused-parameter]
                                 unsigned dims, unsigned size,
                                                         ^~~~

v2: Update commit message.  brw_fs_generator.cpp warnings were already
fixed by another patch.  Noticed by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir: Add floating point atomic min, max, and compare-swap instrinsics
Ian Romanick [Wed, 18 Apr 2018 20:34:25 +0000 (13:34 -0700)]
nir: Add floating point atomic min, max, and compare-swap instrinsics

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agonir: Add floating point atomic add instrinsics
Ian Romanick [Tue, 10 Apr 2018 01:36:22 +0000 (18:36 -0700)]
nir: Add floating point atomic add instrinsics

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoglsl: Add support for lowering shared-variable float atomics
Ian Romanick [Thu, 12 Apr 2018 00:53:22 +0000 (17:53 -0700)]
glsl: Add support for lowering shared-variable float atomics

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoglsl: Add support for lowering SSBO float atomics
Ian Romanick [Mon, 9 Apr 2018 22:26:48 +0000 (15:26 -0700)]
glsl: Add support for lowering SSBO float atomics

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoglsl: Add built-in functions for INTEL_shader_atomic_float_minmax
Ian Romanick [Wed, 18 Apr 2018 20:20:25 +0000 (13:20 -0700)]
glsl: Add built-in functions for INTEL_shader_atomic_float_minmax

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agomesa: Extension boilerplate for INTEL_shader_atomic_float_minmax
Ian Romanick [Wed, 18 Apr 2018 18:45:13 +0000 (11:45 -0700)]
mesa: Extension boilerplate for INTEL_shader_atomic_float_minmax

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agodocs: Initial version of INTEL_shader_atomic_float_minmax spec
Ian Romanick [Thu, 19 Apr 2018 22:35:42 +0000 (15:35 -0700)]
docs: Initial version of INTEL_shader_atomic_float_minmax spec

v2: Describe interactions with the capabilities added by
SPV_INTEL_shader_atomic_float_minmax

v3: Remove 64-bit float support.

v4: Explain NaN issues.  Explain issues with atomicMin(-0, +0) and
atomicMax(-0, +0).

v5: Fix whitespace issues noticed by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoglsl: Add built-in functions for NV_shader_atomic_float
Ian Romanick [Thu, 29 Mar 2018 22:16:38 +0000 (15:16 -0700)]
glsl: Add built-in functions for NV_shader_atomic_float

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agomesa: Extension boilerplate for NV_shader_atomic_float
Ian Romanick [Thu, 29 Mar 2018 21:59:47 +0000 (14:59 -0700)]
mesa: Extension boilerplate for NV_shader_atomic_float

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agomeson: fix egl build for android
Gurchetan Singh [Wed, 22 Aug 2018 23:08:34 +0000 (16:08 -0700)]
meson: fix egl build for android

Haven't tested this, but we do include loader.h
in platform_android.c

Fixes: c5ec1556859b7d33637c9fad13d3473c7b2f9eb3 ("meson: wire up egl/android")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agomeson: fix egl build for surfaceless
Gurchetan Singh [Wed, 22 Aug 2018 23:08:33 +0000 (16:08 -0700)]
meson: fix egl build for surfaceless

Without this, I get:

 > platform_surfaceless.c:38:10: fatal error: 'loader.h' file not found
 > #include "loader.h"
 >      ^~~~~~~~~~
 > 1 error generated.

Fixes: 108d257a16859898f5ce02f4759c5c58f9b8c050 ("meson: build libEGL")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
v2: Split up patches, modify commit message (Dylan)