mesa.git
21 months agoandroid: util: Add a mapping from VkFormat to PIPE_FORMAT.
Mauro Rossi [Sun, 8 Dec 2019 08:40:36 +0000 (09:40 +0100)]
android: util: Add a mapping from VkFormat to PIPE_FORMAT.

Updates Makefile.sources and fixes the following building error:

In file included from external/mesa/src/vulkan/util/vk_format.c:24:
In file included from external/mesa/src/vulkan/util/vk_format.h:28:
external/mesa/src/util/format/u_format.h:33:10: fatal error: 'pipe/p_format.h' file not found
#include "pipe/p_format.h"
         ^~~~~~~~~~~~~~~~~
1 error generated.

Fixes: 3a28281 ("util: Add a mapping from VkFormat to PIPE_FORMAT.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
21 months agoandroid: nir: add a load/store vectorization pass
Mauro Rossi [Sun, 8 Dec 2019 08:40:36 +0000 (09:40 +0100)]
android: nir: add a load/store vectorization pass

Fixes the following aco building error:

external/mesa/src/amd/compiler/aco_instruction_selection_setup.cpp:846:
error: undefined reference to 'nir_opt_load_store_vectorize'

Fixes: ce9205c ("nir: add a load/store vectorization pass")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
21 months agollvmpipe: add debug option to enable OpenCL support.
Dave Airlie [Tue, 10 Dec 2019 04:55:43 +0000 (14:55 +1000)]
llvmpipe: add debug option to enable OpenCL support.

LP_DEBUG=cl will enable CL support for now.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm/nir: add vec8/16 support
Dave Airlie [Thu, 12 Dec 2019 01:48:48 +0000 (11:48 +1000)]
gallivm/nir: add vec8/16 support

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm/nir: lower packing
Dave Airlie [Fri, 13 Dec 2019 03:17:48 +0000 (13:17 +1000)]
gallivm/nir: lower packing

This fixes some CL upsample tests, which lower into packing that needs
lowering.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agollvmpipe: lower hadd/add_sat
Dave Airlie [Thu, 12 Dec 2019 05:33:51 +0000 (15:33 +1000)]
llvmpipe: lower hadd/add_sat

Fixes some CL piglits.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm: handle non-32 bit undefined
Dave Airlie [Thu, 12 Dec 2019 02:42:25 +0000 (12:42 +1000)]
gallivm: handle non-32 bit undefined

other sized undefs caused llvm asserts

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agollvmpipe/nir: use nir_max_vec_components in more places
Dave Airlie [Thu, 12 Dec 2019 01:48:31 +0000 (11:48 +1000)]
llvmpipe/nir: use nir_max_vec_components in more places

This is prep work for when vec8/16 have landed.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agollvmpipe: add support for compute shader params
Dave Airlie [Tue, 10 Dec 2019 04:55:34 +0000 (14:55 +1000)]
llvmpipe: add support for compute shader params

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agollvmpipe: handle serialized nir as a shader type.
Dave Airlie [Tue, 10 Dec 2019 04:55:17 +0000 (14:55 +1000)]
llvmpipe: handle serialized nir as a shader type.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm/llvmpipe: add support for global operations.
Dave Airlie [Tue, 10 Dec 2019 04:53:51 +0000 (14:53 +1000)]
gallivm/llvmpipe: add support for global operations.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm/llvmpipe: add support for block size intrinsic
Dave Airlie [Tue, 10 Dec 2019 04:52:49 +0000 (14:52 +1000)]
gallivm/llvmpipe: add support for block size intrinsic

We have to pass the main block size into the coroutine
and into the shader.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm/llvmpipe: add support for work dimension intrinsic.
Dave Airlie [Tue, 10 Dec 2019 04:51:57 +0000 (14:51 +1000)]
gallivm/llvmpipe: add support for work dimension intrinsic.

We have to pass the work_dim given by the user into the shader.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agotgsi/mesa: handle KERNEL case
Dave Airlie [Tue, 10 Dec 2019 04:49:00 +0000 (14:49 +1000)]
tgsi/mesa: handle KERNEL case

Translate to compute for now.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm/nir: allow 8/16-bit conversion and comparison.
Dave Airlie [Thu, 12 Dec 2019 05:03:01 +0000 (15:03 +1000)]
gallivm/nir: allow 8/16-bit conversion and comparison.

This adds the convert to 8/16 and support for 8/16 comparsions

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm: pick integer builders for alu instructions.
Dave Airlie [Thu, 12 Dec 2019 05:02:14 +0000 (15:02 +1000)]
gallivm: pick integer builders for alu instructions.

This allows these to be used with non 32-bit types.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm: add support for 8-bit/16-bit integer builders
Dave Airlie [Tue, 10 Dec 2019 04:47:07 +0000 (14:47 +1000)]
gallivm: add support for 8-bit/16-bit integer builders

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agollvmpipe/gallivm: add kernel inputs
Dave Airlie [Tue, 10 Dec 2019 04:45:19 +0000 (14:45 +1000)]
llvmpipe/gallivm: add kernel inputs

compute shaders need kernel input support

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agogallivm: add 64-bit const int creator.
Dave Airlie [Tue, 10 Dec 2019 04:41:55 +0000 (14:41 +1000)]
gallivm: add 64-bit const int creator.

Acked-by: Roland Scheidegger <sroland@vmware.com>
21 months agonir: sanitize work group intrinsics to always be 32-bit.
Dave Airlie [Wed, 11 Dec 2019 23:39:21 +0000 (09:39 +1000)]
nir: sanitize work group intrinsics to always be 32-bit.

This saves handling them in the backend later.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
21 months agoradv: Expose all sample counts for integer formats as well.
Bas Nieuwenhuizen [Tue, 24 Dec 2019 13:44:03 +0000 (14:44 +0100)]
radv: Expose all sample counts for integer formats as well.

Things work the same between float and integer.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2261
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
21 months agopanfrost: Route gl_VertexID through cmdstream
Alyssa Rosenzweig [Thu, 19 Dec 2019 19:00:24 +0000 (14:00 -0500)]
panfrost: Route gl_VertexID through cmdstream

It shows up as a special (magic?) attribute. We could try to be clever
and only include the extra record if gl_VertexID is actually read, but
honestly that's just extra complexity for no good reason. Might as well
just always include it; this won't be a real bottleneck, I don't think.

Fixes dEQP-GLES3.functional.shaders.builtin_variable.vertex_id.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Extend attribute_count for vertex builtins
Alyssa Rosenzweig [Thu, 19 Dec 2019 18:39:14 +0000 (13:39 -0500)]
panfrost: Extend attribute_count for vertex builtins

They stretch beyond the usual limit for attributes so are included
implicitly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Lower gl_VertexID/gl_InstanceID to attributes
Alyssa Rosenzweig [Thu, 19 Dec 2019 18:31:21 +0000 (13:31 -0500)]
pan/midgard: Lower gl_VertexID/gl_InstanceID to attributes

We have special records for these, put in a fixed location by convention
per the blob.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Factor out emit_attr_read
Alyssa Rosenzweig [Thu, 19 Dec 2019 18:24:17 +0000 (13:24 -0500)]
pan/midgard: Factor out emit_attr_read

We will load attributes directly for gl_VertexID.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Unset vertex_id_zero_based
Alyssa Rosenzweig [Thu, 19 Dec 2019 18:17:03 +0000 (13:17 -0500)]
panfrost: Unset vertex_id_zero_based

We don't want the lowering; we have native gl_VertexID.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/decode: Handle gl_VertexID/gl_InstanceID
Alyssa Rosenzweig [Thu, 19 Dec 2019 17:28:42 +0000 (12:28 -0500)]
pan/decode: Handle gl_VertexID/gl_InstanceID

Just like varyings have special records for point coordinates (etc),
attributes have special records for vertex/instance ID. We can parse
these fairly easily, although they don't line up exactly with normal
attribute records.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Remove pan_shift_odd
Alyssa Rosenzweig [Thu, 19 Dec 2019 21:46:43 +0000 (16:46 -0500)]
panfrost: Remove pan_shift_odd

Padded counts are numbers of the form:

   n = (2k + 1) * 2^s

for k, s integers. Rather than explicitly store k and s separately and
then compute this formula on demand, it's much cleaner to store the
padded number itself, which is what you manipulate most of the time.
When you do need k,s it is easy to factor by noticing the bitwise
representation:

   s = ctz(n)
   k = n >> (s + 1)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Slight cleanup of Gallium's pan_attribute.c
Alyssa Rosenzweig [Thu, 19 Dec 2019 21:46:28 +0000 (16:46 -0500)]
panfrost: Slight cleanup of Gallium's pan_attribute.c

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/decode: Fix reference computation for invocations
Alyssa Rosenzweig [Wed, 25 Dec 2019 03:33:47 +0000 (22:33 -0500)]
pan/decode: Fix reference computation for invocations

Slight bug with instancing. No harm done but let's get rid of the
pandecode warning, it's just noise.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Fix off-by-one in pan_invocation.c
Alyssa Rosenzweig [Wed, 25 Dec 2019 03:33:13 +0000 (22:33 -0500)]
panfrost: Fix off-by-one in pan_invocation.c

When instance_count=2, the packing code was broken. Fixes a dEQP test.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Factor out panfrost_compute_magic_divisor
Alyssa Rosenzweig [Wed, 25 Dec 2019 02:35:52 +0000 (21:35 -0500)]
panfrost: Factor out panfrost_compute_magic_divisor

The algorithm doesn't need to be tangled up in details about the
attribute records themselves. We'll need to compute magic divisors for
gl_InstanceID in a second.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Move instancing routines to encoder/
Alyssa Rosenzweig [Thu, 19 Dec 2019 21:39:56 +0000 (16:39 -0500)]
panfrost: Move instancing routines to encoder/

Nothing Gallium specific or stateful about them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Factor batch/resource out of instancing routines
Alyssa Rosenzweig [Thu, 19 Dec 2019 21:26:43 +0000 (16:26 -0500)]
panfrost: Factor batch/resource out of instancing routines

They don't need them; this will allow us to move the code into encoder/
which in turn will make the messy Gallium code less scary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Rename pan_instancing.c -> pan_attributes.c
Alyssa Rosenzweig [Thu, 19 Dec 2019 21:04:59 +0000 (16:04 -0500)]
panfrost: Rename pan_instancing.c -> pan_attributes.c

Let's follow the naming convention that panfrost command stream code is
organized by command stream structure.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Compute destination override
Alyssa Rosenzweig [Wed, 13 Nov 2019 12:58:48 +0000 (07:58 -0500)]
pan/midgard: Compute destination override

We shift over the mask in this case.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Add mir_upper_override helper
Alyssa Rosenzweig [Wed, 13 Nov 2019 02:22:53 +0000 (21:22 -0500)]
pan/midgard: Add mir_upper_override helper

Checks if we should emit a dest_override=upper, given a mask.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Support loads from R11G11B10 in a blend shader
Alyssa Rosenzweig [Mon, 16 Dec 2019 19:42:17 +0000 (14:42 -0500)]
pan/midgard: Support loads from R11G11B10 in a blend shader

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Enable lower_(un)pack_* lowering
Alyssa Rosenzweig [Tue, 24 Dec 2019 19:01:33 +0000 (14:01 -0500)]
pan/midgard: Enable lower_(un)pack_* lowering

These show up in some blend shaders. Let's use the shared lowering and
remove our own.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Increase PIPE_SHADER_CAP_MAX_OUTPUTS to 16
Tomeu Vizoso [Thu, 19 Dec 2019 15:01:15 +0000 (16:01 +0100)]
panfrost: Increase PIPE_SHADER_CAP_MAX_OUTPUTS to 16

GL ES 3.0 requires it to be higher, and stuff seems to work just fine.

Fixes: dEQP-GLES3.functional.implementation_limits.max_vertex_output_components
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
21 months agopanfrost: Handle Z24_UNORM_S8_UINT as MALI_Z32_UNORM
Tomeu Vizoso [Thu, 19 Dec 2019 11:51:06 +0000 (12:51 +0100)]
panfrost: Handle Z24_UNORM_S8_UINT as MALI_Z32_UNORM

Fixes dEQP-GLES3.functional.texture.format.sized.2d.depth24_stencil8_pot

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
21 months agopan/midgard: Implement shadow cubemaps
Alyssa Rosenzweig [Fri, 20 Dec 2019 22:25:05 +0000 (17:25 -0500)]
pan/midgard: Implement shadow cubemaps

We need to reshuffle to sync up the shadow coordinate temporary with the
cubemap coordinate temporary. Once that's in place, it's simple enough
(we load the shadow coordinate into .z like 2D).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Generalize temp coordinate to non-2D
Alyssa Rosenzweig [Fri, 20 Dec 2019 22:01:29 +0000 (17:01 -0500)]
pan/midgard: Generalize temp coordinate to non-2D

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Do witchcraft on texture offsets
Alyssa Rosenzweig [Fri, 20 Dec 2019 18:48:24 +0000 (13:48 -0500)]
pan/midgard: Do witchcraft on texture offsets

My latest divination spell has uncovered a pattern in the aether.
Although the swizzle is unaligned, its format is otherwise standard.
Document this, removing the old incorrect understanding of the swizzle
(which coincided on common special swizzles only).

Fixes dEQP-GLES3.functional.shaders.texture_functions.texelfetchoffset.sampler2d_fixed_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Fix fallthrough from offset to comparator
Alyssa Rosenzweig [Fri, 20 Dec 2019 17:58:10 +0000 (12:58 -0500)]
pan/midgard: Fix fallthrough from offset to comparator

Fixes: ccbc9a4e678 ("pan/midgard: Implement textureOffset for 2D textures")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Expand swizzle for texelFetch
Alyssa Rosenzweig [Fri, 20 Dec 2019 17:38:24 +0000 (12:38 -0500)]
pan/midgard: Expand swizzle for texelFetch

We zero the extra components anyway. Fixes
dEQP-GLES3.functional.shaders.texture_functions.texelfetch.sampler2d_fixed_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Clamp LOD register swizzle
Alyssa Rosenzweig [Fri, 20 Dec 2019 17:34:20 +0000 (12:34 -0500)]
pan/midgard: Clamp LOD register swizzle

Fixes register allocation failures with textureLodOffset.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Extend IS_VEC4_ONLY to arguments
Alyssa Rosenzweig [Sun, 22 Dec 2019 19:55:46 +0000 (14:55 -0500)]
pan/midgard: Extend IS_VEC4_ONLY to arguments

I think both need to be aligned at least for ld_cubemap_coords.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/midgard: Bounds check lcra_restrict_range
Alyssa Rosenzweig [Mon, 23 Dec 2019 20:49:18 +0000 (15:49 -0500)]
pan/midgard: Bounds check lcra_restrict_range

We may call it with sentinel values (~0 in particular) corresponding to
unused arguments; ignore these.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agofreedreno/ir3: fix flat shading again
Rob Clark [Fri, 20 Dec 2019 21:06:11 +0000 (13:06 -0800)]
freedreno/ir3: fix flat shading again

These days `ctx->inputs` is the split scalar input components and
`ir->inputs` is the full vecN.  This got fixed in the load_input case,
but the load_interpolated_input case was missed.

Fixes: bdf6b7018ce ("freedreno/ir3: re-work shader inputs/outputs")
Signed-off-by: Rob Clark <robdclark@chromium.org>
21 months agopan/midgard: Fix disassembler cycle/quadword counting
Alyssa Rosenzweig [Mon, 23 Dec 2019 17:24:03 +0000 (12:24 -0500)]
pan/midgard: Fix disassembler cycle/quadword counting

Due to the succeeding break we would fall into some off-by-one errors.
These should be resolved now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/decode: Append 0:0 spills:fills to blobber-db
Alyssa Rosenzweig [Mon, 23 Dec 2019 16:50:28 +0000 (11:50 -0500)]
pan/decode: Append 0:0 spills:fills to blobber-db

At the moment there's no need to actually count these but we do need a
placeholder for report.py to be happy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/decode: Prefix blobberdb with MESA_SHADER_*
Alyssa Rosenzweig [Mon, 23 Dec 2019 16:49:09 +0000 (11:49 -0500)]
pan/decode: Prefix blobberdb with MESA_SHADER_*

We use these prefixes in panfrost shader-db and they need to match for
shader-db to be happpy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopan/decode: Skip COMPUTE in blobber-db
Alyssa Rosenzweig [Mon, 23 Dec 2019 16:48:23 +0000 (11:48 -0500)]
pan/decode: Skip COMPUTE in blobber-db

The blob uses COMPUTE jobs for some internal purposes. These are
essentially free but panfrost doesn't use them, so it messes up the
numbering. Just filter them out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agopanfrost: Decode shader types in pantrace shader-db
Alyssa Rosenzweig [Mon, 23 Dec 2019 16:40:40 +0000 (11:40 -0500)]
panfrost: Decode shader types in pantrace shader-db

We see some COMPUTE jobs that were mistakenly identified as VERTEX.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
21 months agoanv: Properly advertise sampledImageIntegerSampleCounts
Jason Ekstrand [Tue, 24 Dec 2019 04:19:29 +0000 (22:19 -0600)]
anv: Properly advertise sampledImageIntegerSampleCounts

We support the same set of samples for integer color formats as for
non-integer.  We've been advertising it wrong since before the initial
Vulkan 1.0 release. :-(

Fixes: d68974530371 "vk/0.210.0: Rework device features and limits"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
22 months agoAndroid: Fix build issue without LLVM
Roman Stratiienko [Thu, 5 Dec 2019 16:32:02 +0000 (18:32 +0200)]
Android: Fix build issue without LLVM

Some of the latest changes are causing the following build error on Android:

```
external/mesa3d/src/gallium/auxiliary/nir/nir_to_tgsi_info.c:403:6:
error: redefinition of 'nir_tgsi_scan_shader'
void nir_tgsi_scan_shader(const struct nir_shader *nir,
     ^
external/mesa3d/src/gallium/auxiliary/nir/nir_to_tgsi_info.h:37:20:
note: previous definition is here
static inline void nir_tgsi_scan_shader(const struct nir_shader *nir,
                   ^
```

Include nir_to_tgsi_info.c and nir_to_tgsi_info.h into the build
only if LLVM is enabled.

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2978>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2978>

22 months agoiris: Avoid replacing backing storage for buffers with no contents
Kenneth Graunke [Mon, 4 Nov 2019 08:21:06 +0000 (00:21 -0800)]
iris: Avoid replacing backing storage for buffers with no contents

We might get asked to pitch the storage on a buffer that already has
no meaningful contents.  In this case, the existing buffer is as good
as a new one.

22 months agoiris: Fix shader recompile debug printing
Kenneth Graunke [Sun, 22 Dec 2019 23:43:51 +0000 (15:43 -0800)]
iris: Fix shader recompile debug printing

I was passing iris keys to brw_debug_key_recompile, leading to out of
bounds memory reads.

Fixes: 2e654db27a1 ("iris: Create smaller program keys without legacy features")
22 months agoiris: Make helper functions to turn iris shader keys into brw keys.
Kenneth Graunke [Sun, 22 Dec 2019 23:33:17 +0000 (15:33 -0800)]
iris: Make helper functions to turn iris shader keys into brw keys.

We'll need to use these in recompile debugging in the next commit.

Fixes: 2e654db27a1 ("iris: Create smaller program keys without legacy features")
22 months agoswr: Fix build with llvm-10.0.
Vinson Lee [Sat, 14 Dec 2019 04:47:51 +0000 (20:47 -0800)]
swr: Fix build with llvm-10.0.

Fix build error after llvm-10 commit 5d986953c8b9 ("[IR] Split out
target specific intrinsic enums into separate headers").

../src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp:78:37: error: ‘x86_bmi_bextr_32’ is not a member of ‘llvm::Intrinsic’
         {"meta.intrinsic.BEXTR_32", Intrinsic::x86_bmi_bextr_32},
                                     ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
22 months agotravis: autodetect python version instead of hard-coding it
Eric Engestrom [Sat, 21 Dec 2019 19:28:07 +0000 (19:28 +0000)]
travis: autodetect python version instead of hard-coding it

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
22 months agoetnaviv: tgsi: Fix gl_FrontFacing support
Marek Vasut [Sun, 17 Nov 2019 13:53:54 +0000 (14:53 +0100)]
etnaviv: tgsi: Fix gl_FrontFacing support

The GPU presents the state of the hardware front_face in internal
register 0 (i0), the range of which is 0.0f..1.0f.

This patch assigns the fragment shader input to this internal register.
Moreover, based on the internal front_ccw state, the value of the i0
register is inverted accordingly using SET.EQ/SEQ.NE instruction before
being further processed in the shader. This mimics the operation of the
NIR compiler.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2868>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2868>

22 months agou_vbuf: Return true in u_vbuf_get_caps if nb of vbufs is below minimum
Paul Cercueil [Fri, 22 Nov 2019 22:23:36 +0000 (23:23 +0100)]
u_vbuf: Return true in u_vbuf_get_caps if nb of vbufs is below minimum

Return true in u_vbuf_get_caps if the number of vertex buffers is below
the minimum required for proper OpenGL 2.0.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months agou_vbuf: Regard non-constant vbufs with non-instance elements as free
Paul Cercueil [Tue, 19 Nov 2019 21:10:10 +0000 (22:10 +0100)]
u_vbuf: Regard non-constant vbufs with non-instance elements as free

In the case of unroll_indices, we can regard all non-constant
vertex buffers with only non-instance vertex elements as incompatible
and thus free.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months agou_vbuf: use single vertex buffer if it's not possible to have multiple
Wladimir J. van der Laan [Thu, 3 Oct 2013 10:32:12 +0000 (12:32 +0200)]
u_vbuf: use single vertex buffer if it's not possible to have multiple

Put CONST, VERTEX and INSTANCE attributes into one vertex buffer if
necessary due to hardware constraints.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months agou_vbuf: Only create driver CSO if no incompatible elements
Paul Cercueil [Tue, 19 Nov 2019 20:59:07 +0000 (21:59 +0100)]
u_vbuf: Only create driver CSO if no incompatible elements

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months agou_vbuf: Mark vbufs incompatible if more were requested than HW supports
Paul Cercueil [Tue, 19 Nov 2019 20:58:17 +0000 (21:58 +0100)]
u_vbuf: Mark vbufs incompatible if more were requested than HW supports

More vertex buffers are used than the hardware supports.  In
principle, we only need to make sure that less vertex buffers are
used, and mark some of the latter vertex buffers as incompatible.
For now, mark all vertex buffers as incompatible.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months agou_vbuf: add logic to use a limited number of vbufs
Wladimir J. van der Laan [Sat, 11 Jun 2016 19:21:52 +0000 (21:21 +0200)]
u_vbuf: add logic to use a limited number of vbufs

Make it possible to limit the number of vertex buffers as there exist
GPUs with less then 32 supported vertex buffers.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months agogallium: add PIPE_CAP_MAX_VERTEX_BUFFERS
Christian Gmeiner [Sat, 11 Jun 2016 19:21:51 +0000 (21:21 +0200)]
gallium: add PIPE_CAP_MAX_VERTEX_BUFFERS

Add PIPE_CAP_MAX_VERTEX_BUFFERS param, which defaults to 16.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>

22 months ago.mailmap: use correct email address
David Heidelberg [Sat, 21 Dec 2019 01:53:10 +0000 (02:53 +0100)]
.mailmap: use correct email address

Signed-off-by: David Heidelberg <david@ixit.cz>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3190>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3190>

22 months agokmsro: Extend to include ingenic-drm
Paul Cercueil [Mon, 11 Nov 2019 01:01:52 +0000 (02:01 +0100)]
kmsro: Extend to include ingenic-drm

This enables Mesa to work with Ingenic SoCs through the use of the
ingenic-drm modesetting driver along with the render-only drivers,
such as Etnaviv on the JZ4770 SoC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
22 months agokmsro: Add "mcde" entry point
Stephan Gerhold [Mon, 4 Nov 2019 21:48:49 +0000 (22:48 +0100)]
kmsro: Add "mcde" entry point

ST-Ericsson Ux500 boards use a Mali 400 GPU together with MCDE
("Multi Channel Display Engine"), which is supported by the "mcde"
DRM driver.

Adding an entry point for it in kmsro seems to be enough to make
Lima work - at least kmscube is working correctly.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3139>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3139>

22 months agoaco: fix vgpr alloc granule with wave32
Rhys Perry [Tue, 3 Dec 2019 14:21:16 +0000 (14:21 +0000)]
aco: fix vgpr alloc granule with wave32

We still need to increase the number of physical vgprs

Totals from affected shaders:
SGPRS: 671976 -> 675288 (0.49 %)
VGPRS: 550112 -> 562596 (2.27 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 27621660 -> 27606532 (-0.05 %) bytes
Max Waves: 81083 -> 87833 (8.32 %)
Instructions: 5391560 -> 5389031 (-0.05 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
22 months agoaco: improve jump threading with wave32
Rhys Perry [Tue, 3 Dec 2019 14:10:45 +0000 (14:10 +0000)]
aco: improve jump threading with wave32

Totals from affected shaders:
SGPRS: 748746 -> 748746 (0.00 %)
VGPRS: 636984 -> 636984 (0.00 %)
Spilled SGPRs: 387 -> 387 (0.00 %)
Spilled VGPRs: 15 -> 15 (0.00 %)
Code Size: 61138824 -> 60928620 (-0.34 %) bytes
Max Waves: 48602 -> 48602 (0.00 %)
Instructions: 11967660 -> 11915084 (-0.44 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
22 months agoaco/wave32: fix comparison optimizations
Rhys Perry [Tue, 3 Dec 2019 13:37:49 +0000 (13:37 +0000)]
aco/wave32: fix comparison optimizations

Previously, they weren't done in wave32.

Totals from affected shaders:
SGPRS: 507726 -> 508006 (0.06 %)
VGPRS: 450340 -> 450268 (-0.02 %)
Spilled SGPRs: 298 -> 298 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 39689708 -> 39384488 (-0.77 %) bytes
Max Waves: 39631 -> 39636 (0.01 %)
Instructions: 7865919 -> 7793650 (-0.92 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
22 months agonv50ir/nir: support vec8 and vec16
Karol Herbst [Sat, 9 Mar 2019 17:20:38 +0000 (18:20 +0100)]
nv50ir/nir: support vec8 and vec16

Signed-off-by: Karol Herbst <kherbst@redhat.com>
22 months agonir+vtn: vec8+vec16 support
Rob Clark [Sat, 9 Mar 2019 16:17:55 +0000 (17:17 +0100)]
nir+vtn: vec8+vec16 support

This introduces new vec8 and vec16 instructions (which are the only
instructions taking more than 4 sources), in order to construct 8 and 16
component vectors.

In order to avoid fixing up the non-autogenerated nir_build_alu() sites
and making them pass 16 src args for the benefit of the two instructions
that take more than 4 srcs (ie vec8 and vec16), nir_build_alu() is has
nir_build_alu_tail() split out and re-used by nir_build_alu2() (which is
used for the > 4 src args case).

v2 (Karol Herbst):
  use nir_build_alu2 for vec8 and vec16
  use python's array multiplication syntax
  add nir_op_vec helper
  simplify nir_vec
  nir_build_alu_tail -> nir_builder_alu_instr_finish_and_insert
  use nir_build_alu for opcodes with <= 4 sources
v3 (Karol Herbst):
  fix nir_serialize
v4 (Dave Airlie):
  fix serialization of glsl_type
  handle vec8/16 in lowering of bools
v5 (Karol Herbst):
  fix load store vectorizer

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
22 months agoaco: use NIR_MAX_VEC_COMPONENTS instead of 4
Karol Herbst [Sat, 9 Nov 2019 21:39:36 +0000 (22:39 +0100)]
aco: use NIR_MAX_VEC_COMPONENTS instead of 4

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
22 months agonir/serialize: cast swizzle before shifting
Karol Herbst [Wed, 11 Dec 2019 15:01:15 +0000 (16:01 +0100)]
nir/serialize: cast swizzle before shifting

fixes undefined behaviour with enabled vec16

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
22 months agollvmpipe: switch to NIR by default
Dave Airlie [Tue, 3 Dec 2019 05:23:45 +0000 (15:23 +1000)]
llvmpipe: switch to NIR by default

Add LP_DEBUG=tgsi_ir (tgsi already taken) to fallback to TGSI paths.

Disable NIR_VALIDATE in CI (Michel/Eric acked)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2303>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2303>

22 months agogallivm/nir: wrap idiv to avoid divide by 0 (v2)
Dave Airlie [Fri, 13 Dec 2019 03:09:42 +0000 (13:09 +1000)]
gallivm/nir: wrap idiv to avoid divide by 0 (v2)

This code is taken from the TGSI paths, and should fix the regression
seens with GLES2

v2: use the udiv path which has d3d10 defined return.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2303>

22 months agoac/surface: fix an assertion failure on gfx9 in CMASK computation
Marek Olšák [Fri, 20 Dec 2019 21:19:54 +0000 (16:19 -0500)]
ac/surface: fix an assertion failure on gfx9 in CMASK computation

addrlib only allows the 2D resource type with CMASK.

Fixes: 69ea473eeb9 "amd/addrlib: update to the latest version"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3187>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3187>

22 months agopan/midgard: Optimize comparisions with similar operations
Afonso Bordado [Tue, 10 Dec 2019 13:18:00 +0000 (13:18 +0000)]
pan/midgard: Optimize comparisions with similar operations

Optimizes comparisions by removing the invert flag on operands
which we can prove to be equal without the invert.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3036>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3036>

22 months agolima: set shader caps to optimize control flow
Erico Nunes [Thu, 19 Dec 2019 21:51:07 +0000 (22:51 +0100)]
lima: set shader caps to optimize control flow

With these new caps, nir is able to unroll loops and optimize
conditionals much more efficiently in both gpit and ppir.
panfrost and vc4 were used as reference for the values.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3176>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3176>

22 months agolima/ppir: remove assert on ppir_emit_tex unsupported feature
Erico Nunes [Thu, 19 Dec 2019 21:49:49 +0000 (22:49 +0100)]
lima/ppir: remove assert on ppir_emit_tex unsupported feature

This assert causes testing tools such as shaderdb to abort on some test
cases. This is an unsupported feature and not a compiler bug. The
compilation error is already propagated correctly, so we can remove the
assert to allow testing tools to run to completion.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3176>

22 months agolima/ppir: fix lod bias src
Erico Nunes [Fri, 20 Dec 2019 18:20:58 +0000 (19:20 +0100)]
lima/ppir: fix lod bias src

ppir has some code that operates on all ppir_src variables, and for that
uses ppir_node_get_src.
lod bias support introduced a separate ppir_src that is inaccessible by
that function, causing it to be missed by the compiler in some routines.
Ultimately this caused, in some cases, a bug in const lowering:

  .../pp/lower.c:42: ppir_lower_const: Assertion `src != NULL' failed.

This fix moves the ppir_srcs in ppir_load_texture_node together so they
don't get missed.

Fixes: 721d82cf061 lima/ppir: add lod-bias support
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3185>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3185>

22 months agolima: Fix dump file creation
Andreas Baierl [Fri, 20 Dec 2019 10:30:05 +0000 (11:30 +0100)]
lima: Fix dump file creation

Otherwise lima_dump_file_next() always opens a new file and creates the
dumps regardless of what the environment variables say.

Fixes d71cd245d74 ('lima: Rotate dump files after each finished pp frame')

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3179>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3179>

22 months agoradeon/vcn2: enable rate control for hevc encoding
Pierre-Eric Pelloux-Prayer [Tue, 17 Dec 2019 09:41:39 +0000 (10:41 +0100)]
radeon/vcn2: enable rate control for hevc encoding

Based on b0626c1f306 ("radeon/vcn: enable rate control for hevc encoding").

Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225
Fixes: 587b9c5dae6 ("radeon/vcn: implement vcn 2.0 encode")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>

22 months agoradv: rely on pipeline layout when creating push descriptors with template
Samuel Pitoiset [Fri, 20 Dec 2019 12:30:28 +0000 (13:30 +0100)]
radv: rely on pipeline layout when creating push descriptors with template

descriptorSetLayout should be ignored for push descriptors. While
we are it, also ignore pipelineBindPoint.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2210
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3180>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3180>

22 months agoetnaviv: Replace bitwise OR with logical OR
Marek Vasut [Mon, 18 Nov 2019 18:12:49 +0000 (19:12 +0100)]
etnaviv: Replace bitwise OR with logical OR

The test here is testing whether either variable is non-zero.
While currently the test works fine, it's fragile. Replace it
with logical OR to avoid the fragility.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
22 months agoetnaviv: update resource status after flushing
Christian Gmeiner [Fri, 29 Nov 2019 08:44:43 +0000 (09:44 +0100)]
etnaviv: update resource status after flushing

Currently piglit spec@arb_occlusion_query@occlusion_query_conform
spins for ever as the resource status is never reset. See
etna_hw_get_query_result(..) for more details.

Fixes: 1456aa61cc5 ("etnaviv: Rework resource status tracking")
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marek Vasut <marex@denx.de>
22 months agointel: limit shader geometry on BDW GT1
Ross Zwisler [Thu, 19 Dec 2019 02:56:24 +0000 (19:56 -0700)]
intel: limit shader geometry on BDW GT1

Similar to the SKL GT1 fix introduced here:

https://gitlab.freedesktop.org/asimiklit/mesa/commit/b1ba7ffdbd54fdb5da18d086c7b7a830e06a1cff

we need to limit the .urb.max_entries[MESA_SHADER_GEOMETRY] on BDW GT1
to address failures in these two tests:

dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d
dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_2d_array

The value 690 was found via bisection.  691 is the actual max on the
hardware I'm using, but 690 seemed like a nice round number.

Signed-off-by: Ross Zwisler <zwisler@google.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3173>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3173>

22 months agopan/midgard: Lower txd with lower_tex
Alyssa Rosenzweig [Thu, 19 Dec 2019 16:12:50 +0000 (11:12 -0500)]
pan/midgard: Lower txd with lower_tex

This is a hack since we do have native gradient stuff, but for the
moment I'm more interested in conformance and the lowered code is good
enough. Fixes
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler2d_fixed_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>

22 months agopan/midgard: Fix crash with txs
Alyssa Rosenzweig [Thu, 19 Dec 2019 16:12:25 +0000 (11:12 -0500)]
pan/midgard: Fix crash with txs

This regressed since we implemented RECT textures natively, oops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>

22 months agopan/midgard: Implement textureOffset for 2D textures
Alyssa Rosenzweig [Thu, 19 Dec 2019 15:35:18 +0000 (10:35 -0500)]
pan/midgard: Implement textureOffset for 2D textures

Fixes dEQP-GLES3.functional.shaders.texture_functions.textureoffset.sampler2d_fixed_fragment.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>

22 months agoradv: ignore pColorBlendState if rasterization is disabled
Samuel Pitoiset [Thu, 19 Dec 2019 14:03:41 +0000 (15:03 +0100)]
radv: ignore pColorBlendState if rasterization is disabled

Or if the subpass has no color attachments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>

22 months agoradv: tidy up radv_pipeline_init_blend_state()
Samuel Pitoiset [Thu, 19 Dec 2019 14:52:13 +0000 (15:52 +0100)]
radv: tidy up radv_pipeline_init_blend_state()

This is needed for the next commit because pColorBlendState can
actually be NULL but some fields might have to be initialized
(eg. alpha to coverage with no color attachments).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>

22 months agoradv: ignore pDepthStencilState if rasterization is disabled
Samuel Pitoiset [Thu, 19 Dec 2019 13:26:45 +0000 (14:26 +0100)]
radv: ignore pDepthStencilState if rasterization is disabled

Or if the subpass has no depth stencil attachment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>

22 months agoradv: ignore pTessellationState if the pipeline doesn't use tess
Samuel Pitoiset [Thu, 19 Dec 2019 13:18:24 +0000 (14:18 +0100)]
radv: ignore pTessellationState if the pipeline doesn't use tess

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>