mesa.git
3 years agov3d: Emit the VCM_CACHE_SIZE packet.
Eric Anholt [Thu, 2 Aug 2018 19:23:02 +0000 (12:23 -0700)]
v3d: Emit the VCM_CACHE_SIZE packet.

This is needed to ensure that we don't get blocked waiting for VPM space
with bin/render overlapping.

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
3 years agov3d: Drop "VC5" from the renderer string.
Eric Anholt [Thu, 2 Aug 2018 19:15:20 +0000 (12:15 -0700)]
v3d: Drop "VC5" from the renderer string.

VC5 isn't a useful name any more, just stick to v3d.

3 years agov3d: Avoid spilling that breaks the r5 usage after a ldvary.
Eric Anholt [Thu, 2 Aug 2018 18:12:37 +0000 (11:12 -0700)]
v3d: Avoid spilling that breaks the r5 usage after a ldvary.

Fixes bad rendering when forcing 2 spills in glxgears.

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
3 years agov3d: Make sure that QPU instruction-has-a-dest matches VIR.
Eric Anholt [Thu, 2 Aug 2018 00:47:13 +0000 (17:47 -0700)]
v3d: Make sure that QPU instruction-has-a-dest matches VIR.

Found when debugging register spilling -- we would try to spill the dest
of a STVPMV, inserting spill code after entering the last segment.  In
fact, we were likely to to choose to do this, given that the STVPMV "dest"
temp was never read from, making it cheap to spill.

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
3 years agov3d: Wait for TMU writes to complete before continuing after a spill.
Eric Anholt [Wed, 1 Aug 2018 23:56:38 +0000 (16:56 -0700)]
v3d: Wait for TMU writes to complete before continuing after a spill.

The simulator complained that we had write responses outstanding at shader
end.  It seems that a TMU read does not guarantee that previous TMU writes
by the thread have completed, which surprised me.

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
3 years agov3d: Make sure we don't emit a thrsw before the last one finished.
Eric Anholt [Wed, 1 Aug 2018 23:37:08 +0000 (16:37 -0700)]
v3d: Make sure we don't emit a thrsw before the last one finished.

Found while forcing some spilling, which creates a lot of short
tmua->thrsw->ldtmu sequences.

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
3 years agov3d: Add some debug code for forcing register spilling.
Eric Anholt [Thu, 2 Aug 2018 00:38:25 +0000 (17:38 -0700)]
v3d: Add some debug code for forcing register spilling.

This is useful for periodically testing out register spilling to see how
it goes on simple shaders, rather than only failing on insanely
complicated ones.

3 years agodrisw: Fix build on Android Nougat, which lacks shm (v2)
Chad Versace [Thu, 19 Jul 2018 00:43:35 +0000 (17:43 -0700)]
drisw: Fix build on Android Nougat, which lacks shm (v2)

In commit cf54bd5e8, dri_sw_winsys.c began using <sys/shm.h> to support
the new functions putImageShm, getImageShm in DRI_SWRastLoader. But
Android began supporting System V shared memory only in Oreo. Nougat has
no shm headers.

Fix the build by ifdef'ing out the shm code on Nougat.

Fixes: cf54bd5e8 "drisw: use shared memory when possible"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@gmail.com>
3 years agomesa: fix make check for AMD_framebuffer_multisample_advanced
Ian Romanick [Sun, 5 Aug 2018 19:37:08 +0000 (12:37 -0700)]
mesa: fix make check for AMD_framebuffer_multisample_advanced

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107483
Fixes: 3d6900d76ef ("glapi: define AMD_framebuffer_multisample_advanced and add its functions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Vinson Lee <vlee@freedesktop.org>
3 years agoglapi: Fix GLES versioning for AMD_framebuffer_multisample_advanced functions
Ian Romanick [Sun, 5 Aug 2018 19:35:42 +0000 (12:35 -0700)]
glapi: Fix GLES versioning for AMD_framebuffer_multisample_advanced functions

The GL_AMD_framebuffer_multisample_advanced spec says:

    OpenGL ES dependencies:

        Requires OpenGL ES 3.0.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107483
Fixes: 3d6900d76ef ("glapi: define AMD_framebuffer_multisample_advanced and add its functions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Vinson Lee <vlee@freedesktop.org>
3 years agomeson, install_megadrivers: Also remove stale symlinks
Gert Wollny [Fri, 3 Aug 2018 09:47:28 +0000 (11:47 +0200)]
meson, install_megadrivers: Also remove stale symlinks

os.path.exists doesn't return True for stale symlinks, but they are in
the way later, when a link/file with the same name is to be created.
For instance it is conceivable that the pointed to file is replaced by
a file with a new name, and then the symlink is dead.

To handle this check specifically for all existing symlinks to be
removed. (This bugged me for some time with a link libXvMCr600.so
always being in the way of installing this file)

v2: use only os.lexist and replace all instances of os.exist (Dylan Baker)

v3: handle directory check correctly (Eric Engestrom)

Fixes: f7f1b30f81e842db6057591470ce3cb6d4fb2795
       ("meson: extend install_megadrivers script to handle symmlinking")

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>(v2 minus dir check)
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
3 years agoanv: add more swapchain formats
Tapani Pälli [Wed, 25 Jul 2018 11:26:33 +0000 (14:26 +0300)]
anv: add more swapchain formats

This change helps with some of the dEQP-VK.wsi.android.* tests that
try to create swapchain with using such formats.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
3 years agonvc0/ir: return 0 in imageLoad on incomplete textures
Karol Herbst [Sat, 23 Jun 2018 17:01:34 +0000 (19:01 +0200)]
nvc0/ir: return 0 in imageLoad on incomplete textures

We already guarded all OP_SULDP against out of bound accesses, but we
ended up just reusing whatever value was stored in the dest registers.

Fixes CTS test shader_image_load_store.incomplete_textures

v2: fix for loads not ending up with predicates (bindless_texture)
v3: fix replacing the def

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
3 years agogm200/ir: optimize rcp(sqrt) to rsq
Karol Herbst [Sat, 4 Aug 2018 02:19:49 +0000 (04:19 +0200)]
gm200/ir: optimize rcp(sqrt) to rsq

mitigates hurt shaders after adding sqrt:
total instructions in shared programs : 5456166 -> 5454825 (-0.02%)
total gprs used in shared programs    : 647522 -> 647551 (0.00%)
total shared used in shared programs  : 389120 -> 389120 (0.00%)
total local used in shared programs   : 21064 -> 21064 (0.00%)
total bytes used in shared programs   : 58288696 -> 58274448 (-0.02%)

                local     shared        gpr       inst      bytes
    helped           0           0           0         516         516
      hurt           0           0          27           2           2

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
3 years agogm200/ir: add native OP_SQRT support
Karol Herbst [Sat, 4 Aug 2018 01:13:11 +0000 (03:13 +0200)]
gm200/ir: add native OP_SQRT support

./GpuTest /test=pixmark_piano 1024x640 30sec:
301 -> 327 points

shader-db:
total instructions in shared programs : 5472103 -> 5456166 (-0.29%)
total gprs used in shared programs    : 647530 -> 647522 (-0.00%)
total shared used in shared programs  : 389120 -> 389120 (0.00%)
total local used in shared programs   : 21064 -> 21064 (0.00%)
total bytes used in shared programs   : 58459304 -> 58288696 (-0.29%)

                local     shared        gpr       inst      bytes
    helped           0           0          27        8281        8281
      hurt           0           0          21         431         431

v2: use NVISA_GM200_CHIPSET

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
3 years agointel: tools: simplify meson build
Lionel Landwerlin [Sat, 28 Jul 2018 13:51:56 +0000 (14:51 +0100)]
intel: tools: simplify meson build

Remove the if tools condition and just put it through the install:
parameter.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agointel: aubinator: simplify decoding
Lionel Landwerlin [Sat, 28 Jul 2018 13:27:49 +0000 (14:27 +0100)]
intel: aubinator: simplify decoding

Since we don't support streaming an aub file, we can drop the decoding
status enum.

v2: include stdbool (Eric)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agointel: common: add missing stdint include
Lionel Landwerlin [Sat, 28 Jul 2018 18:11:56 +0000 (19:11 +0100)]
intel: common: add missing stdint include

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agointel: decoder: remove unused variable
Lionel Landwerlin [Mon, 30 Jul 2018 01:55:54 +0000 (02:55 +0100)]
intel: decoder: remove unused variable

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agointel: tools: aubwrite: reuse canonical address helper
Lionel Landwerlin [Tue, 31 Jul 2018 09:48:37 +0000 (10:48 +0100)]
intel: tools: aubwrite: reuse canonical address helper

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agointel: aubinator: fix read the context/ring
Lionel Landwerlin [Tue, 31 Jul 2018 06:12:56 +0000 (07:12 +0100)]
intel: aubinator: fix read the context/ring

Up to now we've been lucky that the buffer returned was always exactly
at the address we requested.

Fixes: 144b40db5411 ("intel: aubinator: drop the 1Tb GTT mapping")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
3 years agonir: Transform expressions of b2f(a) and b2f(b) to a == b
Ian Romanick [Thu, 2 Aug 2018 02:34:02 +0000 (19:34 -0700)]
nir: Transform expressions of b2f(a) and b2f(b) to a == b

All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14276886 -> 14276838 (<.01%)
instructions in affected programs: 312 -> 264 (-15.38%)
helped: 2
HURT: 0

total cycles in shared programs: 532578395 -> 532570985 (<.01%)
cycles in affected programs: 682562 -> 675152 (-1.09%)
helped: 374
HURT: 4
helped stats (abs) min: 2 max: 200 x̄: 20.39 x̃: 18
helped stats (rel) min: 0.07% max: 11.64% x̄: 1.25% x̃: 1.28%
HURT stats (abs)   min: 2 max: 114 x̄: 53.50 x̃: 49
HURT stats (rel)   min: 0.06% max: 11.70% x̄: 5.02% x̃: 4.15%
95% mean confidence interval for cycles value: -21.30 -17.91
95% mean confidence interval for cycles %-change: -1.30% -1.06%
Cycles are helped.

Sandy Bridge
total instructions in shared programs: 10488123 -> 10488075 (<.01%)
instructions in affected programs: 336 -> 288 (-14.29%)
helped: 2
HURT: 0

total cycles in shared programs: 150260379 -> 150260439 (<.01%)
cycles in affected programs: 4726 -> 4786 (1.27%)
helped: 0
HURT: 2

No changes on Iron Lake or GM45.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform expressions of b2f(a) and b2f(b) to a ^^ b
Ian Romanick [Thu, 2 Aug 2018 02:33:24 +0000 (19:33 -0700)]
nir: Transform expressions of b2f(a) and b2f(b) to a ^^ b

All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14276892 -> 14276886 (<.01%)
instructions in affected programs: 484 -> 478 (-1.24%)
helped: 2
HURT: 0

total cycles in shared programs: 532578397 -> 532578395 (<.01%)
cycles in affected programs: 3522 -> 3520 (-0.06%)
helped: 1
HURT: 0

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform expressions of b2f(a) and b2f(b) to !(a && b)
Ian Romanick [Thu, 2 Aug 2018 02:32:18 +0000 (19:32 -0700)]
nir: Transform expressions of b2f(a) and b2f(b) to !(a && b)

All Gen platforms had pretty similar results. (Skylake shown)
total cycles in shared programs: 532578400 -> 532578397 (<.01%)
cycles in affected programs: 2784 -> 2781 (-0.11%)
helped: 1
HURT: 1
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.26% max: 0.26% x̄: 0.26% x̃: 0.26%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.08% max: 0.08% x̄: 0.08% x̃: 0.08%

v2: s/fmax/fmin/.  Noticed by Thomas Helland.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform expressions of b2f(a) and b2f(b) to a && b
Ian Romanick [Thu, 2 Aug 2018 02:31:22 +0000 (19:31 -0700)]
nir: Transform expressions of b2f(a) and b2f(b) to a && b

No changes on any Gen platform.

v2: s/fmax/fmin/.  Noticed by Thomas Helland.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform expressions of b2f(a) and b2f(b) to !(a || b)
Ian Romanick [Thu, 2 Aug 2018 02:27:01 +0000 (19:27 -0700)]
nir: Transform expressions of b2f(a) and b2f(b) to !(a || b)

All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14276961 -> 14276892 (<.01%)
instructions in affected programs: 3215 -> 3146 (-2.15%)
helped: 28
HURT: 0
helped stats (abs) min: 1 max: 6 x̄: 2.46 x̃: 2
helped stats (rel) min: 0.47% max: 9.52% x̄: 4.34% x̃: 1.92%
95% mean confidence interval for instructions value: -2.87 -2.06
95% mean confidence interval for instructions %-change: -5.73% -2.95%
Instructions are helped.

total cycles in shared programs: 532577068 -> 532578400 (<.01%)
cycles in affected programs: 121864 -> 123196 (1.09%)
helped: 35
HURT: 30
helped stats (abs) min: 2 max: 268 x̄: 42.34 x̃: 22
helped stats (rel) min: 0.12% max: 12.14% x̄: 3.22% x̃: 1.86%
HURT stats (abs)   min: 2 max: 246 x̄: 93.80 x̃: 36
HURT stats (rel)   min: 0.09% max: 13.63% x̄: 4.47% x̃: 2.58%
95% mean confidence interval for cycles value: -5.02 46.01
95% mean confidence interval for cycles %-change: -0.99% 1.65%
Inconclusive result (value mean confidence interval includes 0).

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 7781299 -> 7781342 (<.01%)
instructions in affected programs: 22300 -> 22343 (0.19%)
helped: 13
HURT: 40
helped stats (abs) min: 2 max: 3 x̄: 2.85 x̃: 3
helped stats (rel) min: 1.15% max: 7.69% x̄: 3.72% x̃: 3.33%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.26% max: 1.30% x̄: 0.47% x̃: 0.43%
95% mean confidence interval for instructions value: 0.23 1.39
95% mean confidence interval for instructions %-change: -1.18% 0.07%
Inconclusive result (%-change mean confidence interval includes 0).

total cycles in shared programs: 177878928 -> 177879332 (<.01%)
cycles in affected programs: 383298 -> 383702 (0.11%)
helped: 7
HURT: 43
helped stats (abs) min: 2 max: 18 x̄: 10.00 x̃: 10
helped stats (rel) min: 0.17% max: 4.81% x̄: 2.62% x̃: 3.40%
HURT stats (abs)   min: 2 max: 38 x̄: 11.02 x̃: 12
HURT stats (rel)   min: 0.08% max: 1.54% x̄: 0.25% x̃: 0.09%
95% mean confidence interval for cycles value: 5.21 10.95
95% mean confidence interval for cycles %-change: -0.51% 0.21%
Inconclusive result (%-change mean confidence interval includes 0).

v2: s/fmin/fmax/.  Noticed by Thomas Helland.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform -fabs(a) >= 0 to a == 0
Ian Romanick [Thu, 2 Aug 2018 02:46:26 +0000 (19:46 -0700)]
nir: Transform -fabs(a) >= 0 to a == 0

All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14276964 -> 14276961 (<.01%)
instructions in affected programs: 411 -> 408 (-0.73%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.47% max: 1.96% x̄: 1.04% x̃: 0.68%

total cycles in shared programs: 532577062 -> 532577068 (<.01%)
cycles in affected programs: 1093 -> 1099 (0.55%)
helped: 1
HURT: 1
helped stats (abs) min: 16 max: 16 x̄: 16.00 x̃: 16
helped stats (rel) min: 7.77% max: 7.77% x̄: 7.77% x̃: 7.77%
HURT stats (abs)   min: 22 max: 22 x̄: 22.00 x̃: 22
HURT stats (rel)   min: 2.48% max: 2.48% x̄: 2.48% x̃: 2.48%

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform expressions of b2f(a) and b2f(b) to a || b
Ian Romanick [Thu, 2 Aug 2018 00:18:07 +0000 (17:18 -0700)]
nir: Transform expressions of b2f(a) and b2f(b) to a || b

All Gen6+ platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277184 -> 14276964 (<.01%)
instructions in affected programs: 10082 -> 9862 (-2.18%)
helped: 37
HURT: 1
helped stats (abs) min: 1 max: 30 x̄: 5.97 x̃: 4
helped stats (rel) min: 0.14% max: 16.00% x̄: 5.23% x̃: 2.04%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.70% max: 0.70% x̄: 0.70% x̃: 0.70%
95% mean confidence interval for instructions value: -7.87 -3.71
95% mean confidence interval for instructions %-change: -6.98% -3.16%
Instructions are helped.

total cycles in shared programs: 532577990 -> 532577062 (<.01%)
cycles in affected programs: 170959 -> 170031 (-0.54%)
helped: 33
HURT: 9
helped stats (abs) min: 2 max: 120 x̄: 30.91 x̃: 30
helped stats (rel) min: 0.02% max: 7.65% x̄: 2.66% x̃: 1.13%
HURT stats (abs)   min: 2 max: 24 x̄: 10.22 x̃: 8
HURT stats (rel)   min: 0.09% max: 1.79% x̄: 0.61% x̃: 0.22%
95% mean confidence interval for cycles value: -31.23 -12.96
95% mean confidence interval for cycles %-change: -2.90% -1.02%
Cycles are helped.

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 7781539 -> 7781301 (<.01%)
instructions in affected programs: 10169 -> 9931 (-2.34%)
helped: 32
HURT: 0
helped stats (abs) min: 2 max: 20 x̄: 7.44 x̃: 6
helped stats (rel) min: 0.47% max: 17.02% x̄: 4.03% x̃: 1.88%
95% mean confidence interval for instructions value: -9.53 -5.34
95% mean confidence interval for instructions %-change: -5.94% -2.12%
Instructions are helped.

total cycles in shared programs: 177878590 -> 177878932 (<.01%)
cycles in affected programs: 78706 -> 79048 (0.43%)
helped: 7
HURT: 21
helped stats (abs) min: 6 max: 34 x̄: 24.57 x̃: 28
helped stats (rel) min: 0.15% max: 8.33% x̄: 4.66% x̃: 6.37%
HURT stats (abs)   min: 2 max: 86 x̄: 24.48 x̃: 22
HURT stats (rel)   min: 0.01% max: 4.28% x̄: 1.21% x̃: 0.70%
95% mean confidence interval for cycles value: 0.30 24.13
95% mean confidence interval for cycles %-change: -1.52% 1.01%
Inconclusive result (%-change mean confidence interval includes 0).

v2: s/fmin/fmax/.  Noticed by Thomas Helland.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Transform -fabs(a) < 0 to a != 0
Ian Romanick [Fri, 27 Jul 2018 01:26:18 +0000 (18:26 -0700)]
nir: Transform -fabs(a) < 0 to a != 0

Unlike the much older -abs(a) >= 0.0 transformation, this is not
precise.  The behavior changes if a is NaN.

All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277216 -> 14277184 (<.01%)
instructions in affected programs: 2300 -> 2268 (-1.39%)
helped: 8
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 4.00 x̃: 3
helped stats (rel) min: 0.48% max: 15.15% x̄: 4.41% x̃: 1.01%
95% mean confidence interval for instructions value: -6.45 -1.55
95% mean confidence interval for instructions %-change: -9.96% 1.13%
Inconclusive result (%-change mean confidence interval includes 0).

total cycles in shared programs: 532577848 -> 532577990 (<.01%)
cycles in affected programs: 17486 -> 17628 (0.81%)
helped: 2
HURT: 5
helped stats (abs) min: 2 max: 6 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.06% max: 1.81% x̄: 0.93% x̃: 0.93%
HURT stats (abs)   min: 6 max: 50 x̄: 30.00 x̃: 26
HURT stats (rel)   min: 0.55% max: 2.17% x̄: 1.19% x̃: 1.02%
95% mean confidence interval for cycles value: -1.06 41.63
95% mean confidence interval for cycles %-change: -0.58% 1.74%
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Rearrange bcsel with two bcsel sources
Ian Romanick [Wed, 1 Aug 2018 23:51:35 +0000 (16:51 -0700)]
nir: Rearrange bcsel with two bcsel sources

All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277220 -> 14277216 (<.01%)
instructions in affected programs: 422 -> 418 (-0.95%)
helped: 2
HURT: 0

total cycles in shared programs: 532577908 -> 532577848 (<.01%)
cycles in affected programs: 2800 -> 2740 (-2.14%)
helped: 2
HURT: 0

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Collapse more repeated bcsels on the same argument
Ian Romanick [Wed, 1 Aug 2018 16:58:19 +0000 (09:58 -0700)]
nir: Collapse more repeated bcsels on the same argument

All Gen platforms had pretty similar results. (Skylake shown)
total instructions in shared programs: 14277230 -> 14277220 (<.01%)
instructions in affected programs: 751 -> 741 (-1.33%)
helped: 4
HURT: 0
helped stats (abs) min: 2 max: 3 x̄: 2.50 x̃: 2
helped stats (rel) min: 1.23% max: 1.40% x̄: 1.32% x̃: 1.32%
95% mean confidence interval for instructions value: -3.42 -1.58
95% mean confidence interval for instructions %-change: -1.47% -1.17%
Instructions are helped.

total cycles in shared programs: 532577947 -> 532577908 (<.01%)
cycles in affected programs: 10641 -> 10602 (-0.37%)
helped: 4
HURT: 3
helped stats (abs) min: 1 max: 40 x̄: 13.75 x̃: 7
helped stats (rel) min: 0.11% max: 3.08% x̄: 1.10% x̃: 0.60%
HURT stats (abs)   min: 2 max: 8 x̄: 5.33 x̃: 6
HURT stats (rel)   min: 0.13% max: 0.55% x̄: 0.30% x̃: 0.23%
95% mean confidence interval for cycles value: -20.69 9.55
95% mean confidence interval for cycles %-change: -1.63% 0.63%
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir: Don't compare i2f or u2i with zero
Ian Romanick [Tue, 3 Jul 2018 19:39:54 +0000 (12:39 -0700)]
nir: Don't compare i2f or u2i with zero

Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14277620 -> 14277230 (<.01%)
instructions in affected programs: 36905 -> 36515 (-1.06%)
helped: 101
HURT: 6
helped stats (abs) min: 1 max: 6 x̄: 4.46 x̃: 6
helped stats (rel) min: 0.32% max: 7.69% x̄: 1.80% x̃: 1.51%
HURT stats (abs)   min: 1 max: 28 x̄: 10.00 x̃: 1
HURT stats (rel)   min: 0.33% max: 1.74% x̄: 0.68% x̃: 0.47%
95% mean confidence interval for instructions value: -4.59 -2.70
95% mean confidence interval for instructions %-change: -1.90% -1.41%
Instructions are helped.

total cycles in shared programs: 532580716 -> 532577947 (<.01%)
cycles in affected programs: 940575 -> 937806 (-0.29%)
helped: 92
HURT: 12
helped stats (abs) min: 2 max: 158 x̄: 51.04 x̃: 62
helped stats (rel) min: 0.24% max: 3.99% x̄: 2.14% x̃: 2.41%
HURT stats (abs)   min: 10 max: 1112 x̄: 160.58 x̃: 63
HURT stats (rel)   min: 0.06% max: 21.90% x̄: 4.22% x̃: 0.20%
95% mean confidence interval for cycles value: -50.66 -2.59
95% mean confidence interval for cycles %-change: -2.09% -0.73%
Cycles are helped.

total spills in shared programs: 8116 -> 8124 (0.10%)
spills in affected programs: 200 -> 208 (4.00%)
helped: 0
HURT: 2

total fills in shared programs: 11086 -> 11094 (0.07%)
fills in affected programs: 436 -> 444 (1.83%)
helped: 0
HURT: 2

Ivy Bridge and Haswell had similar results. (Haswell shown)
total instructions in shared programs: 12979054 -> 12978067 (<.01%)
instructions in affected programs: 33633 -> 32646 (-2.93%)
helped: 120
HURT: 2
helped stats (abs) min: 1 max: 13 x̄: 8.53 x̃: 13
helped stats (rel) min: 0.30% max: 16.67% x̄: 4.55% x̃: 3.17%
HURT stats (abs)   min: 18 max: 18 x̄: 18.00 x̃: 18
HURT stats (rel)   min: 1.15% max: 2.84% x̄: 2.00% x̃: 2.00%
95% mean confidence interval for instructions value: -9.19 -6.99
95% mean confidence interval for instructions %-change: -5.27% -3.62%
Instructions are helped.

total cycles in shared programs: 411212880 -> 411199636 (<.01%)
cycles in affected programs: 696441 -> 683197 (-1.90%)
helped: 107
HURT: 5
helped stats (abs) min: 2 max: 864 x̄: 124.90 x̃: 146
helped stats (rel) min: 0.03% max: 29.20% x̄: 8.58% x̃: 5.88%
HURT stats (abs)   min: 2 max: 50 x̄: 24.00 x̃: 22
HURT stats (rel)   min: 0.01% max: 5.35% x̄: 1.29% x̃: 0.25%
95% mean confidence interval for cycles value: -136.96 -99.54
95% mean confidence interval for cycles %-change: -9.75% -6.53%
Cycles are helped.

total spills in shared programs: 78623 -> 78631 (0.01%)
spills in affected programs: 66 -> 74 (12.12%)
helped: 0
HURT: 2

total fills in shared programs: 80104 -> 80108 (<.01%)
fills in affected programs: 133 -> 137 (3.01%)
helped: 0
HURT: 2

No changes on Sandy Bridge, Iron Lake, or GM45.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Remove f2i(i2f(x)) conversions
Ian Romanick [Tue, 3 Jul 2018 20:57:06 +0000 (13:57 -0700)]
nir: Remove f2i(i2f(x)) conversions

Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14277978 -> 14277620 (<.01%)
instructions in affected programs: 36957 -> 36599 (-0.97%)
helped: 76
HURT: 1
helped stats (abs) min: 2 max: 90 x̄: 4.89 x̃: 4
helped stats (rel) min: 0.44% max: 5.88% x̄: 1.04% x̃: 0.87%
HURT stats (abs)   min: 14 max: 14 x̄: 14.00 x̃: 14
HURT stats (rel)   min: 0.36% max: 0.36% x̄: 0.36% x̃: 0.36%
95% mean confidence interval for instructions value: -7.06 -2.24
95% mean confidence interval for instructions %-change: -1.28% -0.77%
Instructions are helped.

total cycles in shared programs: 532584581 -> 532580716 (<.01%)
cycles in affected programs: 973591 -> 969726 (-0.40%)
helped: 76
HURT: 1
helped stats (abs) min: 2 max: 9940 x̄: 159.80 x̃: 32
helped stats (rel) min: <.01% max: 8.70% x̄: 1.15% x̃: 1.19%
HURT stats (abs)   min: 8280 max: 8280 x̄: 8280.00 x̃: 8280
HURT stats (rel)   min: 2.10% max: 2.10% x̄: 2.10% x̃: 2.10%
95% mean confidence interval for cycles value: -386.98 286.59
95% mean confidence interval for cycles %-change: -1.41% -0.81%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 8127 -> 8116 (-0.14%)
spills in affected programs: 108 -> 97 (-10.19%)
helped: 1
HURT: 0

total fills in shared programs: 11090 -> 11086 (-0.04%)
fills in affected programs: 440 -> 436 (-0.91%)
helped: 1
HURT: 1

Haswell
total instructions in shared programs: 12979174 -> 12979054 (<.01%)
instructions in affected programs: 9040 -> 8920 (-1.33%)
helped: 14
HURT: 1
helped stats (abs) min: 2 max: 34 x̄: 8.79 x̃: 6
helped stats (rel) min: 0.41% max: 7.04% x̄: 2.66% x̃: 1.14%
HURT stats (abs)   min: 3 max: 3 x̄: 3.00 x̃: 3
HURT stats (rel)   min: 0.19% max: 0.19% x̄: 0.19% x̃: 0.19%
95% mean confidence interval for instructions value: -13.58 -2.42
95% mean confidence interval for instructions %-change: -3.94% -1.01%
Instructions are helped.

total cycles in shared programs: 411227148 -> 411212880 (<.01%)
cycles in affected programs: 630506 -> 616238 (-2.26%)
helped: 15
HURT: 0
helped stats (abs) min: 2 max: 11192 x̄: 951.20 x̃: 38
helped stats (rel) min: <.01% max: 16.01% x̄: 3.92% x̃: 0.17%
95% mean confidence interval for cycles value: -2544.28 641.88
95% mean confidence interval for cycles %-change: -6.89% -0.94%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 78626 -> 78623 (<.01%)
spills in affected programs: 42 -> 39 (-7.14%)
helped: 1
HURT: 0

total fills in shared programs: 80111 -> 80104 (<.01%)
fills in affected programs: 140 -> 133 (-5.00%)
helped: 1
HURT: 1

Ivy Bridge
total instructions in shared programs: 11684101 -> 11684030 (<.01%)
instructions in affected programs: 3080 -> 3009 (-2.31%)
helped: 4
HURT: 1
helped stats (abs) min: 5 max: 59 x̄: 18.50 x̃: 5
helped stats (rel) min: 6.47% max: 7.04% x̄: 6.87% x̃: 6.99%
HURT stats (abs)   min: 3 max: 3 x̄: 3.00 x̃: 3
HURT stats (rel)   min: 0.15% max: 0.15% x̄: 0.15% x̃: 0.15%
95% mean confidence interval for instructions value: -45.59 17.19
95% mean confidence interval for instructions %-change: -9.38% -1.56%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 258407697 -> 258389653 (<.01%)
cycles in affected programs: 328323 -> 310279 (-5.50%)
helped: 5
HURT: 0
helped stats (abs) min: 32 max: 14908 x̄: 3608.80 x̃: 32
helped stats (rel) min: 1.26% max: 17.22% x̄: 9.30% x̃: 10.60%
95% mean confidence interval for cycles value: -11616.71 4399.11
95% mean confidence interval for cycles %-change: -16.56% -2.03%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 4537 -> 4528 (-0.20%)
spills in affected programs: 64 -> 55 (-14.06%)
helped: 1
HURT: 0

total fills in shared programs: 4823 -> 4815 (-0.17%)
fills in affected programs: 189 -> 181 (-4.23%)
helped: 1
HURT: 1

Sandy Bridge
total instructions in shared programs: 10488464 -> 10488449 (<.01%)
instructions in affected programs: 272 -> 257 (-5.51%)
helped: 3
HURT: 0
helped stats (abs) min: 5 max: 5 x̄: 5.00 x̃: 5
helped stats (rel) min: 5.49% max: 5.56% x̄: 5.51% x̃: 5.49%

total cycles in shared programs: 150263359 -> 150263263 (<.01%)
cycles in affected programs: 7978 -> 7882 (-1.20%)
helped: 3
HURT: 0
helped stats (abs) min: 32 max: 32 x̄: 32.00 x̃: 32
helped stats (rel) min: 1.15% max: 1.23% x̄: 1.20% x̃: 1.23%

No changes on Iron Lake or GM45.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agonir: Mark the 0.0 < abs(a) transformation as imprecise
Ian Romanick [Wed, 1 Aug 2018 17:13:55 +0000 (10:13 -0700)]
nir: Mark the 0.0 < abs(a) transformation as imprecise

Unlike the much older -abs(a) >= 0.0 transformation, this is not
precise.  The behavior changes if the source is NaN.

No shader-db changes on any platform.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
3 years agoradeonsi: cosmetic changes
Marek Olšák [Thu, 2 Aug 2018 20:39:41 +0000 (16:39 -0400)]
radeonsi: cosmetic changes

3 years agost/mesa: expose & set limits for AMD_framebuffer_multisample_advanced
Marek Olšák [Mon, 11 Jun 2018 22:54:26 +0000 (18:54 -0400)]
st/mesa: expose & set limits for AMD_framebuffer_multisample_advanced

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agost/mesa: add renderbuffer support for AMD_framebuffer_multisample_advanced
Marek Olšák [Mon, 11 Jun 2018 22:48:58 +0000 (18:48 -0400)]
st/mesa: add renderbuffer support for AMD_framebuffer_multisample_advanced

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agost/mesa: pass storage_sample_count parameter into st_choose_format
Marek Olšák [Mon, 11 Jun 2018 19:04:11 +0000 (15:04 -0400)]
st/mesa: pass storage_sample_count parameter into st_choose_format

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agomesa: add functional FBO changes for AMD_framebuffer_multisample_advanced
Marek Olšák [Mon, 11 Jun 2018 22:30:34 +0000 (18:30 -0400)]
mesa: add functional FBO changes for AMD_framebuffer_multisample_advanced

- relax FBO completeness rules
- validate sample counts

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agomesa: add gl_renderbuffer::NumStorageSamples
Marek Olšák [Mon, 11 Jun 2018 21:24:16 +0000 (17:24 -0400)]
mesa: add gl_renderbuffer::NumStorageSamples

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agomesa: implement glGet for AMD_framebuffer_multisample_advanced
Marek Olšák [Mon, 11 Jun 2018 19:10:50 +0000 (15:10 -0400)]
mesa: implement glGet for AMD_framebuffer_multisample_advanced

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agoglapi: define AMD_framebuffer_multisample_advanced and add its functions
Marek Olšák [Thu, 28 Jun 2018 06:05:12 +0000 (02:05 -0400)]
glapi: define AMD_framebuffer_multisample_advanced and add its functions

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agomesa: add storageSamples parameter to renderbuffer functions
Marek Olšák [Mon, 11 Jun 2018 19:26:41 +0000 (15:26 -0400)]
mesa: add storageSamples parameter to renderbuffer functions

It's just passed to other functions but otherwise unused.
It will be used in following commits.

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agoinclude: update GL & GLES headers (v2)
Marek Olšák [Wed, 18 Jul 2018 22:06:37 +0000 (18:06 -0400)]
include: update GL & GLES headers (v2)

v2: use correct files

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoamd: remove support for LLVM 5.0
Marek Olšák [Sun, 1 Jul 2018 19:50:51 +0000 (15:50 -0400)]
amd: remove support for LLVM 5.0

Users are encouraged to switch to LLVM 6.0 released in March 2018.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agowinsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0
Marek Olšák [Thu, 12 Jul 2018 04:50:52 +0000 (00:50 -0400)]
winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

3 years agogallium/u_vbuf: handle indirect multidraws correctly and efficiently (v3)
Marek Olšák [Tue, 17 Jul 2018 05:52:25 +0000 (01:52 -0400)]
gallium/u_vbuf: handle indirect multidraws correctly and efficiently (v3)

v2: need to do MAX{start+count} instead of MAX{count}
    added piglit tests
v3: use malloc

Cc: 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agoandroid: radv: build vulkan.radv conditionally to radeonsi
Mauro Rossi [Thu, 2 Aug 2018 19:07:31 +0000 (21:07 +0200)]
android: radv: build vulkan.radv conditionally to radeonsi

A problem was reported with arm,arm64 targets build due to missing
libLLVM shared library dependency with AOSP; to avoid this issue vulkan.radv
is built conditionally only when radeonsi is in BOARD_GPU_DRIVERS

Fixes: 0ca153f869 ("android: radv: enable build of vulkan.radv HAL module")
Reported-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
3 years agoutil: return 0 for NaNs in float_to_ubyte
Roland Scheidegger [Fri, 3 Aug 2018 03:34:07 +0000 (05:34 +0200)]
util: return 0 for NaNs in float_to_ubyte

d3d10 requires NaNs to get converted to 0 for float->unorm conversions
(and float->int etc.). GL spec probably doesn't care in general, but it
would make sense to have reasonable behavior in any case imho - the
old code was converting negative NaNs to 0, and positive NaNs to 255.
(Note that using float comparison isn't actually all that much more
effort in any case, at least with sse2 it's just float comparison
(ucommiss) instead of int one - I converted the second comparison
to float too simply because it saves the probably somewhat expensive
transfer of the float from simd to int domain (with sse2 via stack),
so the generated code actually has 2 less instructions, although float
comparisons are more expensive than int ones.)

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agoanv/pipeline: Disable FS dispatch for pointless fragment shaders
Jason Ekstrand [Wed, 11 Jul 2018 07:03:27 +0000 (00:03 -0700)]
anv/pipeline: Disable FS dispatch for pointless fragment shaders

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir: add fall through comment to nir_gather_info
Timothy Arceri [Thu, 2 Aug 2018 00:04:51 +0000 (10:04 +1000)]
nir: add fall through comment to nir_gather_info

This stops Coverity reporting a defect and helps make the code less
error-prone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoCleanSpec.mk: Remove HOST_OUT_release
Dan Willemsen [Wed, 1 Aug 2018 23:20:38 +0000 (16:20 -0700)]
CleanSpec.mk: Remove HOST_OUT_release

This is a forward port of a patch from the AOSP/master tree:
https://android.googlesource.com/platform/external/mesa3d/+/bd633f11de0c6ac1ed333a28344c74fd9898df9e%5E%21/

Which replaces HOST_OUT_release with HOST_OUT

As per Dan's explanation, the current code was incorrect to use
$(HOST_OUT_release) as $(HOST_OUT) will be set properly for
whether the current build that's being cleaned during
incrementals is using host debug or release builds.

Additionally Dan noted it was incredibly uncommon to use a debug
host build, as there was never a shortcut and one had to set an
environment variable manually. Thus it was rarely if ever tested.

Change-Id: I7972c0a50fa3520dcfa962d6dd7e602bfe22368d
Cc: Rob Herring <rob.herring@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
3 years agoAndroid.common.mk: define HAVE_TIMESPEC_GET
Sumit Semwal [Wed, 1 Aug 2018 23:20:37 +0000 (16:20 -0700)]
Android.common.mk: define HAVE_TIMESPEC_GET

This is a forward port of a patch from the AOSP/master tree:
https://android.googlesource.com/platform/external/mesa3d/+/bd30b663f55f8af73a0be4446349c5a2d4c641b0%5E%21/

Since https://android-review.googlesource.com/c/718518 added
timespec_get() to bionic, mesa3d doesn't build due to redefinition
of timespec_get().

Avoid redefinition by defining HAVE_TIMESPEC_GET flag.

Test: build and boot tested db820c to UI.

Change-Id: I3dcc8034b48785e45cd3fa50e4d9cf2c684694a0
Cc: Rob Herring <rob.herring@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
3 years agoutil: Android.mk: Convert implicit rules to static pattern rules
Dan Willemsen [Wed, 1 Aug 2018 23:20:36 +0000 (16:20 -0700)]
util: Android.mk: Convert implicit rules to static pattern rules

This is a partial cherry-pick from AOSP's mesa3d tree:
 https://android.googlesource.com/platform/external/mesa3d/+/a88dcf769eb00a4ffc7183a0396d881a28b5a29b%5E%21/

"We're deprecating make implicit rules, preferring static pattern
rules, or just regular rules."

Without this patch, the freedesktop/master branch won't build in
the AOSP environment, and this patch corrects that, as tested
on the Dragonboard 820c.

The i965 portion of the patch this is based on collided badly,
and I'm not sure how to best forward port it. However, so far
we don't see build issues without that portion.

Comments or feedback would be appreciated!

Change-Id: Id6dfd0d018cbd665fa19d80c14abd5f75fa10b8a
Cc: Rob Herring <rob.herring@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
3 years agoradeonsi: add new R600_DEBUG test "testclearbufperf"
Darren Powell [Wed, 13 Jun 2018 22:54:24 +0000 (18:54 -0400)]
radeonsi: add new R600_DEBUG test "testclearbufperf"

Signed-off-by: Darren Powell <darren.powell@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
3 years agomesa: add switch case for GL 2.0 in _mesa_compute_version()
Brian Paul [Thu, 2 Aug 2018 15:32:58 +0000 (09:32 -0600)]
mesa: add switch case for GL 2.0 in _mesa_compute_version()

Previously, I added a switch case for GL 2.1 (ed7a0770b881791dd697f3).
I don't know of any driver which only supports GL 2.0, but adding
this switch case avoids a failure if the app queries
GL_SHADING_LANGUAGE_VERSION.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agointel/tools: add error2aub creation into autotools
Andres Gomez [Thu, 2 Aug 2018 16:39:06 +0000 (19:39 +0300)]
intel/tools: add error2aub creation into autotools

Tarball distribution is done through "make distcheck". We include the
meson targets also into autotools so they won't fail when building
from the tarball.

Fixes: 6a60beba408 ("intel/tools: Add an error state to aub translator")
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Dylan Baker <dylan.c.baker@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agoanv/pipeline: Do cross-stage linking optimizations
Jason Ekstrand [Sat, 28 Oct 2017 00:07:52 +0000 (17:07 -0700)]
anv/pipeline: Do cross-stage linking optimizations

This appears to help the Aztec Ruins benchmark by about 2% on my Kaby
Lake gt2 laptop.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Pull most of the anv_pipeline_compile_* into common code
Jason Ekstrand [Fri, 27 Oct 2017 23:54:32 +0000 (16:54 -0700)]
anv/pipeline: Pull most of the anv_pipeline_compile_* into common code

This leaves us with a series of little anv_pipeline_compile_* functions
which each take a compiler object, a mem_ctx, the stage to compile, and
the previous stage for VUE linking purposes.  Some of them do
interesting things but most are little more than wrappers around
brw_compile_*.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Add a separate "link" stage
Jason Ekstrand [Fri, 27 Oct 2017 23:03:58 +0000 (16:03 -0700)]
anv/pipeline: Add a separate "link" stage

This breaks compilation up a bit into "link" and "compile".  In the
"link" stage, new anv_pipeline_link_* helpers are called which are
responsible for setting up the binding table and doing anything needed
to properly link with the next stage in the pipeline if one exists.
They are called in reverse order starting with the fragment shader so
you can assume linking in later stages is already done.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Compile to NIR in compile_graphics
Jason Ekstrand [Fri, 27 Oct 2017 22:47:11 +0000 (15:47 -0700)]
anv/pipeline: Compile to NIR in compile_graphics

This pulls the SPIR-V to NIR step out into common code.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Recompile all shaders if any are missing from the cache
Jason Ekstrand [Fri, 27 Oct 2017 22:05:02 +0000 (15:05 -0700)]
anv/pipeline: Recompile all shaders if any are missing from the cache

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Drop anv_pipeline_add_compiled_stage
Jason Ekstrand [Fri, 27 Oct 2017 21:47:38 +0000 (14:47 -0700)]
anv/pipeline: Drop anv_pipeline_add_compiled_stage

We can set active_stages much more directly and then it's just candy
around setting pipeline->stages[stage].

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Pull shader compilation out into a helper.
Jason Ekstrand [Fri, 27 Oct 2017 17:18:31 +0000 (10:18 -0700)]
anv/pipeline: Pull shader compilation out into a helper.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Call anv_pipeline_compile_* in a loop
Jason Ekstrand [Fri, 27 Oct 2017 17:13:38 +0000 (10:13 -0700)]
anv/pipeline: Call anv_pipeline_compile_* in a loop

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Hash the entire pipeline in one go
Jason Ekstrand [Fri, 27 Oct 2017 02:24:28 +0000 (19:24 -0700)]
anv/pipeline: Hash the entire pipeline in one go

Instead of hashing each stage separately (and TES and TCS together), we
hash the entire pipeline.  This means we'll get fewer cache hits if
they, for instance, re-use the same VS over and over again but it also
means we can now safely do cross-stage optimizations.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Populate keys up-front
Jason Ekstrand [Fri, 27 Oct 2017 01:59:33 +0000 (18:59 -0700)]
anv/pipeline: Populate keys up-front

Instead of having each anv_pipeline_compile_* function populate the
shader key, make it part of the anv_pipeline_stage struct and fill it
out up-front.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipline: Add a helper struct for per-stage info
Jason Ekstrand [Fri, 27 Oct 2017 01:42:35 +0000 (18:42 -0700)]
anv/pipline: Add a helper struct for per-stage info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agomeson: use correct keyword to fix a meson warning
Jon Turney [Thu, 2 Aug 2018 13:50:27 +0000 (14:50 +0100)]
meson: use correct keyword to fix a meson warning

With a sufficently recent meson, the following warning is produced:

WARNING: Passed invalid keyword argument "extra_args".
WARNING: This will become a hard error in the future.

It seems that compiler.links(args:) is meant here.

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-and-Tested-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agodocs: add 18.3.0-devel release notes template
Andres Gomez [Thu, 2 Aug 2018 15:15:33 +0000 (18:15 +0300)]
docs: add 18.3.0-devel release notes template

Signed-off-by: Andres Gomez <agomez@igalia.com>
3 years agomesa: bump version to 18.3.0-devel
Andres Gomez [Thu, 2 Aug 2018 15:00:01 +0000 (18:00 +0300)]
mesa: bump version to 18.3.0-devel

Signed-off-by: Andres Gomez <agomez@igalia.com>
3 years agoegl/main: fix indentation
Eric Engestrom [Thu, 2 Aug 2018 10:56:13 +0000 (11:56 +0100)]
egl/main: fix indentation

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
3 years agoloader: fix indentation
Eric Engestrom [Thu, 2 Aug 2018 10:49:40 +0000 (11:49 +0100)]
loader: fix indentation

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
3 years agoswr: Remove unnecessary memset call
Vlad Golovkin [Wed, 1 Aug 2018 17:56:23 +0000 (20:56 +0300)]
swr: Remove unnecessary memset call

Zeroing memory after calloc is not necessary. This also allows to avoid
possible crash when allocation fails, because memset is called before
checking screen for NULL.

Fixes: a29d63ecf71546c4798c6 "swr: refactor swr_create_screen to allow
                              for proper cleanup on error"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agomesa: replace binary constants with hexadecimal constants
Andres Gomez [Wed, 1 Aug 2018 14:16:24 +0000 (17:16 +0300)]
mesa: replace binary constants with hexadecimal constants

The binary constant notation "0b" is a GCC extension. Instead, we use
hexadecimal notation to fix the MSVC 2013 build:

Compiling src\mesa\main\texcompress_astc.cpp ...
texcompress_astc.cpp
src\mesa\main\texcompress_astc.cpp(111) : error C2059: syntax error : 'bad suffix on number'

...

src\mesa\main\texcompress_astc.cpp(1007) : fatal error C1003: error count exceeds 100; stopping compilation
scons: *** [build\windows-x86-debug\mesa\main\texcompress_astc.obj] Error 2
scons: building terminated because of errors.

v2: Fix wrong conversion (Ilia).

Fixes: 38ab39f6501 ("mesa: add ASTC 2D LDR decoder")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Roland Scheidegger <sroland@vmware.com>
Cc: Mike Lothian <mike@fireburn.co.uk>
Cc: Gert Wollny <gert.wollny@collabora.com>
Cc: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoddebug: use util_snprintf() in dd_get_debug_filename_and_mkdir
Andres Gomez [Wed, 1 Aug 2018 13:26:48 +0000 (16:26 +0300)]
ddebug: use util_snprintf() in dd_get_debug_filename_and_mkdir

Instead of plain snprintf(). To fix the MSVC 2013 build:

  Compiling src\gallium\auxiliary\driver_ddebug\dd_draw.c ...
dd_draw.c
c:\projects\mesa\src\gallium\auxiliary\driver_ddebug\dd_util.h(60) : warning C4013: 'snprintf' undefined; assuming extern returning int

...

gallium.lib(dd_draw.obj) : error LNK2001: unresolved external symbol _snprintf
build\windows-x86-debug\gallium\targets\graw-gdi\graw.dll : fatal error LNK1120: 1 unresolved externals
scons: *** [build\windows-x86-debug\gallium\targets\graw-gdi\graw.dll] Error 1120
scons: building terminated because of errors.

Fixes: 6ff0c6f4ebc ("gallium: move ddebug, noop, rbug, trace to auxiliary to improve build times")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Roland Scheidegger <sroland@vmware.com>
Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agokutil/queue: use util_snprintf() in util_queue_init
Andres Gomez [Wed, 1 Aug 2018 12:55:51 +0000 (15:55 +0300)]
kutil/queue: use util_snprintf() in util_queue_init

Instead of plain snprintf(). To fix the MSVC 2013 build:

  Compiling src\util\u_queue.c ...
u_queue.c
src\util\u_queue.c(325) : warning C4013: 'snprintf' undefined; assuming extern returning int

...

mesautil.lib(u_queue.obj) : error LNK2001: unresolved external symbol _snprintf
scons: building terminated because of errors.

Fixes: b238e33bc9d ("kutil/queue: add a process name into a thread name")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Roland Scheidegger <sroland@vmware.com>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agogallium/aux/util: use util_snprintf() in test_texture_barrier
Andres Gomez [Wed, 1 Aug 2018 12:47:13 +0000 (15:47 +0300)]
gallium/aux/util: use util_snprintf() in test_texture_barrier

Instead of plain snprintf(). To fix the MSVC 2013 build:

  Compiling src\gallium\auxiliary\util\u_tests.c ...
u_tests.c
src\gallium\auxiliary\util\u_tests.c(624) : warning C4013: 'snprintf' undefined; assuming extern returning int

...

gallium.lib(u_tests.obj) : error LNK2019: unresolved external symbol _snprintf referenced in function _test_texture_barrier
build\windows-x86-debug\gallium\targets\graw-gdi\graw.dll : fatal error LNK1120: 1 unresolved externals
scons: *** [build\windows-x86-debug\gallium\targets\graw-gdi\graw.dll] Error 1120
scons: building terminated because of errors.

Fixes: 56342c97ee7 ("gallium/u_tests: test FBFETCH and shader-based blending with MSAA")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Roland Scheidegger <sroland@vmware.com>
Cc: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agoglsl: use util_snprintf()
Andres Gomez [Wed, 1 Aug 2018 10:22:00 +0000 (13:22 +0300)]
glsl: use util_snprintf()

Instead of plain snprintf(). To fix the MSVC 2013 build.

Fixes: 6ff0c6f4ebc ("gallium: move ddebug, noop, rbug, trace to auxiliary to improve build times")
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agointel/compiler: Add brw_get_compiler_config_value for disk cache
Jordan Justen [Wed, 25 Jul 2018 21:31:05 +0000 (14:31 -0700)]
intel/compiler: Add brw_get_compiler_config_value for disk cache

During code review, Jason pointed out that:

2b3064c0731 "i965, anv: Use INTEL_DEBUG for disk_cache driver flags"

Didn't account for INTEL_SCALER_* environment variables.

To fix this, let the compiler return the disk_cache driver flags.

Another possible fix would be to pull the INTEL_SCALER_* into
INTEL_DEBUG bits, but as we are currently using 41 of 64 bits, I
didn't think it was a good use of 4 more of these bits. (5 since
INTEL_PRECISE_TRIG needs to be accounted for as well.)

Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoi965: Disable shader cache with INTEL_DEBUG=shader_time
Jordan Justen [Wed, 25 Jul 2018 00:13:52 +0000 (17:13 -0700)]
i965: Disable shader cache with INTEL_DEBUG=shader_time

Shader time hard codes an index of the shader time buffer within the
gen program.

In order to support shader time in the disk shader cache, we'd need to
add the shader time index into the program key. This should work, but
probably is not worth it for this particular debug feature.

Therefore, let's just disable the disk shader cache if the shader time
debug feature is used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106382
Fixes: 96fe36f7acc "i965: Enable disk shader cache by default"
Cc: Eero Tamminen <eero.t.tamminen@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoglsl: make a copy of array indices that are used to deref a function out param
Timothy Arceri [Sat, 21 Jul 2018 05:22:24 +0000 (15:22 +1000)]
glsl: make a copy of array indices that are used to deref a function out param

Fixes new piglit test:
tests/spec/glsl-1.20/execution/qualifiers/vs-out-conversion-int-to-float-vec4-index.shader_test

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoanv/pipeline: Add populate_tcs/tes_key helpers
Jason Ekstrand [Fri, 27 Oct 2017 01:11:25 +0000 (18:11 -0700)]
anv/pipeline: Add populate_tcs/tes_key helpers

They don't really do anything interesting, but it's more consistent this
way.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Rework the parameters to populate_wm_prog_key
Jason Ekstrand [Fri, 27 Oct 2017 00:56:07 +0000 (17:56 -0700)]
anv/pipeline: Rework the parameters to populate_wm_prog_key

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: More aggressively optimize away color attachments
Jason Ekstrand [Wed, 11 Jul 2018 06:31:47 +0000 (23:31 -0700)]
anv/pipeline: More aggressively optimize away color attachments

Instead of just looking at the number of color attachments, look at
which ones are actually used by the subpass.  This lets us potentially
throw away chunks of the fragment shader.  In DXVK, for example, all
subpasses have 8 attachments and most are VK_ATTACHMENT_UNUSED so this
is very helpful in that case.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv: Restrict the number of color regions to those actually written
Jason Ekstrand [Thu, 28 Jun 2018 01:30:09 +0000 (18:30 -0700)]
anv: Restrict the number of color regions to those actually written

The back-end compiler emits the number of color writes specified by
wm_prog_key::nr_color_regions regardless of what nir_store_outputs we
have.  Once we've gone through and figured out which render targets
actually exist and are written by the shader, we should restrict the key
to avoid extra RT write messages.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoanv/pipeline: Fix up deref modes if we delete a FS output
Jason Ekstrand [Thu, 28 Jun 2018 01:25:17 +0000 (18:25 -0700)]
anv/pipeline: Fix up deref modes if we delete a FS output

With the new deref instructions, we have to keep the modes consistent
between the derefs and the variables they reference.  Since we remove
outputs by changing them to local variables, we need to run the fixup
pass to fix the modes.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agonir/lower_indirect: Bail early if modes == 0
Jason Ekstrand [Sat, 28 Oct 2017 16:05:01 +0000 (09:05 -0700)]
nir/lower_indirect: Bail early if modes == 0

There's no point in walking the program if we're never going to actually
lower anything.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agointel/nir: Call nir_lower_io_to_scalar_early
Jason Ekstrand [Tue, 31 Jul 2018 13:16:34 +0000 (06:16 -0700)]
intel/nir: Call nir_lower_io_to_scalar_early

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166953 -> 15073611 (-0.62%)
    instructions in affected programs: 2390284 -> 2296942 (-3.91%)
    helped: 16469
    HURT: 505

    total loops in shared programs: 4954 -> 4951 (-0.06%)
    loops in affected programs: 3 -> 0
    helped: 3
    HURT: 0

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agointel/nir: Split IO arrays into elements
Jason Ekstrand [Thu, 26 Jul 2018 05:52:39 +0000 (22:52 -0700)]
intel/nir: Split IO arrays into elements

The NIR nir_lower_io_arrays_to_elements pass attempts to split I/O
variables which are arrays or matrices into a sequence of separate
variables.  This can help link-time optimization by allowing us to
remove varyings at a more granular level.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15177645 -> 15168494 (-0.06%)
    instructions in affected programs: 79857 -> 70706 (-11.46%)
    helped: 392
    HURT: 0

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoi965/fs: Flag all slots of a flat input as flat
Jason Ekstrand [Tue, 31 Jul 2018 12:31:47 +0000 (05:31 -0700)]
i965/fs: Flag all slots of a flat input as flat

Otherwise, only the first vec4 of a matrix or other complex type will
get marked as flat and we'll interpolate the others.  This was caught by
a dEQP test which started failing because it did a SSO vs. non-SSO
comparison.  Previously, we did the interpolation wrong consistently in
both versions.  However, with one of Tim Arceri's NIR linkingpatches, we
started splitting the matrix input into vectors at link time in the
non-SSO version and it started getting correctly interpolated which
didn't match the broken SSO version.  As of this commit, they both get
correctly interpolated.

Fixes: e61cc87c757f8bc "i965/fs: Add a flat_inputs field to prog_data"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agointel/nir: Use the correct scalar stage for consumers when linking
Jason Ekstrand [Tue, 31 Jul 2018 18:31:22 +0000 (11:31 -0700)]
intel/nir: Use the correct scalar stage for consumers when linking

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agodocs: update 18.2.0 release notes for virgl
Dave Airlie [Wed, 1 Aug 2018 22:43:56 +0000 (08:43 +1000)]
docs: update 18.2.0 release notes for virgl

3 years agonir/meson: fix c vs cpp args for nir test
Dylan Baker [Tue, 22 May 2018 22:34:38 +0000 (15:34 -0700)]
nir/meson: fix c vs cpp args for nir test

Fixes: d1992255bb29054fa51763376d125183a9f602f3
       ("meson: Add build Intel "anv" vulkan driver")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agogallium: fix ddebug on windows
Dylan Baker [Wed, 18 Apr 2018 17:21:14 +0000 (10:21 -0700)]
gallium: fix ddebug on windows

By including the proper headers for getpid and for mkdir.

Fixes: 6ff0c6f4ebcb87ea6c6fe5a4ba90b548f666067d
       ("gallium: move ddebug, noop, rbug, trace to auxiliary to improve build times")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoutil: move process.[ch] to u_process.[ch]
Dylan Baker [Tue, 10 Jul 2018 22:00:13 +0000 (15:00 -0700)]
util: move process.[ch] to u_process.[ch]

On windows process.h is a system provided header, and it's required in
include/c11/threads_win32.h. This header interferes with searching for
that header, and results in windows build warnings with scons, but
errors in meson which doesn't allow implicit function declarations. Just
rename process to u_process, which follows the style of utils anyway.

Fixes: 2e1e6511f76370870b5cde10caa9ca3b6d0dc65f
       ("util: extract get_process_name from xmlconfig.c")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoac,radeonsi: reduce optimizations for complex compute shaders on older APUs (v2)
Marek Olšák [Fri, 20 Jul 2018 02:55:49 +0000 (22:55 -0400)]
ac,radeonsi: reduce optimizations for complex compute shaders on older APUs (v2)

To make dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23
finish sooner on the older CPUs. (otherwise it gets killed and we fail
the test)

Acked-by: Dave Airlie <airlied@gmail.com>
3 years agov3d: Actually put the "%s" in the snprintf.
Eric Anholt [Wed, 1 Aug 2018 18:25:58 +0000 (11:25 -0700)]
v3d: Actually put the "%s" in the snprintf.

I missed an important part when porting the change over, fixing my
compiler warning but breaking -Werror=format-security.

Fixes: e6ff5ac4468e ("v3d: use snprintf(..., "%s", ...) instead of strncpy")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107443

3 years agovc4: Fix automake linking error.
Juan A. Suarez Romero [Tue, 31 Jul 2018 12:17:23 +0000 (14:17 +0200)]
vc4: Fix automake linking error.

  CXXLD    gallium_dri.la
../../../../src/gallium/drivers/vc4/.libs/libvc4.a(vc4_cl_dump.o): In function `vc4_dump_cl':
src/gallium/drivers/vc4/vc4_cl_dump.c:45: undefined reference to `clif_dump_init'
src/gallium/drivers/vc4/vc4_cl_dump.c:82: undefined reference to `clif_dump_destroy'
../../../../src/broadcom/cle/.libs/libbroadcom_cle.a(cle_libbroadcom_cle_la-v3d_decoder.o): In function `v3d_field_iterator_next':
src/broadcom/cle/v3d_decoder.c:902: undefined reference to `clif_lookup_bo'

Fixes: e92959c4e0 ("v3d: Pass the whole clif_dump structure to v3d_print_group().")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107423
CC: Eric Anholt <eric@anholt.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Andres Gomez <agomez@igalia.com>
3 years agoscons: require scons 2.4 or greater
Juan A. Suarez Romero [Wed, 1 Aug 2018 15:48:11 +0000 (17:48 +0200)]
scons: require scons 2.4 or greater

There is a bug with scons 2.3, used in Travis, where it fails to detect
some C functions.

Reviewed-by: Andres Gomez <agomez@igalia.com>