mesa.git
6 years agoloader: use HAVE_LIBDRM instead of ! __NOT_HAVE_DRM_H
Emil Velikov [Tue, 7 Jul 2015 14:42:15 +0000 (15:42 +0100)]
loader: use HAVE_LIBDRM instead of ! __NOT_HAVE_DRM_H

Double negatives in English language are normally avoided, plus the
former seems cleaner and more consistent.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agost/dri: unwrap/remove __NOT_HAVE_DRM_H magic
Emil Velikov [Wed, 22 Jul 2015 15:34:15 +0000 (16:34 +0100)]
st/dri: unwrap/remove __NOT_HAVE_DRM_H magic

With the dri_interface.h clean of the macro, we can remove the final
only st/dri specific use of the very same.

Seemingly it was incorrectly used, as the build-time presence of dri2 is
not libdrm specific. At run-time, the code is already limited to dri2
use-cases plus returning true, when the extension is not present (or too
old) will likely lead to a crash as one tries to use it shortly after
the dri_with_format() call.

As a side effect this gives us a nice cleanup the builds.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
6 years agodri_interface: drop __NOT_HAVE_DRM_H magic
Emil Velikov [Tue, 7 Jul 2015 14:13:46 +0000 (15:13 +0100)]
dri_interface: drop __NOT_HAVE_DRM_H magic

v2: use HAVE_LIBDRM macro.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agodri/swrast: automake: add LIBDRM_CFLAGS
Emil Velikov [Wed, 22 Jul 2015 15:22:44 +0000 (16:22 +0100)]
dri/swrast: automake: add LIBDRM_CFLAGS

With the follow up commit we'll remove the __NOT_HAVE_DRM_H macro. As
requested by Ian HAVE_LIBDRM will be used instead, which will lead to
swrast including drm.h when libdrm package is available, even though we
don't need/make use of the header.

As the define is added after the AM_CFLAGS we cannnot use -UHAVE_LIBDRM,
but instead let's just add LIBDRM_CFLAGS. The latter of which will
expand to NULL when the libdrm package is not around.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
6 years agoconfigure.ac: do not set HAVE_DRI(23) when libdrm is missing
Emil Velikov [Thu, 9 Jul 2015 20:19:15 +0000 (21:19 +0100)]
configure.ac: do not set HAVE_DRI(23) when libdrm is missing

These conditionals are used to guard both dri modules and loader(s).

Currently if we try to build the gallium swrast dri module (without glx)
on a system that's missing libdrm the build will fail.

v2: Make sure we assign prior to checking the have_libdrm variable.

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
6 years agomesa: fix typo s/glGetTextImage/glGetTexImage/
Brian Paul [Wed, 22 Jul 2015 14:04:49 +0000 (08:04 -0600)]
mesa: fix typo s/glGetTextImage/glGetTexImage/

Trivial.

6 years agoradeonsi: Flush when we're asked to return a fence but don't have one yet
Michel Dänzer [Wed, 22 Jul 2015 07:11:39 +0000 (16:11 +0900)]
radeonsi: Flush when we're asked to return a fence but don't have one yet

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: fix misleading comment
Timothy Arceri [Fri, 3 Jul 2015 22:34:32 +0000 (08:34 +1000)]
mesa: fix misleading comment

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
6 years agomesa: fix active sampler conflict validation
Timothy Arceri [Wed, 17 Jun 2015 13:03:52 +0000 (23:03 +1000)]
mesa: fix active sampler conflict validation

The type stored in gl_uniform_storage is the type of a single array
element not the array type so size was always 1.

V2: Dont validate sampler units pointing to 0

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
6 years agoglsl: check for leading zeros in array index validation
Timothy Arceri [Thu, 2 Jul 2015 22:45:30 +0000 (08:45 +1000)]
glsl: check for leading zeros in array index validation

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
6 years agoswrast: remove unneeded & operators in _swrast_choose_texture_sample_func()
Brian Paul [Wed, 22 Jul 2015 00:44:07 +0000 (18:44 -0600)]
swrast: remove unneeded & operators in _swrast_choose_texture_sample_func()

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
6 years agomesa: move check for no-op glShadeModel call earlier
Brian Paul [Wed, 22 Jul 2015 00:44:07 +0000 (18:44 -0600)]
mesa: move check for no-op glShadeModel call earlier

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agomesa: move check for no-op glAlphaFunc call earlier
Brian Paul [Wed, 22 Jul 2015 00:44:07 +0000 (18:44 -0600)]
mesa: move check for no-op glAlphaFunc call earlier

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agomesa: move check for no-op glFrontFace call earlier
Brian Paul [Wed, 22 Jul 2015 00:44:07 +0000 (18:44 -0600)]
mesa: move check for no-op glFrontFace call earlier

If the new mode matches the current mode, there can be no error.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agomesa: s/GLint/GLsizei/ for consistency
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: s/GLint/GLsizei/ for consistency

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agodocs: document that GL_ARB_get_texture_sub_image is completed
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
docs: document that GL_ARB_get_texture_sub_image is completed

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: enable GL_ARB_get_texture_sub_image for all drivers
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: enable GL_ARB_get_texture_sub_image for all drivers

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: add API dispatch for GL_ARB_get_texture_sub_image
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: add API dispatch for GL_ARB_get_texture_sub_image

This adds the new glGetTextureSubImage() and
glGetCompressedTextureSubImage() functions.  Also update the
dispatch sanity test program.

v2: remove stray brace, move xi:include line in gl_API.xml, fix extension
number typo, s/program/texture/ in xml file.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: add new _mesa_Get[Compressed]TextureSubImage() functions
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: add new _mesa_Get[Compressed]TextureSubImage() functions

Simple implementations in terms of get_[compressed_]texture_image().

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: overhaul the glGetCompressedTexImage code
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: overhaul the glGetCompressedTexImage code

Same idea as the previous patch.
v2: a few clean-ups spotted by Ilia

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: overhaul the glGetTexImage code
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: overhaul the glGetTexImage code

1. Reorganize the error checking code.
2. Lay groundwork for getting sub images by passing image offset and
   dimensions to the error checking code.
3. Implement _mesa_GetnTexImageARB(), _mesa_GetTexImage() and
   _mesa_GetTextureImage() all in terms of get_texture_image().

v2: pass offset/width/height/depth arguments to the error checking
function, avoid using magic width/height/depth values.
v3: remove unused bufSize param to get_texture_image()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: 80-column wrapping in texgetimage.c
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: 80-column wrapping in texgetimage.c

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: replace Driver.GetCompressedTexImage() w/ GetCompressedTexSubImage()
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: replace Driver.GetCompressedTexImage() w/ GetCompressedTexSubImage()

For now, pass offsets of zero and width/height/depth equal to the
whole image.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: make _mesa_get_[compressed_]texture_image() static
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: make _mesa_get_[compressed_]texture_image() static

These functions are only called from teximage.c

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: plumb offset/size parameters through GetTexSubImage code
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: plumb offset/size parameters through GetTexSubImage code

Needed for GL_ARB_get_texture_sub_image.  But at this point, the
offsets are always zero and the sizes match the whole texture image.

v2: Fixes, suggestions from Laura Ekstrand:
* Fix calls to ctx->Driver.UnmapTextureImage() to pass the correct
  slice value.
* Added comments and assertions to check zoffset+depth<=tex->Depth before
  the 'img' loops.
* Added a new zoffset==0 assert in get_tex_memcpy().

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agomesa: replace Driver.GetTexImage with GetTexSubImage()
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: replace Driver.GetTexImage with GetTexSubImage()

The new driver hook has x/y/zoffset and width/height/depth parameters
for the new glGetTextureSubImage() function.

The meta code and gallium state tracker are updated to handle the
new parameters.

Callers to Driver.GetTexSubImage() pass in offsets=0 and sizes equal
to the whole texture size.

v2: update i965 driver code, s/GLint/GLsizei/ in GetTexSubImage hook

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agometa: add offset, width, height parameters to decompress_texture_image()
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
meta: add offset, width, height parameters to decompress_texture_image()

In preparation for decompressing texture sub images.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agometa: handle subimages in _mesa_meta_setup_texture_coords()
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
meta: handle subimages in _mesa_meta_setup_texture_coords()

v2: fix depth, total_depth mix-up in meta.h, per Laura Ekstrand.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
6 years agomesa: assorted whitespace, formatting fixes in teximage.c
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: assorted whitespace, formatting fixes in teximage.c

Trivial.

6 years agomesa: allow GL_TEXTURE_CUBE_MAP_ARRAY case for glCompressedTexSubImage3D()
Brian Paul [Wed, 22 Jul 2015 00:35:38 +0000 (18:35 -0600)]
mesa: allow GL_TEXTURE_CUBE_MAP_ARRAY case for glCompressedTexSubImage3D()

Since s3tc works for cube maps and 2D arrays, it should also work for
cube arrays.  NVIDIA's driver supports this too.  Seems like the spec
should say this.

This is a minor follow-on fix for the commit "mesa: fix up some texture
error checks".

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agomesa: include stdarg.h for va_list
Jonathan Gray [Wed, 15 Jul 2015 15:17:37 +0000 (01:17 +1000)]
mesa: include stdarg.h for va_list

Include stdarg.h for va_list.  Unbreaks the build on OpenBSD:

In file included from mesa/program/dummy_errors.c:24:
../src/mesa/main/errors.h:85: error: expected declaration specifiers or '...' before 'va_list'

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agogallium: replace INLINE with inline
Ilia Mirkin [Mon, 20 Jul 2015 23:58:43 +0000 (19:58 -0400)]
gallium: replace INLINE with inline

Generated by running:
git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g'
git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g'
git checkout src/gallium/state_trackers/clover/Doxyfile

and manual edits to
src/gallium/include/pipe/p_compiler.h
src/gallium/README.portability

to remove mentions of the inline define.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
6 years agonvc0: force cache flush when binding a new ubo
Samuel Pitoiset [Tue, 21 Jul 2015 19:58:08 +0000 (21:58 +0200)]
nvc0: force cache flush when binding a new ubo

This fixes the following piglit test:
  ext_transform_feedback-immediate-reuse-uniform-buffer

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agonv50: force cache flush when binding a new ubo
Samuel Pitoiset [Tue, 21 Jul 2015 19:35:43 +0000 (21:35 +0200)]
nv50: force cache flush when binding a new ubo

This fixes the following piglit test:
  ext_transform_feedback-immediate-reuse-uniform-buffer

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agost/mesa: Silence GCC unused-variable warning.
Vinson Lee [Tue, 21 Jul 2015 04:52:40 +0000 (21:52 -0700)]
st/mesa: Silence GCC unused-variable warning.

Silence a release build warning.

st_glsl_to_tgsi.cpp: In function 'pipe_error st_translate_program(gl_context*, uint, ureg_program*, glsl_to_tgsi_visitor*, const gl_program*, GLuint, const GLuint*, const GLuint*, const ubyte*, const ubyte*, const GLuint*, const GLuint*, GLuint, const GLuint*, const GLuint*, const ubyte*, const ubyte*, boolean, boolean)':
st_glsl_to_tgsi.cpp:5461:36: warning: unused variable 'pscreen' [-Wunused-variable]
                struct pipe_screen *pscreen = st->pipe->screen;
                                    ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
6 years agor600/sb: Fix an &/&& mistake
Adam Jackson [Tue, 21 Jul 2015 16:08:20 +0000 (12:08 -0400)]
r600/sb: Fix an &/&& mistake

gcc says:

    sb/sb_sched.cpp: In member function 'bool r600_sb::alu_group_tracker::try_reserve(r600_sb::alu_node*)':
    sb/sb_sched.cpp:492:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses]
      if (!trans & fbs)

It happens to be harmless; if fbs is ever non-zero, it will be VEC_210,
which is 5, so (!trans & 5) == 1 and the branch works as expected.  But
logical AND is clearly what was meant.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
6 years agoRevert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"
Anuj Phogat [Fri, 17 Jul 2015 21:14:29 +0000 (14:14 -0700)]
Revert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"

Commit c9dbdc0 introduced some dead code which is supposed to be used
once we have Yf/Ys tiling working and performing better. Ken reported
the issue that static analysis tool now shows warnings due to the dead
code. To fix these warnings, this patch reverts the changes made in
commit c9dbdc0.

It'll be better to add the Yf/Ys tiling selection code later, when we
are ready to use it.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Fix stride field for the result of emit_uniformize().
Francisco Jerez [Mon, 13 Jul 2015 12:52:28 +0000 (15:52 +0300)]
i965: Fix stride field for the result of emit_uniformize().

This is essentially the same problem fixed in an earlier patch for
immediates.  Setting the stride to zero will be particularly useful
for my future SIMD lowering pass, because we will be able to just
check whether the stride of a source register is zero and skip
emitting the copies required to unzip it in that case.

Instead of setting stride to zero in every caller of emit_uniformize()
I've changed the function to return the result as its return value
(previously it was being written into a caller-provided destination
register), because this way we can enforce that the result is used with
the correct regioning from the function itself.

The changes to the prototype of its VEC4 counterpart are mainly for
the sake of symmetry, VEC4 registers don't have stride.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
6 years agoi965/fs: Fix stride field for uniforms.
Francisco Jerez [Mon, 13 Jul 2015 12:29:39 +0000 (15:29 +0300)]
i965/fs: Fix stride field for uniforms.

This fixes essentially the same problem as for immediates.  Registers
of the UNIFORM file are typically accessed according to the formula:

 read_uniform(r, channel_index, array_index) =
    read_element(r, channel_index * 0 + array_index * 1)

Which matches the general direct addressing formula for stride=0:

 read_direct(r, channel_index, array_index) =
    read_element(r, channel_index * stride +
                    array_index * max{1, stride * width})

In either case if reladdr is present the access will be according to
the composition of two register regions, the first one determining the
per-channel array_index used for the second, like:

 read_indirect(r, channel_index, array_index) =
    read_direct(r, channel_index,
                read(r.reladdr, channel_index, array_index))

where:
 read(r, channel_index, array_index) = if r.reladdr == NULL
    then read_direct(r, channel_index, array_index)
    else read_indirect(r, channel_index, array_index)

In conclusion we can handle uniforms consistently with the other
register files if we set stride to zero.  After lowering to a GRF
using VARYING_PULL_CONSTANT_LOAD in demote_pull_constant_loads() the
stride of the source is set to one again because the result of
VARYING_PULL_CONSTANT_LOAD is generally non-uniform.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
6 years agoi965/fs: Fix stride for immediate registers.
Francisco Jerez [Mon, 13 Jul 2015 11:50:24 +0000 (14:50 +0300)]
i965/fs: Fix stride for immediate registers.

When the width field was removed from fs_reg the BROADCAST handling
code in opt_algebraic() started to miss a number of trivial
optimization cases resulting in the ugly indirect-addressing sequence
to be emitted unnecessarily for some variable-indexed texturing and
UBO loads regardless of one of the sources of BROADCAST being
immediate.  Apparently the reason was that we were setting the stride
field to one for immediates even though they are typically uniform.
Width used to be set to one too which is why this optimization used to
work previously until the "reg.width == 1" check was removed.

The stride field of vector immediates is intentionally left equal to
one, because they are strictly speaking not uniform.  The assertion in
fs_generator makes sure that immediates have the expected stride as
consistency check.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
6 years agoi965/vec4: Fix liveness analysis with BRW_OPCODE_SEL
Iago Toral Quiroga [Mon, 20 Jul 2015 10:58:12 +0000 (12:58 +0200)]
i965/vec4: Fix liveness analysis with BRW_OPCODE_SEL

We only consider a vgrf defined by a given block if the block writes to it
unconditionally. So far we have been checking this by testing that the
instruction is not predicated, however, in the case of BRW_OPCODE_SEL,
the predication is used to select the value to write, not to decide if
the write is actually done. The consequence of this was increased life
spans for affected vgrfs, which could lead to additional register pressure.

Since NIR generates selects for conditional writes this was causing massive
register pressure in a handful of piglit and dEQP tests that had a large
number of select operations with the NIR-vec4 backend.

Fixes the following piglit tests with the NIR-vec4 backend:
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec4-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec4-index-rd
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec2-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec3-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/vs-output-array-float-index-wr-before-gs

Fixes 80 dEQP tests with the NIR-vec4 backend in the following category:
dEQP-GLES3.functional.ubo.*

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().
Kenneth Graunke [Sat, 18 Jul 2015 08:22:00 +0000 (01:22 -0700)]
mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().

Generated by sed; no manual changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
6 years agonouveau: use bool instead of boolean
Samuel Pitoiset [Mon, 20 Jul 2015 19:32:43 +0000 (21:32 +0200)]
nouveau: use bool instead of boolean

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agogallivm: Initialize LLVM Modules's DataLayout to an empty string.
Tom Stellard [Mon, 20 Jul 2015 15:12:56 +0000 (15:12 +0000)]
gallivm: Initialize LLVM Modules's DataLayout to an empty string.

This fixes crashes in llvmpipe with LLVM 3.8 and also some piglit tests
on radeonsi that use the draw module.

This is just a temporary solution.  The correct solution will require
creating a TargetMachine during gallivm initialization and pulling the
DataLayout from there.  This will be a somewhat invasive change, and it
will need to be validatated on multiple LLVM versions.

https://llvm.org/bugs/show_bug.cgi?id=24172

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agonvc0: add a missing parameter to nvc0_set_shader_images()
Samuel Pitoiset [Thu, 16 Jul 2015 21:05:05 +0000 (23:05 +0200)]
nvc0: add a missing parameter to nvc0_set_shader_images()

This fixes a compilation warning introduced in commit 05a12c5
(gallium: add interface for writable shader images).

While we are at it, fix indentation and rename parameters according to
the gallium interface.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agonouveau: always align buffers to 0x100
Samuel Pitoiset [Mon, 20 Jul 2015 16:47:17 +0000 (18:47 +0200)]
nouveau: always align buffers to 0x100

Only constbufs must be aligned to 0x100, but since all buffers can be
rebinded as constant buffers they must be also aligned.

This patch prevents this behaviour by aligning everything to 256-byte
increments at buffer creation.

This fixes dmesg fails for the following piglit test:
  ext_transform_feedback-immediate-reuse-uniform-buffer -auto -fbo

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agonv50: limit the maximum number of samplers to 16
Samuel Pitoiset [Mon, 13 Jul 2015 11:34:31 +0000 (13:34 +0200)]
nv50: limit the maximum number of samplers to 16

NV50_3D_BIND_TSC only allows to bind 16 samplers, and since we don't
want to do anything with NV50_3D_BIND_TSC2, just limit the maximum
number of samplers to 16 like for nvc0.

This fixes dmesg fails with the following piglit test:
 max-samplers

But the test still fails.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agonv50: turn samples counts off during blit
Samuel Pitoiset [Mon, 13 Jul 2015 10:52:57 +0000 (12:52 +0200)]
nv50: turn samples counts off during blit

Fixes the following piglit test:
  occlusion_query_meta_no_fragments

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agonv50: add nesting support for occlusion queries
Samuel Pitoiset [Mon, 13 Jul 2015 10:51:21 +0000 (12:51 +0200)]
nv50: add nesting support for occlusion queries

This is loosely based on nvc0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agoi965/nir/fs: removed unneeded support for global variables
Alejandro Piñeiro [Fri, 17 Jul 2015 09:54:34 +0000 (11:54 +0200)]
i965/nir/fs: removed unneeded support for global variables

As functions are inlined, and nir_lower_global_vars_to_local gets
run, all global variables are lowered to local variables.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agonv50: fix max level clamping on G80
Ilia Mirkin [Mon, 20 Jul 2015 04:19:56 +0000 (00:19 -0400)]
nv50: fix max level clamping on G80

It appears that the G80 did not have support for the sampler view
first/last clamping. Put the view's last level in the place of the
texture's so that it doesn't go past what the sampler view allows.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
6 years agogm107/ir: fix indirect txq emission
Ilia Mirkin [Sat, 18 Jul 2015 23:02:29 +0000 (19:02 -0400)]
gm107/ir: fix indirect txq emission

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
6 years agonvc0/ir: don't worry about sampler in txq handling
Ilia Mirkin [Sat, 18 Jul 2015 22:38:42 +0000 (18:38 -0400)]
nvc0/ir: don't worry about sampler in txq handling

There's no need to deal with samplers for texture size queries. That
code also was accidentally setting an invalid sIndirectSrc position, but
it can now just be removed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
6 years agonvc0/ir: fix txq on indirect samplers
Ilia Mirkin [Sat, 18 Jul 2015 20:43:17 +0000 (16:43 -0400)]
nvc0/ir: fix txq on indirect samplers

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
6 years agoi965: Disable resource streamer in BLORP
Abdiel Janulgue [Wed, 20 May 2015 15:02:44 +0000 (18:02 +0300)]
i965: Disable resource streamer in BLORP

Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.

Cc: kenneth@whitecape.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
6 years agoi965: Upload binding tables in hw-generated binding table format.
Abdiel Janulgue [Wed, 2 Oct 2013 13:37:20 +0000 (16:37 +0300)]
i965: Upload binding tables in hw-generated binding table format.

When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.

Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.

Note that the the binding table pointer offset is relative to the binding table
pool base address when resource streamer instead of the surface state base address.

v2: Fix possible buffer overflow when allocating a chunk out of the
    hw-binding table pool (Ken).
v3: Remove extra newline and add missing brace around if-statement (Matt).
v4: Fix broken INTEL_DEBUG=shader_time for hw-generated binding tables.
    Document PRM WaStateBindingTableOverfetch workaround.

Cc: kenneth@whitecape.org
Cc: mattst88@gmail.com
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
6 years agoi965: Implement interface to edit binding table entries
Abdiel Janulgue [Fri, 17 Jul 2015 09:20:18 +0000 (12:20 +0300)]
i965: Implement interface to edit binding table entries

Unlike normal software binding tables where the driver has to manually
generate and fill a binding table array which are then uploaded to the
hardware, the resource streamer instead presents the driver with an option
to fill out slots for individual binding table indices. The hardware
accumulates the state for these combined edits which it then automatically
flushes to a binding table pool when the binding table pointer state
command is invoked.

v2: Clarify binding table edit bit aligment (Topi).
v3: Make comments and function names more clearer (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
6 years agoi965: Enable hardware-generated binding tables on render path.
Abdiel Janulgue [Wed, 15 Apr 2015 10:04:45 +0000 (13:04 +0300)]
i965: Enable hardware-generated binding tables on render path.

This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.

Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.

v2: - Use MOCS in binding table pool alloc for GEN8
    - Fix spurious offset when allocating binding table pool entry
      and start from zero instead.
v3: - Include GEN8 fix for spurious offset above.
v4: - Fixup wrong packet length in enable/disable hw-binding table
      for GEN8 (Ville).
    - Don't invoke HW-binding table disable command when we dont
      have resource streamer (Chris).
v5: - Reorder the state cache invalidate flush so it happens in-between
      enabling hw-generated binding tables and the previous sw-binding
      table GPU state (Chris).
v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables().
    - Adhere to coding guidelines and make comments more informative.

Cc: kenneth@whitecape.org
Cc: syrjala@sci.fi
Cc: chris@chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
6 years agoi965: Enable resource streamer for the batchbuffer
Abdiel Janulgue [Tue, 2 Jul 2013 15:48:22 +0000 (11:48 -0400)]
i965: Enable resource streamer for the batchbuffer

Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER
execbuffer flags.

v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel
      supports RS (Ken).
    - Add brw_device_info::has_resource_streamer and toggle it for
      Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken).
v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel.
v4: - Always inspect the getparam.value (Chris Wilson).
v5: - Fold redundant devinfo->has_resource_streamer check in context create
      into init screen.

Cc: kenneth@whitecape.org
Cc: chris@chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
6 years agoi965: Define HW-binding table and resource streamer control opcodes
Abdiel Janulgue [Mon, 18 May 2015 11:32:17 +0000 (14:32 +0300)]
i965: Define HW-binding table and resource streamer control opcodes

v2: Use macros for HW binding table edits (Topi)
v3: Add Broadwell support.
v4: Make hardware binding table bit definitions even more clearer (Ken)

Cc: kenneth@whitecape.org
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
6 years agovc4: Switch to using a separate ioctl for making shaders.
Eric Anholt [Fri, 17 Jul 2015 17:01:48 +0000 (10:01 -0700)]
vc4: Switch to using a separate ioctl for making shaders.

This gives the kernel a chance to validate and lock down the data,
without having to deal with mmap zapping.

With this, GLBenchmark stops on a texture relocations, because we'd
recycled a shader BO as another shader and failed to revalidate, since we
weren't clearing the cached validation state on mmap faults.

6 years agomesa: fix up some texture error checks
Roland Scheidegger [Fri, 17 Jul 2015 16:01:01 +0000 (18:01 +0200)]
mesa: fix up some texture error checks

In particular, we were incorrectly accepting s3tc (and lots of others)
for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d
targets. At this time, the only allowed formats for these calls are the
bptc ones, since none of the specific extensions allow it (astc hdr would).
Also, fix up a bug in _mesa_target_can_be_compressed - 3d target needs to
be allowed for bptc formats.

Reviewed-by: Brian Paul <brianp@vmware.com>
6 years agovc4: Fix printing of shader-db debug when shader-db isn't turned on.
Eric Anholt [Fri, 17 Jul 2015 18:52:09 +0000 (11:52 -0700)]
vc4: Fix printing of shader-db debug when shader-db isn't turned on.

6 years agovc4: Add debugging on texture relocation validation failures.
Eric Anholt [Fri, 17 Jul 2015 18:22:40 +0000 (11:22 -0700)]
vc4: Add debugging on texture relocation validation failures.

6 years agovc4: Also consider uniform 0 in uniform lowering.
Eric Anholt [Thu, 16 Jul 2015 21:30:28 +0000 (14:30 -0700)]
vc4: Also consider uniform 0 in uniform lowering.

The hash table considers key 0 to be the empty key.

6 years agovc4: Use the pure/const attributes on a bunch of our QPU functions.
Eric Anholt [Fri, 10 Jul 2015 23:30:27 +0000 (16:30 -0700)]
vc4: Use the pure/const attributes on a bunch of our QPU functions.

On a release build, this makes the rest of vc4_qpu_validate.c go away
(the compiler didn't know that our qpu helper function calls had no
side effects).

6 years agomesa: Detect and provide macros for function attributes pure and const.
Eric Anholt [Fri, 10 Jul 2015 23:25:26 +0000 (16:25 -0700)]
mesa: Detect and provide macros for function attributes pure and const.

These are really useful hints to the compiler in the absence of link-time
optimization, and I'm going to use them in VC4.

I've made the const attribute be ATTRIBUTE_CONST unlike other function
attributes, because we have other things in the tree #defining CONST for
their own unrelated purposes.

v2: Alphabetize.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
6 years agoi965/fs: don't make unused payload registers interfere
Connor Abbott [Tue, 30 Jun 2015 20:42:15 +0000 (13:42 -0700)]
i965/fs: don't make unused payload registers interfere

Before, we were setting payload_last_use_ip for unused payload
registers to 0, which made them interfere with whatever the first
instruction wrote to due to the workaround for SIMD16 uniform arguments.
Just use -1 to mean "unused" instead, and then skip setting any
interferences for unused payload registers.

instructions in affected programs:     0 -> 0
helped:                                0
HURT:                                  0
GAINED:                                1
LOST:                                  0

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
6 years agoi965/fs: remove special case in setup_payload_interference()
Connor Abbott [Tue, 30 Jun 2015 20:38:20 +0000 (13:38 -0700)]
i965/fs: remove special case in setup_payload_interference()

regs_read() will handle LINTERP for us since the previous commit. In
addition, we were being too conservative, since it will only read 2
registers on SIMD8.

instructions in affected programs:     9061 -> 8893 (-1.85%)
helped:                                10
HURT:                                  0
GAINED:                                0
LOST:                                  0

All of the changes were due to spills being eliminated, mostly in KSP
shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
6 years agoi965/fs: Mark last used ip for all regs read in the payload
Jordan Justen [Mon, 2 Feb 2015 22:23:35 +0000 (14:23 -0800)]
i965/fs: Mark last used ip for all regs read in the payload

If a source register in the push constant registers uses more than one
register, then we wouldn't update payload_last_use_ip for subsequent
registers.

Unlike most uniform data pushed into registers, the CS gl_LocalInvocationID
data varies per execution channel. Therefore for SIMD16 mode, we have vec16
data in the payload. In this case we then need to mark 2 registers in
payload_last_use_ip as last used by the instruction. There's a similar
situation for the z and w coordinates of gl_FragCoord for fragment shaders,
where it had only happened to work before because of some bogus interferences
which the next commit removes.

(Connor: added bit about gl_FragCoord to commit message)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
6 years agoi965/fs: fix regs_read() for LINTERP
Connor Abbott [Wed, 1 Jul 2015 16:58:47 +0000 (09:58 -0700)]
i965/fs: fix regs_read() for LINTERP

The second source always stays within the same SIMD8 register.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
6 years agonir: add nir_foreach_instr_safe_reverse()
Connor Abbott [Wed, 15 Jul 2015 19:01:20 +0000 (12:01 -0700)]
nir: add nir_foreach_instr_safe_reverse()

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
6 years agonir: add nir_instr_is_first() and nir_instr_is_last() helpers
Connor Abbott [Wed, 15 Jul 2015 19:00:47 +0000 (12:00 -0700)]
nir: add nir_instr_is_first() and nir_instr_is_last() helpers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott@intel.com>
6 years agoi965/cs: Use dispatch width of 8 for cs terminate payload setup
Jordan Justen [Thu, 16 Jul 2015 22:07:05 +0000 (15:07 -0700)]
i965/cs: Use dispatch width of 8 for cs terminate payload setup

This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var < num_vars' failed.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
6 years agoi965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATE
Jordan Justen [Thu, 16 Jul 2015 22:04:43 +0000 (15:04 -0700)]
i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATE

This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_read: Assertion `var < num_vars' failed.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
6 years agoprogram: Allow redundant OPTION ARB_fog_* directives.
Kenneth Graunke [Sun, 5 Jul 2015 02:15:16 +0000 (19:15 -0700)]
program: Allow redundant OPTION ARB_fog_* directives.

A fragment program from "Pixel Piracy" contains redundant OPTION
directives:

!!ARBfp1.0
OPTION ARB_precision_hint_fastest;
OPTION ARB_fog_exp2;
OPTION ARB_precision_hint_fastest;
OPTION ARB_fog_exp2;
...

We already allow redundant ARB_precision_hint_fastest directives, but
disallow the redundant (yet consistent) ARB_fog_exp2 directives, failing
to compile the program.

The specification seems to contradict itself - the main text says that
only one fog application option may be specified, but then backpedals,
indicating the intent is to disallow /contradictory/ flags.  One of the
issues suggests that specifying contradictory ones is stupid, but
allowed, and only the last one should take effect.

Accepting multiple redundant (but consistent) directives seems harmless,
and like a reasonable interpretation of the specification.  It also
fixes a fragment program found in the wild.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965: Push miptree tiling request into flags
Ben Widawsky [Tue, 14 Jul 2015 16:56:09 +0000 (09:56 -0700)]
i965: Push miptree tiling request into flags

With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.

The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.

v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)

v3: small fix in assertion requested by Chad

v4: Use parens to get the order right from v3.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
6 years agoRevert "i965: Push miptree tiling request into flags"
Ben Widawsky [Thu, 16 Jul 2015 23:52:08 +0000 (16:52 -0700)]
Revert "i965: Push miptree tiling request into flags"

This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.

6 years agoi965: Push miptree tiling request into flags
Ben Widawsky [Tue, 14 Jul 2015 16:56:09 +0000 (09:56 -0700)]
i965: Push miptree tiling request into flags

With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.

The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.

v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)

v3: small fix in assertion requested by Chad

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v2)
Reviewed-by: Chad Versace <chad.versace@intel.com> (v2)
6 years agoi965/fs: Factor out universally broken calculation of the register component size.
Francisco Jerez [Tue, 14 Jul 2015 12:43:44 +0000 (15:43 +0300)]
i965/fs: Factor out universally broken calculation of the register component size.

This in principle simple calculation was being open-coded in a number
of places (in a series I haven't yet sent for review there will be a
couple more), all of them were subtly broken in one way or another:
None of them were handling the HW_REG case correctly as pointed out by
Connor, and fs_inst::regs_read() was handling the stride=0 case rather
naively.  This patch solves both problems and factors out the
calculation as a new fs_reg method.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
6 years agoi965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.
Francisco Jerez [Thu, 9 Jul 2015 18:42:28 +0000 (21:42 +0300)]
i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.

This gets rid of two no16() fall-backs and should allow better
scheduling of the generated IR.  There are no uses of usubBorrow() or
uaddCarry() in shader-db so no changes are expected.  However the
"arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow" and
"arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry" piglit
tests go from 40 to 28 instructions.  The reason is that the plain ADD
instruction can easily be CSE'ed with the original addition, and the
b2i negation can easily be propagated into the source modifier of
another instruction, so effectively both operations are performed with
just one instruction.

v2: Rely on carry_to_arith() and borrow_to_arith() to lower these
    (Ilia Mirkin).

Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agoi965: Implement b2f and b2i using negation.
Francisco Jerez [Fri, 10 Jul 2015 16:18:39 +0000 (19:18 +0300)]
i965: Implement b2f and b2i using negation.

Booleans are represented as 0/-1 on modern hardware which means we can
just negate them to convert them into a numeric type.  Negation has
the benefit that it can be implemented using a source modifier which
can easily be propagated into some other instruction.  shader-db
results on HSW:

total instructions in shared programs: 6349082 -> 6346693 (-0.04%)
instructions in affected programs:     40948 -> 38559 (-5.83%)
helped:                                123
HURT:                                  1
GAINED:                                1
LOST:                                  0

Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agogallium: add interface for writable shader buffers
Marek Olšák [Sun, 5 Jul 2015 13:00:22 +0000 (15:00 +0200)]
gallium: add interface for writable shader buffers

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agogallium: add interface for writable shader images
Marek Olšák [Sun, 5 Jul 2015 12:48:33 +0000 (14:48 +0200)]
gallium: add interface for writable shader images

PIPE_CAPs will be added some other time.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agogallium: add new limits for shader buffers and images
Marek Olšák [Sun, 5 Jul 2015 12:34:13 +0000 (14:34 +0200)]
gallium: add new limits for shader buffers and images

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agogallium: add BIND flags for R/W buffers and images
Marek Olšák [Sun, 5 Jul 2015 11:51:16 +0000 (13:51 +0200)]
gallium: add BIND flags for R/W buffers and images

PIPE_CAPs and TGSI support will be added later. The TGSI support should be
straightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE
and TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary.

The idea is:
* ARB_shader_image_load_store should use set_shader_images.
* ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1)
  if M shader storage buffers are supported.
* ARB_shader_atomic_counters should use set_shader_buffers(slots M..N)
  if N-M+1 atomic counter buffers are supported.

PIPE_CAPs can describe various constraints for early DX11 hardware.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agogallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
Marek Olšák [Fri, 12 Jun 2015 12:24:17 +0000 (14:24 +0200)]
gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGS

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agoi965/gen9: Use custom MOCS entries set up by the kernel.
Francisco Jerez [Wed, 1 Jul 2015 13:32:24 +0000 (16:32 +0300)]
i965/gen9: Use custom MOCS entries set up by the kernel.

Instead of relying on hardware defaults the i915 kernel driver is
going program custom MOCS tables system-wide on Gen9 hardware.  The
"WT" entry previously used for renderbuffers had a number of problems:
It disabled caching on eLLC, it used a reserved L3 cacheability
setting, and it used to override the PTE controls making renderbuffers
always WT on LLC regardless of the kernel's setting.  Instead use an
entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE,
L3CC=WB.

The "WB" entry previously used for anything other than renderbuffers
has moved to a different index in the new MOCS tables but it should
have the same caching semantics as the old entry.

Even though the corresponding kernel change ("drm/i915: Added
Programming of the MOCS") is in a way an ABI break it doesn't seem
necessary to check that the kernel is recent enough because the change
should only affect Gen9 which is still unreleased hardware.

v2: Update MOCS values for the new Android-incompatible tables
    introduced in v7 of the kernel patch.

Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
6 years agoclover: little OpenCL status code logging clean
EdB [Tue, 7 Jul 2015 15:58:56 +0000 (17:58 +0200)]
clover: little OpenCL status code logging clean

s/build_error/compile_error in order to match the stored OpenCL status code.
Make program::build catch and log every OpenCL error.
Make tgsi error triggering uniform with the llvm one.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
6 years agoglsl: avoid compiler's segfault when processing operators with void arguments
Renaud Gaubert [Sat, 11 Jul 2015 17:38:10 +0000 (19:38 +0200)]
glsl: avoid compiler's segfault when processing operators with void arguments

This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.

This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignment of a void variable
which will be optimized out (the assignment) during the optimization
pass.

This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.

Thus preventing to dereference NULL in the following cases:
  * binary operator
  * unary operators
  * ternary operator
  * comparison operators (except equal and nequal operator)

Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252

Signed-off-by: Renaud Gaubert <renaud@lse.epita.fr>
Reviewed-by: Gabriel Laskar <gabriel@lse.epita.fr>
Reviewed-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
6 years agor200: fix some potential big endian issues
Roland Scheidegger [Thu, 16 Jul 2015 01:55:59 +0000 (03:55 +0200)]
r200: fix some potential big endian issues

The formats chosen (both by texture format choser, fbo storage allocation)
are different for big endian not just for rgba8 but also lower bit width
formats (why I don't actually know). Even the function to test for renderable
formats used different formats, however the actual colorbuffer setup did not.
And the blitter did not take that into account neither.
Untested (what could possibly go wrong...).
Same as for r100.

Acked-by: Marek Olšák <marek.olsak@amd.com>
6 years agoradeon: fix some potential big endian issues
Roland Scheidegger [Thu, 16 Jul 2015 01:18:20 +0000 (03:18 +0200)]
radeon: fix some potential big endian issues

The formats chosen (both by texture format choser, fbo storage allocation)
are different for big endian not just for rgba8 but also lower bit width
formats (why I don't actually know). Even the function to test for renderable
formats used different formats, however the actual colorbuffer setup did not.
And the blitter did not take that into account neither.
Untested (what could possibly go wrong...).

Acked-by: Marek Olšák <marek.olsak@amd.com>
6 years agoradeon/r200: mark state atoms as dirty after blits
Roland Scheidegger [Sat, 11 Jul 2015 18:03:27 +0000 (20:03 +0200)]
radeon/r200: mark state atoms as dirty after blits

Blit submits lots of packets which are usually handled by state atoms, so
these must be dirtied.
Not sure if this fixes anything, but it was a concern raised by bug 51658
(with this all issues there seen as actual bugs should be fixed, with the
exception of the patch to upload non-used texenv state atoms which I just
don't understand).

Acked-by: Marek Olšák <marek.olsak@amd.com>
6 years agor200: fix fbo rendering by disabling optimized texture format chooser
Roland Scheidegger [Thu, 16 Jul 2015 01:06:47 +0000 (03:06 +0200)]
r200: fix fbo rendering by disabling optimized texture format chooser

It is rather unfortunate that we don't know if a texture is going to be used
as a rt later, and we lack the means to do something about a format chosen
which we can't render to directly, so disable this and always chose renderable
format for rgba8 textures.
This addresses an issue raised on (old) bug,
https://bugs.freedesktop.org/show_bug.cgi?id=51658 with gnome-shell, don't
know if that's still applicable but it might fix other things as well.

Acked-by: Marek Olšák <marek.olsak@amd.com>
6 years agoi965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()
Anuj Phogat [Tue, 7 Jul 2015 19:23:33 +0000 (12:23 -0700)]
i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()

Along with fixing the type of pitch parameter, patch also changes
the types of few local variables and function return type.

Warnings fixed are:
intel_mipmap_tree.c:671:7: warning: passing argument 3 of
'intel_get_yf_ys_bo_size' from incompatible pointer type

intel_mipmap_tree.c:563:1: note: expected 'uint64_t *' but
argument is of type 'long unsigned int *'

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Optimize batchbuffer macros.
Matt Turner [Thu, 9 Jul 2015 02:00:48 +0000 (19:00 -0700)]
i965: Optimize batchbuffer macros.

Previously OUT_BATCH was just a macro around an inline function which
does

   brw->batch.map[brw->batch.used++] = dword;

When making consecutive calls to intel_batchbuffer_emit_dword() the
compiler isn't able to recognize that we're writing consecutive memory
locations or that it doesn't need to write batch.used back to memory
each time.

We can avoid both of these problems by making a local pointer to the
next location in the batch in BEGIN_BATCH().

Cuts 18k from the .text size.

   text     data      bss      dec      hex  filename
4946956   195152    26192  5168300   4edcac  i965_dri.so before
4928956   195152    26192  5150300   4e965c  i965_dri.so after

This series (including commit c0433948) improves performance of Synmark
OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agoi965: Add and use USED_BATCH macro.
Matt Turner [Sat, 11 Jul 2015 21:36:25 +0000 (14:36 -0700)]
i965: Add and use USED_BATCH macro.

The next patch will replace the .used field with an on-demand
calculation of batchbuffer usage.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agoi965: Split batch emission from relocation functions.
Matt Turner [Thu, 9 Jul 2015 01:59:51 +0000 (18:59 -0700)]
i965: Split batch emission from relocation functions.

So that everything writing to the batch between BEGIN_BATCH() and
ADVANCE_BATCH() goes through OUT_BATCH.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agoi965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().
Matt Turner [Thu, 9 Jul 2015 01:56:52 +0000 (18:56 -0700)]
i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().

BEGIN_BATCH() and ADVANCE_BATCH() will contain "do {" and "} while (0)"
respectively to allow declaring local variables used by intervening
OUT_BATCH macros. As such, BEGIN_BATCH() and ADVANCE_BATCH() need to be
in the same control flow.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agoosmesa: fix OSMesaPixelsStore typo
Brian Paul [Wed, 15 Jul 2015 12:15:06 +0000 (06:15 -0600)]
osmesa: fix OSMesaPixelsStore typo

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91337
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>