mesa.git
2 years agoetnaviv: Fix double-free in etna_bo_cache_free()
Marek Vasut [Sat, 1 Jun 2019 23:07:28 +0000 (01:07 +0200)]
etnaviv: Fix double-free in etna_bo_cache_free()

The following situation can happen in a multithreaded OpenGL application.
A BO is submitted from etna_cmd_stream #1 with flags set for read.
A BO is submitted from etna_cmd_stream #2 with flags set for write.
This triggers a flush on stream #1 and clears the BO's current_stream
pointer. If at this point, stream #2 attempts to queue BO again, which
does happen, the BO will be added to the submit list twice. The Linux
kernel driver correctly detects this and warns about it with "BO at
index %u already on submit list" kernel message.

However, when cleaning the BO cache in etna_bo_cache_free(), the BO
which was submitted twice will also be free()d twice, this triggering
a glibc double free detector.

The fix is easy, even if the BO does not have current_stream set,
iterate over current streams' list of BOs before adding the BO to it
and verify that the BO is not yet there.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2 years agokmsro: Add missing definitions to Android.mk
Roman Stratiienko [Tue, 6 Aug 2019 10:29:06 +0000 (13:29 +0300)]
kmsro: Add missing definitions to Android.mk

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Rob Herring robh@kernel.org
2 years agosoftpipe: Add support for ARB_derivative_control
Gert Wollny [Tue, 13 Aug 2019 16:08:34 +0000 (18:08 +0200)]
softpipe: Add support for ARB_derivative_control

Enables and passes piglits:

spec/ARB_drivative_control/
        dfdx-coarse
        dfdx-dfdy
        dfdx-fine
        dfdy-coarse
        dfdy-fine

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2 years agolima/ppir: print srcs and dests in ppir_node_print_prog()
Vasily Khoruzhick [Fri, 2 Aug 2019 04:27:17 +0000 (21:27 -0700)]
lima/ppir: print srcs and dests in ppir_node_print_prog()

Now we have an accessors for ppir src, so it's possible to easily
print all srcs and dests while dumping ppir representation.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/ppir: use src accessors in ppir regalloc
Vasily Khoruzhick [Fri, 2 Aug 2019 05:04:34 +0000 (22:04 -0700)]
lima/ppir: use src accessors in ppir regalloc

Get rid of most switch/case by using src accessors

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/ppir: add ppir_node to ppir_src
Vasily Khoruzhick [Wed, 24 Jul 2019 22:29:34 +0000 (15:29 -0700)]
lima/ppir: add ppir_node to ppir_src

We'll need it if we want to walk through node sources

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/ppir: introduce accessors for ppir_node sources
Vasily Khoruzhick [Wed, 24 Jul 2019 22:25:33 +0000 (15:25 -0700)]
lima/ppir: introduce accessors for ppir_node sources

Sometimes we need to walk through ppir_node sources, common
accessor for all node types will simplify code a lot.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agoiris: Expose aux buffer as 2nd plane w/modifiers
Jordan Justen [Tue, 25 Jun 2019 02:24:37 +0000 (19:24 -0700)]
iris: Expose aux buffer as 2nd plane w/modifiers

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Export and import surfaces with modifiers that have aux data
Jordan Justen [Tue, 9 Jul 2019 07:47:15 +0000 (00:47 -0700)]
iris: Export and import surfaces with modifiers that have aux data

The DRI interface for modifiers with aux data treats the aux data as a
separate plane of the main surface.

When the dri layer requests the plane associated with the aux data, we
save the required information into the dri aux plane image.

Later when the image is used, the dri plane image will be available in
the pipe_resource structure's `next` field. Therefore in iris, we
reconstruct the aux setup from this separate dri plane image when the
image is used.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Do proper format checks for Y+CCS modifier support
Kenneth Graunke [Tue, 26 Mar 2019 07:25:31 +0000 (00:25 -0700)]
iris: Do proper format checks for Y+CCS modifier support

We need to ensure that the DRI image format supports CCS.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2 years agoiris: Create single bo for surfaces with modifiers and aux data
Jordan Justen [Sun, 23 Jun 2019 08:16:48 +0000 (01:16 -0700)]
iris: Create single bo for surfaces with modifiers and aux data

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Split iris_resource_alloc_aux to enable aux modifiers
Jordan Justen [Sun, 23 Jun 2019 07:53:23 +0000 (00:53 -0700)]
iris: Split iris_resource_alloc_aux to enable aux modifiers

Reworks:

 * If the aux-state is not ISL_AUX_STATE_AUX_INVALID, then use memset
   even when memset_value is zero. The hiz buffer initial aux-state
   will be set to invalid, and therefore we can skip the memset. But,
   for CCS it will be set to ISL_AUX_STATE_PASS_THROUGH, and therefore
   the aux data must be cleared to 0 with the memset. Previously we
   would use BO_ALLOC_ZEROED with the CCS aux data, so this memset
   wasn't required. Now, the CCS aux data may be part of the main
   surface. We prefer to not use BO_ALLOC_ZEROED excessively, so the
   memset is needed for the CCS case. (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Add aux offset into hiz_address
Jordan Justen [Tue, 13 Aug 2019 08:37:11 +0000 (01:37 -0700)]
iris: Add aux offset into hiz_address

This is not currently required because the hiz buffer is in a separate
buffer, and therefore the offset is 0. If we combine the aux buffer
with the main surface buffer, then the hiz offset may become non-zero.

Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agotgsi_to_nir: add assertions for max varying slots
Marek Olšák [Tue, 13 Aug 2019 22:14:17 +0000 (18:14 -0400)]
tgsi_to_nir: add assertions for max varying slots

Nine uses GENERIC slots > 31.

Trivial.

2 years agotgsi_to_nir: expand vec3 system values to vec4
Marek Olšák [Tue, 13 Aug 2019 19:26:51 +0000 (15:26 -0400)]
tgsi_to_nir: expand vec3 system values to vec4

for nir_intrinsic_load_work_group_id

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agotgsi_to_nir: fix incorrect number of image src1 components
Marek Olšák [Tue, 13 Aug 2019 19:25:40 +0000 (15:25 -0400)]
tgsi_to_nir: fix incorrect number of image src1 components

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoi965/gen11: fix genX_bits.h include path
Mauro Rossi [Tue, 13 Aug 2019 15:38:29 +0000 (17:38 +0200)]
i965/gen11: fix genX_bits.h include path

Instead of "genX_bits.h" use "genxml/genX_bits.h"
as already done in other similar cases

Besides being more correct, it also fixes building error in Android.

Fixes: f0d2923 ("i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2 years agopanfrost: Workaround bug in partial update implementation
Alyssa Rosenzweig [Tue, 13 Aug 2019 14:19:27 +0000 (07:19 -0700)]
panfrost: Workaround bug in partial update implementation

We can't intersect with empty regions.

Fixes: 65ae86b8542 ("panfrost: Add support for KHR_partial_update()")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agogitlab-ci: Run the GLES2 CTS on llvmpipe.
Eric Anholt [Fri, 28 Jun 2019 23:35:32 +0000 (16:35 -0700)]
gitlab-ci: Run the GLES2 CTS on llvmpipe.

This is the start of doing CTS tests on merges to Mesa master.  We use
the surfaceless platform so that we don't need to bother bringing up
weston or X11.  The surface size is kept low to reduce runtime, but
this comes at the cost of many rendering tests skipping due to
too-small render targets (as we see the impact of Mesa on the shared
runner pool, we can reevaluate this and what set of CTS tests we want
to run).

We split the job up across 4 runners (each at 4 llvmpipe threads), so
that the job can load-balance across our shared runners and finish
sooner (since dEQP is very single-thread-performance bound).

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agogitlab-ci: Switch the meson-main build type to debugoptimized.
Eric Anholt [Thu, 1 Aug 2019 19:14:15 +0000 (12:14 -0700)]
gitlab-ci: Switch the meson-main build type to debugoptimized.

Now that we're running the drivers we build, building with
optimization is important for keeping our runtime down.  Shaves about
4 minutes of runtime off of GLES2 CTS of llvmpipe at 64x64.

v2: Only switch meson-main until we enable CTS for other builds
    on request by Michel.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agogitlab-ci: Set the prefix to ./install instead of the DESTDIR.
Eric Anholt [Thu, 25 Jul 2019 18:02:34 +0000 (11:02 -0700)]
gitlab-ci: Set the prefix to ./install instead of the DESTDIR.

If we don't set DESTDIR, then the DEFAULT_DRIVER_DIR built into the
libraries is correct and we don't need to use LIBGL_DRIVERS_PATH and
friends for CI usage.  Incidentally, this moves our installed paths
from /builds/anholt/mesa/install/usr/local/lib (for example) to
/builds/anholt/mesa/install/lib for simplicity.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agogitlab-ci: Build the CTS in the debian build image.
Eric Anholt [Mon, 22 Jul 2019 19:03:47 +0000 (12:03 -0700)]
gitlab-ci: Build the CTS in the debian build image.

This will let us reuse the image for test runs.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agosurfaceless: Fix swrast-path segfault when loader doesn't know driver name.
Eric Anholt [Mon, 29 Jul 2019 23:25:56 +0000 (16:25 -0700)]
surfaceless: Fix swrast-path segfault when loader doesn't know driver name.

If we're hitting the swrast fallback path here, it's probably because
we stumbled across a KMS-only device (such as the ASpeed that some of
our CI runners have) that will then return a NULL driver_name.  Don't
crash in that case.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agosurfaceless: Fix swrast path.
Eric Anholt [Tue, 23 Jul 2019 20:18:21 +0000 (13:18 -0700)]
surfaceless: Fix swrast path.

We get a getDrawableInfo() call in the MakeCurrent path, which
platform_device was handling correctly by returning the pbuffer's
width/height but platform_surfaceless segfaulted for.  Reuse
platform_device's implementation.

Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2 years agogitlab-ci: Move around which builds cover which swrast.
Eric Anholt [Wed, 7 Aug 2019 21:05:51 +0000 (14:05 -0700)]
gitlab-ci: Move around which builds cover which swrast.

I want to enable CI of llvmpipe out of the meson-main build.  So, kick
classic swrast/osmesa to meson-i386, then promote llvmpipe to
meson-main (along with nine, now that classic osmesa isn't keeping it
out of there).

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agomeson: Don't require DRI classic swrast for OSMesa.
Eric Anholt [Thu, 18 Jul 2019 21:45:57 +0000 (14:45 -0700)]
meson: Don't require DRI classic swrast for OSMesa.

OSMesa doesn't care about this build option, it links against
src/mesa/swrast regardless.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2 years agopanfrost: Implement transform feedback
Alyssa Rosenzweig [Fri, 9 Aug 2019 19:32:49 +0000 (12:32 -0700)]
panfrost: Implement transform feedback

Midgard has no hardware support for transform feedback, so we simulate
it in software. Lucky us.

What Midgard does do is write out vertex shader outputs to main memory
unconditonally. Fragment shaders read varyings back from main memory;
there's no on-chip storage for varyings. Whether this was a reasonable
design is a question I will not be engaging in this commit message.

What that does mean is that, in some sense, Midgard *always* does
transform feedback uncondtionally, and there's no way to turn off
transform feedback. Normally, we would allocate some scratch memory
every frame to store the varyings in an arbitrary format (interleaved
for simplicity), and then feed that scratch to the fragment shader and
discard when the rendering completes.

The only difference now is that sometimes, for some buffers, we use a BO
provided to us by Gallium and a format provided by Gallium, instead of
allocating the memory and choosing the format ourselves. This has some
limitations -- in particular, it only works at vec4 granularity, so a
corresponding GLSL linkage patch is needed to correctly implement
transform feedback for non-vec4 types. Nevertheless, given the hardware
already works in this admittedly-bizarre fashion, transform feedback is
"free". Or, at least, it's no more expensive than any other rendering.

Specifically not implemented is dynamically-sized transform feedback
(i.e. with geometry/tesselation shaders).

Spoiler alert: Midgard has no support for geometry *or* tessellation
shaders, despite advertising support. They get compiled to *massive*
compute shaders. How's that for checkbox compliance?

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Increment offsets[] per draw
Alyssa Rosenzweig [Thu, 8 Aug 2019 15:16:09 +0000 (08:16 -0700)]
panfrost: Increment offsets[] per draw

We have to maintain the internal offset ourselves. Per v3d.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Fixup stream out information per variant
Alyssa Rosenzweig [Wed, 7 Aug 2019 17:33:15 +0000 (10:33 -0700)]
panfrost: Fixup stream out information per variant

We could probably get away with doing this once per pipe_shader_state
but let's not jump down that rabbit hole quite yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Route outputs_written through the compiler
Alyssa Rosenzweig [Wed, 7 Aug 2019 17:26:12 +0000 (10:26 -0700)]
panfrost: Route outputs_written through the compiler

It's there in shader_info, but we need to access it from pan_context.c

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Import stream out utility from iris
Alyssa Rosenzweig [Wed, 7 Aug 2019 17:11:28 +0000 (10:11 -0700)]
panfrost: Import stream out utility from iris

We'll need this in a moment. Ken's implementation, lightly edited for
Panfrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Flush when using transform feedback
Alyssa Rosenzweig [Thu, 8 Aug 2019 14:46:54 +0000 (07:46 -0700)]
panfrost: Flush when using transform feedback

This is a huge hack to workaround incomplete BO flushing logic, but it's
enough for the dEQP transform feedback tests, and doing the resource
management to get this right is out-of-scope for this patch series.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Set PIPE_CAP_TGSI_TEXCOORD
Alyssa Rosenzweig [Wed, 7 Aug 2019 19:00:14 +0000 (12:00 -0700)]
panfrost: Set PIPE_CAP_TGSI_TEXCOORD

It doesn't really make sense, since we don't have special texture
coordinate varyings, but it'll make some code simpler for XFB and it
doesn't hurt us, even if I lose a bit of my soul setting it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Wire up statistics for primitives
Alyssa Rosenzweig [Thu, 8 Aug 2019 14:10:24 +0000 (07:10 -0700)]
panfrost: Wire up statistics for primitives

GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN should now be handled.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Implement callbacks for PRIMITIVES queries
Alyssa Rosenzweig [Thu, 8 Aug 2019 14:01:12 +0000 (07:01 -0700)]
panfrost: Implement callbacks for PRIMITIVES queries

We're just going to compute them in the driver but let's get the
structures setup to handle them. Implementation from v3d.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agofreedreno/a6xx: move SSBO/image consts to IBO stateobj
Rob Clark [Wed, 7 Aug 2019 18:40:31 +0000 (11:40 -0700)]
freedreno/a6xx: move SSBO/image consts to IBO stateobj

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: move VS driverparams to it's own stateobj
Rob Clark [Wed, 7 Aug 2019 18:34:03 +0000 (11:34 -0700)]
freedreno/a6xx: move VS driverparams to it's own stateobj

If driver-params are required, we really should emit it on every draw
for correctness.  And if not required, we should emit a DISABLE so that
un-applied state updates from previous draws don't corrupt the const
state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3+a6xx: same VBO state for draw/binning
Rob Clark [Fri, 2 Aug 2019 21:07:47 +0000 (14:07 -0700)]
freedreno/ir3+a6xx: same VBO state for draw/binning

Worth ~+20% on gl_driver2

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: add fd_emit_take_group()
Rob Clark [Fri, 2 Aug 2019 16:57:08 +0000 (09:57 -0700)]
freedreno/a6xx: add fd_emit_take_group()

Which takes ownership of the stateobj.  Useful for streaming state-
objs, to avoid an extra ref/unref

Worth ~5% at gl_driver2

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: track # of driver params
Rob Clark [Thu, 1 Aug 2019 21:22:46 +0000 (14:22 -0700)]
freedreno/ir3: track # of driver params

To avoid emitting unneeded const state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: move immediates to program stateobj
Rob Clark [Thu, 1 Aug 2019 15:35:14 +0000 (08:35 -0700)]
freedreno/a6xx: move immediates to program stateobj

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: stop using ir3_emit_{vs,fs}_consts()
Rob Clark [Thu, 1 Aug 2019 15:31:25 +0000 (08:31 -0700)]
freedreno/a6xx: stop using ir3_emit_{vs,fs}_consts()

Should be no functional change.  Next step is to re-arrange various
const state into different stateobjs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: push ctx further up call chain
Rob Clark [Thu, 1 Aug 2019 15:13:02 +0000 (08:13 -0700)]
freedreno/ir3: push ctx further up call chain

Move more of the code to deal just w/ screen, without requiring ctx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: move ring_wfi() further up call chain
Rob Clark [Thu, 1 Aug 2019 02:00:59 +0000 (19:00 -0700)]
freedreno/ir3: move ring_wfi() further up call chain

Hoist them out of code-paths that will eventually be called directly for
various a6xx+ const related stateobjs.

This ends up duplicating one constlen check in ir3_emit_vs_consts(), to
avoid what could otherwise be an unnecessary WFI on older gens.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/all: move more emit helpers to screen
Rob Clark [Thu, 1 Aug 2019 01:26:57 +0000 (18:26 -0700)]
freedreno/all: move more emit helpers to screen

framebuffer_barrier() still depends on the ctx, but the rest can move to
screen.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a3xx-a6xx+ir3: move emit_const* to screen
Rob Clark [Thu, 1 Aug 2019 01:20:52 +0000 (18:20 -0700)]
freedreno/a3xx-a6xx+ir3: move emit_const* to screen

These don't need to be in context, and we'll need them in screen in a
later patch.  Plus it's a good cleanup.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: add fd6_emit_init_screen()
Rob Clark [Thu, 1 Aug 2019 01:13:38 +0000 (18:13 -0700)]
freedreno/a6xx: add fd6_emit_init_screen()

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a5xx: add fd5_emit_init_screen()
Rob Clark [Thu, 1 Aug 2019 01:12:00 +0000 (18:12 -0700)]
freedreno/a5xx: add fd5_emit_init_screen()

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a3xx: add fd3_emit_init_screen()
Rob Clark [Thu, 1 Aug 2019 01:09:26 +0000 (18:09 -0700)]
freedreno/a3xx: add fd3_emit_init_screen()

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a2xx: add fd2_emit_init_screen()
Rob Clark [Thu, 1 Aug 2019 01:01:07 +0000 (18:01 -0700)]
freedreno/a2xx: add fd2_emit_init_screen()

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a4xx: add fd4_emit_init_screen()
Rob Clark [Thu, 1 Aug 2019 00:58:56 +0000 (17:58 -0700)]
freedreno/a4xx: add fd4_emit_init_screen()

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a2xx: call fd2_emit_ib() directly from fd2
Rob Clark [Thu, 1 Aug 2019 00:43:32 +0000 (17:43 -0700)]
freedreno/a2xx: call fd2_emit_ib() directly from fd2

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a5xx: call fd5_emit_ib() directly from fd5
Rob Clark [Thu, 1 Aug 2019 00:41:20 +0000 (17:41 -0700)]
freedreno/a5xx: call fd5_emit_ib() directly from fd5

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a4xx: call fd4_emit_ib() directly from fd4
Rob Clark [Thu, 1 Aug 2019 00:37:57 +0000 (17:37 -0700)]
freedreno/a4xx: call fd4_emit_ib() directly from fd4

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a3xx: call fd3_emit_ib() directly from fd3
Rob Clark [Thu, 1 Aug 2019 00:35:11 +0000 (17:35 -0700)]
freedreno/a3xx: call fd3_emit_ib() directly from fd3

No reason for the indirection when called from a3xx specific code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: move VS driver-param emit
Rob Clark [Wed, 31 Jul 2019 22:23:49 +0000 (15:23 -0700)]
freedreno/ir3: move VS driver-param emit

Move DP emit to it's own function.  No functional change, just code
motion to prepare for splitting up const state into multiple state-
objs on a6xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: drop unneeded ir3_ra() args
Rob Clark [Mon, 5 Aug 2019 15:35:10 +0000 (08:35 -0700)]
freedreno/ir3: drop unneeded ir3_ra() args

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agopanfrost: Add support for KHR_partial_update()
Boris Brezillon [Mon, 12 Aug 2019 10:07:08 +0000 (12:07 +0200)]
panfrost: Add support for KHR_partial_update()

Implement ->set_damage_region() region to support partial updates.

This is a dummy implementation in that it does not try to merge
damage rects. It also does not deal with distinct regions and instead
pick the largest quad as the only damage rect and generate up to 4
reload rects out of it (the left/right/top/bottom regions surrounding
the biggest damage rect).

We also do not try to reduce the number of draws by passing all quad
vertices to the blit request (would require extending u_blitter)

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agost/dri2: Implement DRI2bufferDamageExtension
Daniel Stone [Mon, 12 Aug 2019 10:07:07 +0000 (12:07 +0200)]
st/dri2: Implement DRI2bufferDamageExtension

Add a pipe_screen->set_damage_region() hook to propagate
set-damage-region requests to the driver, it's then up to the driver to
decide what to do with this piece of information.

If the hook is left unassigned, the buffer-damage extension is
considered unsupported.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoegl/dri: Use __DRI2_BUFFER_DAMAGE extension for KHR_partial_update
Harish Krupo [Mon, 12 Aug 2019 10:07:06 +0000 (12:07 +0200)]
egl/dri: Use __DRI2_BUFFER_DAMAGE extension for KHR_partial_update

Use the DRI2 interface callback to pass the damage rects to
the driver.

Signed-off-by: Harish Krupo <harishkrupo@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agodri_interface: add DRI2_BufferDamage interface
Daniel Stone [Mon, 12 Aug 2019 10:07:05 +0000 (12:07 +0200)]
dri_interface: add DRI2_BufferDamage interface

Add a new DRI2_BufferDamage interface to support the
EGL_KHR_partial_update extension, informing the driver of an overriding
scissor region for a particular drawable.

Based on a commit originally authored by:
Harish Krupo <harish.krupo.kps@intel.com>
renamed extension, retargeted at DRI drawable instead of context,
rewritten description

Signed-off-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoegl/android: Delete set_damage_region from egl dri vtbl
Harish Krupo [Mon, 12 Aug 2019 10:07:04 +0000 (12:07 +0200)]
egl/android: Delete set_damage_region from egl dri vtbl

The intension of the KHR_partial_update was not to send the damage back
to the platform but to send the damage to the driver to ensure that the
following rendering could be restricted to those regions.
This patch removes the set_damage_region from the egl_dri vtbl and all
the platfrom_*.c files.
Then upcomming patches add a new dri2 interface for the drivers to
implement

Signed-off-by: Harish Krupo <harishkrupo@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoiris: Implement pipe_screen::resource_get_param
Jordan Justen [Fri, 2 Aug 2019 08:21:12 +0000 (01:21 -0700)]
iris: Implement pipe_screen::resource_get_param

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agogallium/dri2: Use pipe_screen::resource_get_param in image queries
Jordan Justen [Sat, 3 Aug 2019 08:16:48 +0000 (01:16 -0700)]
gallium/dri2: Use pipe_screen::resource_get_param in image queries

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agogallium/dri2: Support images with multiple planes for modifiers
Jordan Justen [Mon, 24 Jun 2019 17:39:03 +0000 (10:39 -0700)]
gallium/dri2: Support images with multiple planes for modifiers

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agogallium/dri2: Refactor image property queries
Jordan Justen [Sat, 3 Aug 2019 08:14:01 +0000 (01:14 -0700)]
gallium/dri2: Refactor image property queries

This refactor will let us more easily use
pipe_screen::resource_get_param as an alternative to
pipe_screen::resource_get_handle.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agostate_tracker/winsys_handle: Add plane input field
Jordan Justen [Fri, 2 Aug 2019 20:52:29 +0000 (13:52 -0700)]
state_tracker/winsys_handle: Add plane input field

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agogallium/dri2: Support creating multi-planar modifier images
Jordan Justen [Fri, 2 Aug 2019 21:00:08 +0000 (14:00 -0700)]
gallium/dri2: Support creating multi-planar modifier images

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agogallium/dri2: Implement dri2ImageExtension.queryDmaBufFormatModifierAttribs
Jordan Justen [Mon, 8 Jul 2019 22:05:04 +0000 (15:05 -0700)]
gallium/dri2: Implement dri2ImageExtension.queryDmaBufFormatModifierAttribs

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agogallium/screen: Add pipe_screen::resource_get_param
Jordan Justen [Thu, 1 Aug 2019 20:30:21 +0000 (13:30 -0700)]
gallium/screen: Add pipe_screen::resource_get_param

This function retrieves individual parameters selected by enum
pipe_resource_param. It can be used as a more direct alternative to
pipe_screen::resource_get_handle.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
2 years agovc4: clamp gl_PointSize to a minimum of 1.0
Iago Toral Quiroga [Wed, 31 Jul 2019 08:33:08 +0000 (10:33 +0200)]
vc4: clamp gl_PointSize to a minimum of 1.0

The OpenGL ES spec requires that the value of gl_PointSize is clamped
to an implementation-dependent range matching what is advertised by
GL_ALIASED_POINT_SIZE_RANGE. For VC4 this is [1.0, 512.0], but the
hardware won't clamp to the minimum side of the range and won't render
points with a size strictly smaller than 1.0 either, so we need to
clamp manually. For points larger than the maximum size of the range
the hardware clamps automatically.

Fixes piglit test:
spec/!opengl 2.0/vs-point_size-zero

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: clamp gl_PointSize to a minimum of 1.0
Iago Toral Quiroga [Wed, 31 Jul 2019 07:50:34 +0000 (09:50 +0200)]
v3d: clamp gl_PointSize to a minimum of 1.0

The OpenGL ES spec requires that the value of gl_PointSize is clamped
to an implementation-dependent range matching what is advertised by
GL_ALIASED_POINT_SIZE_RANGE. For V3D this is [1.0, 512.0], but the
hardware won't clamp to the minimum side of the range and won't render
points with a size strictly smaller than 1.0 either, so we need to
clamp manually. For points larger than the maximum size of the range
the hardware clamps automatically.

Fixes piglit test:
spec/!opengl 2.0/vs-point_size-zero

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agonir: add a pass to clamp gl_PointSize to a range
Iago Toral Quiroga [Wed, 31 Jul 2019 07:47:08 +0000 (09:47 +0200)]
nir: add a pass to clamp gl_PointSize to a range

The OpenGL and OpenGL ES specs require that implementations clamp the
value of gl_PointSize to an implementation-depedent range. This pass
is useful for any GPU hardware that doesn't do this automatically
for either one or both sides of the range, such as V3D.

v2:
 - Turn into a generic NIR pass (Eric).
 - Make the pass work before lower I/O so we can use the deref variable
   to inspect if we are writing to gl_PointSize (Eric).
 - Make the pass take the range to clamp as parameter and allow it
   to clamp to both sides of the range or just one side.
 - Make the pass report progress.

v3:
 - Fix copyright header (Eric)
 - use fmin/fmax instead of bcsel to clamp (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: line length style fixes
Iago Toral Quiroga [Wed, 7 Aug 2019 06:32:58 +0000 (08:32 +0200)]
v3d: line length style fixes

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: honor the write mask on store operations
Iago Toral Quiroga [Wed, 7 Aug 2019 06:20:35 +0000 (08:20 +0200)]
v3d: honor the write mask on store operations

v2:
  - Fix incremental update of the const offset when we need to emit a sequence
    with more than one write because of the writemask.
  - Do not move the tmu write emission to a separate helper.

v3:
  - Get the store writemask before the loop, use ffs to get the first component
    to write and clear writemask bits as we process the components (Eric).
  - Simplified the code that figured out the number of components for the TMU
    config based on the number of tmu writes for stores and atomics.

v4:
  - Code clean-ups (Eric).

Fixes:
KHR-GLES31.core.shader_image_load_store.advanced-cast-cs
KHR-GLES31.core.shader_image_load_store.advanced-cast-fs
KHR-GLES31.core.shader_storage_buffer_object.advanced-switchBuffers-cs
KHR-GLES31.core.shader_storage_buffer_object.advanced-switchPrograms-cs
KHR-GLES31.core.shader_storage_buffer_object.basic-operations-case1-cs

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: refactor ntq_emit_tmu_general() slightly
Iago Toral Quiroga [Tue, 6 Aug 2019 10:18:17 +0000 (12:18 +0200)]
v3d: refactor ntq_emit_tmu_general() slightly

When we implement write masks on store operations we might need to
emit multiple write sequences for a given store intrinsic. To make
that easier, let's split the emission of the tmud instructions to
their own block after we are done with the code that only needs to
run once no matter how many write sequences we need to emit.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: do not automatically flush current job for SSBOs and shader images
Iago Toral Quiroga [Mon, 12 Aug 2019 06:36:37 +0000 (08:36 +0200)]
v3d: do not automatically flush current job for SSBOs and shader images

If the current job has a sequence of draw calls involving SSBOs and/or
shader images, we would flush the job in between each draw call.
With this change, we won't flush the current job and we rely on the
application inserting correct barriers by issuing glMemoryBarrier()
when needed.

v2 (Eric):
 - When mapping a buffer for writing, we always need to flush.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: only process glMemoryBarrier() for SSBOs and images
Iago Toral Quiroga [Thu, 8 Aug 2019 10:46:43 +0000 (12:46 +0200)]
v3d: only process glMemoryBarrier() for SSBOs and images

PIPE_BARRIER_UPDATE is defined as:
PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE

Which means we were flushing for any flags other than these two, but
this was intended to only flush for ssbos and images.

Actually, the driver automatically flushes jobs as we need, including
writes/reads involving SSBOs and images, so we don't really need to
flush anything when the program emits a barrier. However, this may
lead to excessive flushing in some cases, so we will soon change this
to avoid atutomatic flushing of the current job for SSBOs and images,
meaning that we will rely on the application to emit correct memory
barriers for these that we should make sure to process here.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: fix flushing of SSBOs and shader images
Iago Toral Quiroga [Fri, 9 Aug 2019 11:02:32 +0000 (13:02 +0200)]
v3d: fix flushing of SSBOs and shader images

If the current draw call includes SSBOs, then we must flush any jobs
that are writing to the same SSBOs (so that our SSBOs reads are correct),
as well as jobs reading from the same SSBO (so that our SSBO writes don't
stomp previous SSBO reads).

The exact same logic applies to shader images. In this case we were already
flushing previous writes, but we should also flush previous reads.

Note that We don't need to call v3d_flush_jobs_reading_resource() and
v3d_flush_jobs_writing_resource() separately though, since flushing
jobs that read a resource also flushes those writing to it.

Suggested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agointel/tools: Fix aub_file initialization in intel_dump_gpu
Caio Marcelo de Oliveira Filho [Mon, 12 Aug 2019 19:55:37 +0000 (12:55 -0700)]
intel/tools: Fix aub_file initialization in intel_dump_gpu

The `device` can be set earlier either by a command line or a by
intercepting an ioctl call to get the I915_PARAM_CHIPSET_ID done by
the application early.  In both cases `aub_file` and `devinfo` would
not be initialized.

Fix by splitting the conditions

- `device == 0`: use the FD to get both device and devinfo.
- Or `devinfo.gen == 0`: use `device` to initialize it.

And separatedly, initialize aub_file the first time it is needed.

Fixes: d594d2a0524 ("intel/tools: use device info initializer")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoi965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli [Mon, 22 Jul 2019 22:49:24 +0000 (15:49 -0700)]
i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.

If the pixel pipes have a different number of subslices, emit a slice
hashing table that will ensure proper workload distribution.

v2: Set Mask field to 0xffff for workaround (Ken).

2 years agoanv/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli [Mon, 22 Jul 2019 17:56:53 +0000 (10:56 -0700)]
anv/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.

If the pixel pipes have a different number of subslices, emit a slice
hashing table that will ensure proper workload distribution.

v2: Don't need to set the mask - it's mbo (Ken).

2 years agoiris/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli [Fri, 19 Jul 2019 22:29:00 +0000 (15:29 -0700)]
iris/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.

If the pixel pipes have a different number of subslices, emit a slice
hashing table that will ensure proper workload distribution.

v2: Don't need to set the mask - it's mbo (Ken).
v3: Don't keep a reference to the resource used for emitting the table
(Ken).

2 years agointel: Get information about pixel pipes subslices.
Rafael Antognolli [Mon, 1 Jul 2019 20:34:08 +0000 (13:34 -0700)]
intel: Get information about pixel pipes subslices.

v2: Use 1 instead of 1UL (Ken).

2 years agointel/gen_decoder: Decode SLICE_HASH_TABLE.
Rafael Antognolli [Fri, 19 Jul 2019 22:30:56 +0000 (15:30 -0700)]
intel/gen_decoder: Decode SLICE_HASH_TABLE.

2 years agointel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.
Rafael Antognolli [Fri, 19 Jul 2019 20:37:25 +0000 (13:37 -0700)]
intel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.

Add these fields and the 3DSTATE_SLICE_TABLE_STATE_POINTERS instruction
so we can properly configure the slice and subslice hashing on ICL+

v2: Make 'Mask' field a mbo (Ken).

2 years agoanv: Implement VK_KHR_pipeline_executable_properties
Jason Ekstrand [Wed, 24 Apr 2019 08:02:35 +0000 (03:02 -0500)]
anv: Implement VK_KHR_pipeline_executable_properties

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: Add a ralloc context to anv_pipeline
Jason Ekstrand [Wed, 24 Apr 2019 07:21:01 +0000 (02:21 -0500)]
anv: Add a ralloc context to anv_pipeline

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: Force a full re-compile when CAPTURE_INTERNAL_REPRESENTATION_TEXT is set
Jason Ekstrand [Thu, 25 Apr 2019 00:56:39 +0000 (19:56 -0500)]
anv: Force a full re-compile when CAPTURE_INTERNAL_REPRESENTATION_TEXT is set

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv/pipeline: Split setting up per-stage keys into its own loop
Jason Ekstrand [Thu, 25 Apr 2019 00:54:14 +0000 (19:54 -0500)]
anv/pipeline: Split setting up per-stage keys into its own loop

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: Record shader compile stats in the pipeline cache
Jason Ekstrand [Wed, 24 Apr 2019 07:00:25 +0000 (02:00 -0500)]
anv: Record shader compile stats in the pipeline cache

We're going to want these to be available regardless of caching.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv/pipeline: Stash generated code in the pipeline stage
Jason Ekstrand [Wed, 24 Apr 2019 08:19:25 +0000 (03:19 -0500)]
anv/pipeline: Stash generated code in the pipeline stage

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/fs: Add SLM size to brw_cs_prog_data
Jason Ekstrand [Thu, 25 Jul 2019 17:00:23 +0000 (12:00 -0500)]
intel/fs: Add SLM size to brw_cs_prog_data

We don't need it for state setup but it's a useful statistic we want to
pass on to developers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/compiler: Fill a compiler statistics struct
Jason Ekstrand [Wed, 24 Apr 2019 04:19:56 +0000 (23:19 -0500)]
intel/compiler: Fill a compiler statistics struct

This commit is all annoying plumbing work which just adds support for a
new brw_compile_stats struct.  This struct provides a binary driver
readable form of the same statistics we dump out to stderr when we
INTEL_DEBUG is set with a shader stage.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agofreedreno: disable tiling for cubemaps
Khaled Emara [Sun, 4 Aug 2019 15:51:24 +0000 (17:51 +0200)]
freedreno: disable tiling for cubemaps

Tiling doesn't work quite well with cubemaps.
Revert to linear textures, until it's fixed.

2 years agofreedreno: add tiling parameters for 2D/2DArray/3D
Khaled Emara [Sat, 3 Aug 2019 12:59:18 +0000 (14:59 +0200)]
freedreno: add tiling parameters for 2D/2DArray/3D

2 years agofreedreno: simplified slices setup for a3xx
Khaled Emara [Sat, 3 Aug 2019 12:30:53 +0000 (14:30 +0200)]
freedreno: simplified slices setup for a3xx

a3xx doesn't support ASTC and layout_first always returns false

2 years agofreedreno: enable tiled textures for debug builds
Khaled Emara [Sat, 3 Aug 2019 12:29:43 +0000 (14:29 +0200)]
freedreno: enable tiled textures for debug builds

2 years agointel/fs: add 64 bit integer multiplication lowering
Paulo Zanoni [Thu, 11 Jul 2019 22:08:03 +0000 (15:08 -0700)]
intel/fs: add 64 bit integer multiplication lowering

While NIR's lower_imul64() solves the case of 64 bit integer multiplications
generated early, we don't have a way to lower such instructions when they are
generated by our own backend, such as the scan/reduce intrinsics. We'll need
this soon, so implement it now.

An easy way to test this is to simply disable nir_lower_imul64 to let
those operations reach the backend.

v2:
  - Fix Q/UQ copy/paste errors (Caio).
  - Transform an 'if' into 'else if' (Caio).
  - Add an extra comment to clarify the need for 64b = 32b * 32b
    (Caio).
  - Make private functions private (Caio).
v3:
  - Remove ambiguity with 'b' and 'd' variables (Caio).
  - Allocate potentially less regs for the dwords (Caio).

Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Matt Turner <matt.turner@intel.com>
Cc: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2 years agointel/compiler: invert the logic of lower_integer_multiplication()
Paulo Zanoni [Thu, 11 Jul 2019 00:03:48 +0000 (17:03 -0700)]
intel/compiler: invert the logic of lower_integer_multiplication()

Invert the logic of how progress is handled: remove the continue
statements and mark progress inside the places where it actually
happens.

We're going to add a new lowering that also looks for BRW_OPCODE_MUL,
so inverting the logic here makes the resulting code much easier to
follow.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>