mesa: Add missing include guards

Signed-off-by: Michał Janiszewski <janisozaur+signed@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: Add missing include guards

Signed-off-by: Michał Janiszewski <janisozaur+signed@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

svga: Add missing include guards

Signed-off-by: Michał Janiszewski <janisozaur+signed@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: Add missing include guards

Signed-off-by: Michał Janiszewski <janisozaur+signed@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

intel/batch-decoder: remove never-used function

This function was there when the file was introduced in commit
38f10d5a03542c60a589 "intel: tools: add aubinator viewer", but was
never actually used.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

st/dri: remove leftover local variable

Left over from the cleanup in 6ccc435e7ad92bb0ba77d "pipe-loader: move dup(fd)
within pipe_loader_drm_probe_fd"

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

glsl/linker: Fix out variables linking during single stage

Since out variables are copied from shader objects instruction
streams to linked shader instruction steam it should be cloned
at first to keep source instruction steam unaltered.

Fixes: 966a797e433 ("glsl/linker: Link all out vars from a shader
objects on a single stage")

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105731

ac: fix ac_build_fdiv for f64

trivial

Fixes: a5f35aa742c

nir: fix yet another MSVC build break

Trivial.

vulkan/wsi: simplify meson file tracking

Meson already automatically tracks included headers, so there's no need
to add them everywhere; cleans up the code a bit.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

clover: add missing meson build dependency

Fixes: 42ea0631f108d82554339 "meson: build clover"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

svga: add missing meson build dependency

Fixes: a537231b226280bc1e5b7 "meson: build svga driver on linux"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

radv: add missing meson build dependency

Fixes: 9d40ec2cf6ec6d3d9d78 "radv: Add support for VK_KHR_driver_properties."
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

anv: add missing meson build dependency

Fixes: e4538b93f5d5177318f2 "anv: Implement VK_KHR_driver_properties"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

radv: implement VK_EXT_transform_feedback

This implementation should work and potential bugs can be
fixed during the release candidates window anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: add multiple streams support for the GS copy shader

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: emit stream outputs for vertex and tessellation stages

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: declare streamout SGPRs

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: gather stream output info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: allow to emit a vertex to a specified stream

This is required for GS multiple streams support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: allow to use up to 4 GSVS ring buffers

For all streams. We basically just need to update the
base address and compute a stride for every stream.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: adjust the number of output components per stream

Same as the previous patch, except that is only the number of
components.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: adjust the GSVS ring sizes based on the number of components

For multiple streams support we have to set the different ring
buffer sizes correctly. This relies on the number of output
components per stream.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: gather which GS stream is used for every outputs

To only emit outputs for the given stream.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: gather the number of output components per stream

This will be also used for splitting the GS->VS ring buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: gather the number of streams used by geometry shaders

This will be used for splitting the GS->VS ring buffer. The
stream ID is always 0 for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

nir: Add a pass for gathering transform feedback info

This is different from the GL_ARB_spirv pass because it generates a much
simpler data structure that isn't tied to OpenGL and mtypes.h.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

vulkan: Update the XML and headers to 1.1.90

This doesn't include any new features but it does include an XML and
header typo fix for modifiers.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: remove wrong comment in calculate_gs_ring_sizes() about streams

The computation seems correct compared to RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

freedreno: don't flush when new and old pfb is identical

In the 'inorder' case (ie. FD_MESA_DEBUG=inorder, or old kernel), if the
u_blitter clear path is used (a3xx, a4xx, and some fallback cases on
newer gens), util_blitter_restore_fb_state() will set_framebuffer_state()
to something that is identical to the current fb state, which triggers
an unnecessary flush, and then eventually an assert:

  (gdb) bt
  #0  0x0000007fbf24a078 in kill () from /lib64/libc.so.6
  #1  0x0000007fbe061278 in _debug_assert_fail (expr=0x7fbe93a820 "!batch->flushed", file=0x7fbe93a628 "../src/gallium/drivers/freedreno/freedreno_batch.c", line=491, function=0x7fbe93a990 <__func__.17380> "fd_batch_check_size") at ../src/gallium/auxiliary/util/u_debug.c:322
  #2  0x0000007fbe1ccb8c in fd_batch_check_size (batch=0x55556d5a70) at ../src/gallium/drivers/freedreno/freedreno_batch.c:491
  #3  0x0000007fbe1d0e08 in fd_clear (pctx=0x55555c61e0, buffers=5, color=0x55556e388c, depth=1, stencil=0) at ../src/gallium/drivers/freedreno/freedreno_draw.c:463
  #4  0x0000007fbe57afa4 in st_Clear (ctx=0x55556e17b0, mask=18) at ../src/mesa/state_tracker/st_cb_clear.c:452

The assert was introduced in 4b847b38ae3, so from a functionality
standpoint this patch fixes that commit.  But it should also avoid an
unnecessary flush in the 'inorder' case, fixing a performance bug.

Fixes: 4b847b38ae3 freedreno: make fd_batch a one-shot thing
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: dependency tracking for z/s depends on ZSA state

ZSA state can change whether depth or stencil is enabled

This plus previous patch fix stk, and various things w/
FD_MESA_DEBUG=inorder

Fixes: ec717fc629 freedreno: reduce resource dependency tracking overhead
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: mark all state dirty after switching batch

The problem isn't directly with ec717fc629 but rather that commit
exposes the problem.  When we switch batch we cannot assume previous
state is clean so we should mark all state dirty.

Fixes: ec717fc629 freedreno: reduce resource dependency tracking overhead
Signed-off-by: Rob Clark <robdclark@gmail.com>

anv: Use absolute timeouts in wait_for_bo_fences

We were previously using relative timeouts and decrementing the
user-provided timeout as we waited.  Instead, this commit refactors
things to use absolute timeouts throughout.  This should fix a subtle
bug in the waitAll case where we aren't decrementing the timeout after a
successful GPU wait.  Since pthread_cond_timedwait already takes an
absolute timeout, it's also significantly simpler.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Flag semaphore BOs as external

It probably doesn't actually break anything but it does cause some
assertions in debug builds.

Fixes: 7a89a0d9edae6 "anv: Use separate MOCS settings for external BOs"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Improve the asserts in anv_buffer_get_range

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

freedreno/a6xx: inline draw_impl()

Now that it is just called once per draw (instead of once for binning
and once for draw), let's just inline it.  If nothing else, it makes
perf-annotate easier to look at.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: small cleanup

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: move where we handle dirty vbo state

Historically this wasn't in fdN_emit_state(), because prior to addition
of blitter in a5xx, fdN_emit_state() was also used in the clear path.
These days that is only true for a2xx (a3xx and a4xx use u_blitter).  So
the reason for it not to be in fd6_emit_state() no longer exists.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: avoid no-op flushes by re-using last-fence

Noticed that with webgl (in chromium, at least) we end up generating a
lot of no-op submits just to get a fence.  Tracking the last fence and
returning that if there is no rendering since last flush avoids this.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: Move stencil/depth/alpha state to IB

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/a6xx: Move stencil mask emit to FD_DIRTY_ZSA group

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/a6xx: Rename FD6_GROUP_ZSA ro FD6_GROUP_LRZ

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/a6xx: Move rasterizer state to state object

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/a6xx: Fix set_blit_scissor helper

The scissor maxx/maxy are non-inclusive, so don't subtract one from
framebuffer width and height.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/a2xx: Squash a compiler warning

We get a warning here for assigning a const char * pointer to
char *swizzle in struct ir2_src_register.  The constructor strdups a 4
byte string here, so just memcpy to that instead.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/a6xx: Use fd6_emit_ib from a6xx

Move it to a header and use it where possible to avoid vfunc call.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno: import libdrm_freedreno + redesign submit

In the pursuit of lowering driver overhead, it became clear that some
amount of redesign of how libdrm_freedreno constructs the submit ioctl
would be needed.  In particular, as the gallium driver is starting to
make heavier use of CP_SET_DRAW_STATE state groups/objects, the over-
head of tracking cmd buffers and relocs becomes too much.  And for
"streaming" state, which isn't ever reused (like uniform uploads) the
overhead of allocating/freeing ringbuffer[1] objects is too high.

This redesign makes two main changes:

 1) Introduces a fd_submit object for tracking bos and cmds table
    for the submit ioctl, making ringbuffer objects more light-
    weight.  This was previously done in the ringbuffer.  But we
    have many ringbuffer instances involved in a submit (gmem +
    draw + potentially 1000's of state-group rbs), and only need
    a single bos and cmds table.  (Reloc table is still per-rb)

    The submit is also a convenient place for a slab allocator for
    ringbuffer objects.  Other options would have required locking
    because, while we can guarantee allocations will only happen on
    a single thread, free's could happen either on the application
    thread or the flush_queue thread.  With the slab allocator in
    the submit object, any frees that happen on the flush_queue
    thread happen after we know that the application thread is done
    with the submit.

 2) Introduce a new "softpin" msm_ringbuffer_sp implementation that
    does not use relocs and only has cmds table entries for IB1 (ie.
    the cmdstream buffers that kernel needs to CP_INDIRECT_BUFFER
    to from the RB).  To do this properly will require some updates
    on the kernel side, so whether you get the softpin or legacy
    submit/ringbuffer implementation at runtime depends on your
    kernel version.

To make all these changes in libdrm would basically require adding a
libdrm_freedreno2, so this is a good point to just pull the libdrm code
into mesa.  Plus it allows for using mesa's hashtable, slab allocator,
etc.  And it lets us have asserts enabled for debug mesa buids but
omitted for release builds.  And it makes life easier if further API
changes become necessary.

At this point I haven't tried to pull in the kgsl backend.  Although
I left the level of vfunc indirection which would make it possible
to have other backends.  (And this was convenient to keep to allow
for the "softpin" ringbuffer to coexist.)

NOTE: if bisecting a build error takes you here, try a clean build.
There are a bunch of ways things can go wrong if you still have
libdrm_freedreno cflags.

[1] "ringbuffer" is probably a bad name, the only level of cmdstream
    buffer that is actually a ring is RB managed by kernel.  User-
    space cmdstream is all IB1/IB2 and state-groups.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>

Revert "anv/skylake: disable ForceThreadDispatchEnable"

This reverts commit 0fa9e6d7b304f6a8064ed78a4b9c557e1026e7e5.  The real
issue appears to have been that HiZ ops don't like having WM thread
dispatch force-enabled.  The previous commit fixes that problem so we
can go back to using the ForceThreadDispatchEnable bit even on SKL+.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP

Cc: mesa-stable@lists.freedesktop.org
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/nine: Handle window resize when a presentation buffer is used

Usually when a window is resized, the app calls d3d to resize the back
buffer to the window size. In some cases, it is not done,
and it expects the output resizes to the window size, even if
the back buffer size is unchanged.

This patch introduces the behaviour when a presentation buffer
is used.

ID3DPresent_GetWindowInfo is a function available with
D3DPresent v1.0, and thus we don't need to check if the
function is available.
The function had been introduced to implement this very
feature.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

d3dadapter: Fix wrong naming in header file

GetWindowInfo used to be GetWindowSize before gallium
nine was merged. A left-over remained...

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Reduce MaxSimultaneousTextures to 8

Windows drivers don't set this flag (which affects ff) to more than 8.

Do the same in case some games check for 8.

v2: Remove any dependence on MaxSimultaneousTextures. For non-ff
the number of textures is 16 when the device is able of vs/ps3.
Add this requirement of 16 textures to the driver requirements.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Enable shadow mapping for ps 1.X

We didn't implement shadow textures for ps 1.X,
assuming the case couldn't happen...
Well it does.

Fixes: https://github.com/iXit/Mesa-3D/issues/261
Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Do not set unused states for stateblocks

A lot of these states are used only for the context,
and are unused for stateblocks (which just uses the
changed.* fields instead for a lot of them).

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Fix aliasing states for stateblocks

If NINE_STATE_FF_MATERIAL is set, the stateblock will upload
its recorded materials matrix.
If NINE_STATE_FF_LIGHTING is set, the lighting set is uploaded.

These flags could be set by a NineDevice9_SetTransform call
or by setting some states related to ff, but that shouldn't trigger
these stateblock behaviours.

We don't need to follow the context states dirtied by render states.
NINE_STATE_FF_VSTRANSF is exactly the state controlling stateblock
updates of transformation matrices, NINE_STATE_FF is too broad.

These two changes avoid setting the two mentionned states when we
shouldn't.

Fixes: https://github.com/iXit/Mesa-3D/issues/320
Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Never update device changed.* fields

The device state changed.* field are never used.
These fields are used only for stateblocks.

Avoid setting them at all for clarity.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Capture also default matrices for D3DSBT_ALL

We avoid allocating space for never unused matrices.
However we must do as if we had captured them.
Thus when a D3DSBT_ALL stateblock apply has fewer matrices
than device state, allocate the default matrices for the stateblock
before applying.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Mark transform matrices dirty for D3DSBT_ALL

D3DSBT_ALL stateblocks capture the transform matrices.

Fixes some d3d test programs not displaying properly.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Don't update unused world matrices

While to the application we have to track
accurately all 256 world matrices (including
in stateblocks), hw vertex processing enables
to set a limit to the number of world matrices
the hardware can access to in the advertised caps,
which is 8 for nine.

Thus don't bother in the stateblock code to send
the updated values for the unreachable matrices.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Remove two unused states.

NINE_STATE_MATERIAL was used incorrectly at one location.
Replace it with the correct state.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

st/nine: Remove commented nine_context_apply_stateblock

At some point the project was to adapt the
commented version to csmt.

The csmt rework enabled to fix some state aliasing
issues between stateblocks and internal state updates.
The commented version needs a lot of work to work with that.
Just drop it.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>

nir: Fix array initializer

Empty initializer is not standard C.  This fixes MSVC build.

Trivial.

anv: Return VK_ERROR_DEVICE_LOST from anv_device_set_lost

This lets us get rid of a bunch of duplicated error messages.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

anv/util: Split a vk_errorv helper out of vk_errorf

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

scons/svga: remove opt from the list of valid build types

This reverts commit a5fd54f8bf6713312fa5efd7ef5cd125557a0ffe.

The whole point was to add a way to pass -DVMX86_STATS to the build,
but we can do that with a command line argument when we invoke scons.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

intel/blorp: Define the clear value bounds for HiZ clears

Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:

./bin/depthstencil-render-miplevels 146 d=z32f_s8

Jason found this to fix incorrect clearing on SKL.

Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b
       ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>

radv: remove duplicate brackets in version string

MESA_GIT_SHA1 resolves to either an empty "" string if not build from git,
or " (git-DEADBEEF)" if it is. No need to wrap it in additional "()".

Fixes: 9d40ec2cf6ec6d3d9d78 "radv: Add support for VK_KHR_driver_properties."
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

vulkan: drop always-true param

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeon/vcn: use util function to get h264 profile idc

Use utility function for converting h264 pipe video profile to profile idc,
instead of using array.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig at amd.com>

radeon/vce: use util function to get h264 profile idc

Use utility function for converting h264 pipe video profile to profile idc,
instead of using array.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig at amd.com>

vl: get h264 profile idc

Adding a function for converting h264 pipe video profile to profile idc

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig at amd.com>

intel/nir: Use the OPT macro for more passes

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

spirv: Initialize subgroup destinations with the destination type

Instead of initializing them manually, just use the type that we already
have sitting there.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

spirv: Use the right bit-size for spec constant ops

Previously, we would always pull the bit size from the destination which
is wrong for opcodes like nir_ilt where the sources are variable-sized
but the destination is a fixed size.  We were getting lucky before
because nir_op_ilt returns a 32-bit value and basically everyone who
uses spec constants uses 32-bit ones.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nir/prog: Use nir_bany in kill handling

We have a helper that does exactly what the bany_inequal was doing.  It
emits the same code but is a bit higher level and is designed to operate
on a bvec4.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl/nir: Use i2b instead of ine for fixing UBO/SSBO Booleans

They do the same thing in the end but i2b is a bit simpler.  Also, let's
clean up the mess of code for SSBO handling with one line of builder.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/system_values: Use the bit size from the load_deref

This isn't a great solution for bit-sizes but we don't have a
particularly convenient way to get a bit size from the system value enum
and this keeps the lowering pass from changing it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/opt_if: Rework condition propagation

Instead of doing our own constant folding, we just emit instructions and
let constant folding happen.  This is substantially simpler and lets us
use the nir_imm_bool helper instead of dealing with the const_value's
ourselves.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

nir/search: Use the nir_imm_* helpers from nir_builder

This requires that we rework the interface a bit to use nir_builder but
that's a nice little modernization anyway.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/builder: Handle 16-bit floats in nir_imm_floatN_t

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/builder: Add a nir_imm_true/false helpers

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/constant_folding: Use nir_src_as_bool for discard_if

Missed one while converting to the nir_src_as_* helpers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/constant_folding: Add an unreachable to a switch

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir/validate: Print when the validation failed

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

anv: Handle the device loss abort in anv_device_set_lost

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

anv: Add helpers for setting/checking device lost

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

anv: Provide a error message with a DEVICE_LOST

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

anv: Fix sanitization of stencil state when the depth test is disabled

When depth testing is disabled, we shouldn't pay attention to the
specified depthCompareOp, and just treat it as always passing. Before,
if the depth test is disabled, but depthCompareOp is VK_COMPARE_OP_NEVER
(e.g. from the app having zero-initialized the structure), then
sanitize_stencil_face() would have incorrectly changed passOp to
VK_STENCIL_OP_KEEP.

v2: Roll the depthTestEnable check into the ds_aspect check below since
    they now both do the same thing.

Fixes: 028e1137e6 "anv/pipeline: Be smarter about depth/stencil state"
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radv: implement image to image operations for R32G32B32

This should address the remaining failures in Batman Arkhman City.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107765
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix a comment in radv_meta_buffer_to_image_cs_r32g32b32()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add get_image_stride_for_r32g32b32() helper

For the special R32G32B32 paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add create_bview_for_r32g32b32() helper

For the special R32G32B32 paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add create_buffer_from_image() helper

For the special R32G32B32 paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

intel/compiler: Print message descriptor as immediate source

While disassembling send(c) instruction print message descriptor as
immediate source operand along with message descriptor. This allows
assembler to read immediate source operand and set bits accordingly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

intel/compiler: Print hex representation along with floating point value

While encoding the immediate floating point values in instruction we use
values upto precision 9, but while disassembling, we print precision to
6 places, which round up the value and gives wrong interpretation for
encoded immediate constant.

To avoid misinterpretation of encoded immediate values in instruction
and disassembled output, print hex representation along with floating
point value which can be used by assembler in future.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

util: Change remaining uint32 cache ids to sha1

After discussion with Timothy Arceri. disk_cache_get_function_identifier
was using only the first byte of the sha1 build-id.  Replace
disk_cache_get_function_identifier with implementation from
radv_get_build_id.  Instead of writing a uint32_t it now writes to a
mesa_sha1.  All drivers using disk_cache_get_function_identifier are
updated accordingly.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")

freedreno: use fd_bc_alloc_batch instead of fd_batch_create.

Following the commit 2385d7b066 and 8e798e28f7, for resource dependancy
tracking.

Fixes: dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
with FD_MESA_DEBUG=inorder

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: take reg->num out of union in ir3_register

To avoid wrong result when identifying the type of register.
Ie. If the reg is an array, it might be identified as address or
predicate register.

Fixes: dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: disable unused groups

Don't leave vsconst/fsconst group enabled if we switch to shader with no
uniforms.

Fixes: abcdf5627a2 freedreno/a6xx: move const emit to state group
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add useful assert

Would have been useful to catch the problem fixed in
8e798e28f736e22e9e1e4534ab42a36cde14b142

Signed-off-by: Rob Clark <robdclark@gmail.com>