mesa.git
19 months agopan/bi: Add bi_layout.c for clause layout helpers
Alyssa Rosenzweig [Tue, 5 May 2020 21:58:16 +0000 (17:58 -0400)]
pan/bi: Add bi_layout.c for clause layout helpers

Figuring out what "shapes" of clauses are kosher happens during
scheduling, not packing, but shouldn't distract the scheduler. So let's
add a new file for these sorts of questions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Remove more artefacts of 2-pass scheduling
Alyssa Rosenzweig [Tue, 5 May 2020 21:29:24 +0000 (17:29 -0400)]
pan/bi: Remove more artefacts of 2-pass scheduling

A clause is, by definition, already scheduled.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Add MUL.i32 to disasm
Alyssa Rosenzweig [Tue, 5 May 2020 20:15:44 +0000 (16:15 -0400)]
pan/bi: Add MUL.i32 to disasm

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Disassemble pos=0xe
Alyssa Rosenzweig [Tue, 5 May 2020 20:15:36 +0000 (16:15 -0400)]
pan/bi: Disassemble pos=0xe

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Document constant count invariant
Alyssa Rosenzweig [Tue, 5 May 2020 20:15:16 +0000 (16:15 -0400)]
pan/bi: Document constant count invariant

   constants + instructions <= 13

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Move bi_flip_ports out of port assignment
Alyssa Rosenzweig [Tue, 5 May 2020 18:34:58 +0000 (14:34 -0400)]
pan/bi: Move bi_flip_ports out of port assignment

It's more of a packing fixup than anything scheduler-y, and port
assignment will soon be the domain of the scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Add FILE* argument to bi_print_registers
Alyssa Rosenzweig [Tue, 5 May 2020 18:31:20 +0000 (14:31 -0400)]
pan/bi: Add FILE* argument to bi_print_registers

In case we need it in general IR printing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Drop `struct` from bi_registers
Alyssa Rosenzweig [Tue, 5 May 2020 18:30:06 +0000 (14:30 -0400)]
pan/bi: Drop `struct` from bi_registers

It's a full-fledged part of the IR now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Move bi_registers to bi_bundle
Alyssa Rosenzweig [Tue, 5 May 2020 18:28:53 +0000 (14:28 -0400)]
pan/bi: Move bi_registers to bi_bundle

Make it a part of the IR itself.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Move bi_registers to common IR structures
Alyssa Rosenzweig [Tue, 5 May 2020 18:23:41 +0000 (14:23 -0400)]
pan/bi: Move bi_registers to common IR structures

Port assignments are critical to scheduling, this can't just live in
bi_pack.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Remove comment about old scheduler design
Alyssa Rosenzweig [Tue, 5 May 2020 18:17:58 +0000 (14:17 -0400)]
pan/bi: Remove comment about old scheduler design

I've realized it really has to be 1-pass to be sane.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopan/bi: Remove FMA? parameter from get_src
Alyssa Rosenzweig [Mon, 4 May 2020 23:46:32 +0000 (19:46 -0400)]
pan/bi: Remove FMA? parameter from get_src

We can lower away zeroes a bit earlier.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>

19 months agopanfrost: Preload gl_FragCoord on Bifrost
Alyssa Rosenzweig [Fri, 29 May 2020 20:06:39 +0000 (16:06 -0400)]
panfrost: Preload gl_FragCoord on Bifrost

It's a precoloured register but we do need to specify in the cmdstream
that we want the preloading to happen.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>

19 months agopanfrost: Set reads_frag_coord as a sysval
Alyssa Rosenzweig [Fri, 29 May 2020 20:06:10 +0000 (16:06 -0400)]
panfrost: Set reads_frag_coord as a sysval

In addition to parsing out the varying. This is needed so it works on
Bifrost as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>

19 months agopanfrost: Don't generate gl_FragCoord varying on Bifrost
Alyssa Rosenzweig [Fri, 29 May 2020 20:05:22 +0000 (16:05 -0400)]
panfrost: Don't generate gl_FragCoord varying on Bifrost

It's treated as a sysval there, so that's silly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>

19 months agofreedreno/a6xx: fix vsc assert
Rob Clark [Mon, 18 May 2020 21:14:51 +0000 (14:14 -0700)]
freedreno/a6xx: fix vsc assert

Fixes a debug build assert seeing with an android app.  Not quite sure
which path was passing us draw_info w/ instance_count==0.  But we should
just treat non-instanced draws as having a single instance.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5091>

19 months agofreedreno/a6xx: Program VFD_DEST_CNTL from program stateobj
Kristian H. Kristensen [Thu, 21 May 2020 08:26:02 +0000 (01:26 -0700)]
freedreno/a6xx: Program VFD_DEST_CNTL from program stateobj

This only depends on the generated shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>

19 months agofreedreno/a6xx: Create stateobj for VFD_DECODE
Kristian H. Kristensen [Thu, 21 May 2020 08:38:44 +0000 (01:38 -0700)]
freedreno/a6xx: Create stateobj for VFD_DECODE

This now only depends on vertex state and we can create it once
up front in pctx->create_vertex_elements_state().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>

19 months agofreedreno/a6xx: Decouple VFD_FETCH and VFD_DECODE
Kristian H. Kristensen [Thu, 21 May 2020 05:50:20 +0000 (22:50 -0700)]
freedreno/a6xx: Decouple VFD_FETCH and VFD_DECODE

We used to output a VFD_FETCH entry for each VFD_DECODE, but we can
instead output just one VFD_FETCH per VBO and point multiple
VFD_DECODE entries at the same VFD_FETCH entry.  There's typically
fewer VBOs than vertex elements so this is a small win in itselfs, but
more importantly, the VFD_DECODE state now only depends on program
state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>

19 months agofreedreno/a6xx: Move per element offset to VFD_DECODE
Kristian H. Kristensen [Thu, 21 May 2020 05:34:59 +0000 (22:34 -0700)]
freedreno/a6xx: Move per element offset to VFD_DECODE

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>

19 months agoci: Rename x86_cross_arm_test to just arm_test.
Eric Anholt [Sat, 23 May 2020 03:00:07 +0000 (20:00 -0700)]
ci: Rename x86_cross_arm_test to just arm_test.

This gets us back to the behavior we used to have for freedreno: clicking
play on arm_test gets you testing of the ARM platforms that aren't under
arm-build (the LAVA runners).

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>

19 months agoci: Don't build an arm_test container now that the last user is gone.
Eric Anholt [Sat, 23 May 2020 02:58:50 +0000 (19:58 -0700)]
ci: Don't build an arm_test container now that the last user is gone.

db410c and cheza used to use it, and now both are on baremetal.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>

19 months agoci: Switch cheza (freedreno a630) testing to baremetal.
Eric Anholt [Fri, 15 May 2020 18:22:37 +0000 (11:22 -0700)]
ci: Switch cheza (freedreno a630) testing to baremetal.

Now that we have scripts in place to do baremetal testing of cheza, switch
it over.  As of this writing, we have 5 chezas for baremetal and 4 for the
old docker CI setup (just 2 fewer than we originally had before this work,
since some had had filesystem failures and I switched those first), and
once we are sure of this we can backport to stable branch CI and move the
rest of them to baremetal.

I've run a lot of jobs through the baremetal scripts as I worked on
sorting out vulkan CTS stability, so I feel good about the stability of
the GLES CTS here.

The options job is now split out to separate jobs, as we don't currently
have a way to stack multiple sets deqp runs with different env vars in a
single baremetal run, and just chaining cros_servo.sh invocations runs
into a lack of cleanup of the serial-watching scripts which we rely on
container exit sorting out for us.  This means a little less than 2x the
artifacts downloads we had before for a630 and a few more container
instantiations.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>

19 months agoci: Add scripts for controlling bare-metal chezas.
Eric Anholt [Fri, 15 May 2020 16:57:25 +0000 (09:57 -0700)]
ci: Add scripts for controlling bare-metal chezas.

This will let us:

- deploy kernels for testing code depending on new kernel featuers
- Ensure a pristine state in the HW before starting our tests
- Avoid disk rot on the chezas taking them out (we'd lost 3/9 in a few
  months).

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>

19 months agoci: Build a cheza kernel.
Eric Anholt [Mon, 6 Apr 2020 22:55:30 +0000 (15:55 -0700)]
ci: Build a cheza kernel.

This is a set of kernel options I've come up with mostly cribbing from
chrome os's kernel config snippet.  We also build an lzma kernel, as
uncompressed kernel is big but lzma is the only compression supported by
the bootloader.  With that image, we have to pack it into a FIT formatted
image+dtb blob.

CONFIG_SUNRPC_DEBUG is added so that you can set "nfsrootdebug" to figure
out what's going wrong with your nfs mount (mine were "both the tcp and
nfsvers options were required, and don't try to use 'default' as the root
path to defer to DHCP's answer because otherwise you get
/tftpboot/default, just use an empty root path which doesn't prepend
/tftpboot.")

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>

19 months agoci: Disable the firmware loader user helper option in arm64 kernels.
Eric Anholt [Tue, 7 Apr 2020 00:00:14 +0000 (17:00 -0700)]
ci: Disable the firmware loader user helper option in arm64 kernels.

We won't have a user helper, so don't block for 60 seconds for it to show
up.  Speeds up debug of new kernel builds.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>

19 months agoradv/aco: enable VK_KHR_subgroup_extended_types on GFX8+
Samuel Pitoiset [Thu, 21 May 2020 15:14:12 +0000 (17:14 +0200)]
radv/aco: enable VK_KHR_subgroup_extended_types on GFX8+

Should be working now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

19 months agoaco: sign-extend input/indentity for 32-bit reduce ops on GFX10
Samuel Pitoiset [Thu, 28 May 2020 07:09:49 +0000 (09:09 +0200)]
aco: sign-extend input/indentity for 32-bit reduce ops on GFX10

Because some 16-bit instructions are already VOP3 on GFX10, we use
the 32-bit variants to remove the temporary VGPR and to use DDP with
the arithmetic instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

19 months agoaco: allow gfx10_wave64_bpermute with 8-bit/16-bit input
Samuel Pitoiset [Mon, 18 May 2020 15:01:46 +0000 (17:01 +0200)]
aco: allow gfx10_wave64_bpermute with 8-bit/16-bit input

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

19 months agoaco: allocate a temp VGPR for some 8-bit/16-bit reduction ops on GFX10
Samuel Pitoiset [Mon, 18 May 2020 15:03:21 +0000 (17:03 +0200)]
aco: allocate a temp VGPR for some 8-bit/16-bit reduction ops on GFX10

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

19 months agoaco: implement 8-bit/16-bit reductions on GFX10
Samuel Pitoiset [Mon, 18 May 2020 15:38:17 +0000 (17:38 +0200)]
aco: implement 8-bit/16-bit reductions on GFX10

Some 16-bit instructions are VOP3 on GFX10 and we have to emit a
32-bit DPP mov followed by the ALU instruction.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

19 months agoaco: fix register allocation for subdword instructions on GFX10
Samuel Pitoiset [Fri, 29 May 2020 08:02:39 +0000 (10:02 +0200)]
aco: fix register allocation for subdword instructions on GFX10

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

19 months agofrontend/dri: Implement mapping individual planes.
Bas Nieuwenhuizen [Mon, 25 May 2020 13:53:59 +0000 (15:53 +0200)]
frontend/dri: Implement mapping individual planes.

It is kinda surprising that

image2 = fromPlanar(image, 2, NULL)
mapImage(..., image2, ...)

does not map the third plane.

This implements that behavior in the case where the DRI frontend
lowers the multi-planar textures.

In the case it doesn't this would need driver support. AFAIU at
least etnaviv is impacted, and while it looks possible, I don't
have the etnaviv knowledge to implement it.

Instead of silently returning weird results (either always plane 0
or possibly something interleaved) this adds an error return on
mapping multi-planar textures otherwise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5200>

19 months agozink: Check fopen result.
Vinson Lee [Wed, 27 May 2020 23:19:25 +0000 (16:19 -0700)]
zink: Check fopen result.

Fix warning reported by Coverity.

Dereference null return value (NULL_RETURNS)
dereference: Dereferencing a pointer that might be NULL fp when calling
fwrite.

Fixes: 8d46e35d16e3 ("zink: introduce opengl over vulkan")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5235>

19 months agoradv/aco: enable VK_EXT_subgroup_size_control
Samuel Pitoiset [Wed, 20 May 2020 06:41:46 +0000 (08:41 +0200)]
radv/aco: enable VK_EXT_subgroup_size_control

ACO should already support Wave32 on GFX10 with all shader stages
and CTS pass. RADV currently only allows Wave32 with the compute
shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5056>

19 months agofreedreno/a6xx: document LRZ flag buffer
Rob Clark [Wed, 27 May 2020 20:50:05 +0000 (13:50 -0700)]
freedreno/a6xx: document LRZ flag buffer

Doesn't seem to be a big win, although I could still be missing
something in my implementation.  But might as well add the
documentation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>

19 months agofreedreno/a6xx: LRZ fix for alpha-test
Rob Clark [Tue, 26 May 2020 20:58:22 +0000 (13:58 -0700)]
freedreno/a6xx: LRZ fix for alpha-test

Similarly to stencil-test, if alpha-test is enabled, we don't know
necessarily whether the fragment will pass.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3045
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>

19 months agoutil: Initialize pipe_shader_state for passthrough and transform shaders
Neha Bhende [Wed, 27 May 2020 15:15:29 +0000 (20:45 +0530)]
util: Initialize pipe_shader_state for passthrough and transform shaders

mesa/st is initializing pipe_shader_state for user define shaders.
This patch intialized pipe_shader_state for all passthough
and transform shaders.

This fixes crashes for several opengl apps. Issue is found in vmware
internal testing

Fixes: f01c0565bb9 ("draw: free the NIR IR.")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5240>

19 months agoiris: Rename iris_seqno to iris_fine_fence
Chris Wilson [Wed, 27 May 2020 21:19:52 +0000 (22:19 +0100)]
iris: Rename iris_seqno to iris_fine_fence

Rename iris_seqno to iris_fine_fence, borrowed from si_fine_fence, to
avoid introducing any confusion with any other seqno used for tracking
pipelines.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5233>

19 months agonir: lower_tex: Don't normalize coordinates for TXF with RECT
Gert Wollny [Tue, 19 May 2020 15:52:31 +0000 (17:52 +0200)]
nir: lower_tex: Don't normalize coordinates for TXF with RECT

v2: remove the option to actually request normalization and its
    application in Intel < Gen6 (Jason)

v3: Also don't lower for query operations (Jason)

Fixes: 1ce8060c25c7f2c7a54159fab6a6974c0ba182a8
    nir/lower_tex: support for lowering RECT textures

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5105>

19 months agoci: Quick exit qpa extraction for non-matching qpas.
Eric Anholt [Tue, 26 May 2020 20:28:30 +0000 (13:28 -0700)]
ci: Quick exit qpa extraction for non-matching qpas.

When you're bringing up a new driver in CI with significant number of
failures (or when a CI run breaks a driver), the QPA extraction can easily
take the whole job timeout as we go about processing each QPA (100 of them
in my early VK CI fails) per unexpected result we're saving (50), which
involves reading and each line of the file in shell.  By quickly filtering
out the QPA files not including our test, we can save all that shell
overhead, bringing QPA extract time down to a couple of minutes.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

19 months agoci: Move baremetal DEQP_NO_SAVE_RESULTS setup to the yml.
Eric Anholt [Fri, 22 May 2020 22:48:55 +0000 (15:48 -0700)]
ci: Move baremetal DEQP_NO_SAVE_RESULTS setup to the yml.

I'm going to want it unset (artifacts enabled) for the cheza jobs.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

19 months agoci: Add DEQP_EXPECTED_RENDERER support for VK tests.
Eric Anholt [Tue, 26 May 2020 17:53:05 +0000 (10:53 -0700)]
ci: Add DEQP_EXPECTED_RENDERER support for VK tests.

I used this to debug what was going on with freedreno VK in CI.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

19 months agoci: Auto-detect the architecture for VK ICD filenames.
Eric Anholt [Tue, 26 May 2020 18:18:33 +0000 (11:18 -0700)]
ci: Auto-detect the architecture for VK ICD filenames.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

19 months agoci: Drop old comment about enabling --deqp-watchdog.
Eric Anholt [Tue, 26 May 2020 18:07:41 +0000 (11:07 -0700)]
ci: Drop old comment about enabling --deqp-watchdog.

The parallel deqp runner does its own 60s watchdog.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

19 months agoci: Drop double ".txt" suffix on the unexpected results file.
Eric Anholt [Tue, 26 May 2020 17:15:19 +0000 (10:15 -0700)]
ci: Drop double ".txt" suffix on the unexpected results file.

Just a cosmetic fix in reviewing logs.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

19 months agospirv,radv,anv: implement no-op VK_GOOGLE_user_type
Samuel Pitoiset [Thu, 28 May 2020 08:21:27 +0000 (10:21 +0200)]
spirv,radv,anv: implement no-op VK_GOOGLE_user_type

This extension only allows HLSL shader compilers to optionally embed
unambiguous type information which can be safely ignored by the driver.

This fixes a crash with the recent Vulkan backend of Path Of Exile
(it uses the extension without checking if it's supported).

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5237>

19 months agoaco: fix 64-bit shared_atomic_exchange
Rhys Perry [Mon, 4 May 2020 13:11:00 +0000 (14:11 +0100)]
aco: fix 64-bit shared_atomic_exchange

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

19 months agoaco: don't reorder barriers in the scheduler
Rhys Perry [Fri, 1 May 2020 10:04:27 +0000 (11:04 +0100)]
aco: don't reorder barriers in the scheduler

Unless we're reordering it around a barrier of the same type

No shader-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

19 months agoaco: preserve more fields when combining additions into SMEM
Rhys Perry [Thu, 30 Apr 2020 15:10:42 +0000 (16:10 +0100)]
aco: preserve more fields when combining additions into SMEM

Totals from 11 (0.01% of 127638) affected shaders:

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

19 months agoaco: check instruction format before waiting for a previous SMEM store
Rhys Perry [Wed, 29 Apr 2020 16:47:50 +0000 (17:47 +0100)]
aco: check instruction format before waiting for a previous SMEM store

Totals from 7 (0.01% of 127638) affected shaders:
CodeSize: 40336 -> 40320 (-0.04%)
Instrs: 7807 -> 7803 (-0.05%)
Cycles: 118588 -> 118344 (-0.21%); split: -0.23%, +0.02%
SMEM: 331 -> 339 (+2.42%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 1749953ea3 ('aco/gfx10: Wait for pending SMEM stores before loads')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

19 months agoaco: consider SDWA during value numbering
Rhys Perry [Fri, 22 May 2020 14:42:39 +0000 (15:42 +0100)]
aco: consider SDWA during value numbering

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 23ac24f5b1fdde73cf8ec1ef6cbe08d73d6776f5
   ('aco: add missing conversion operations for small bitsizes')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>

19 months agoaco: fix interaction with 3f branch workaround and p_constaddr
Rhys Perry [Fri, 22 May 2020 14:42:12 +0000 (15:42 +0100)]
aco: fix interaction with 3f branch workaround and p_constaddr

The offset was incorrect if we inserted a nop before the p_constaddr.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>

19 months agogitlab-ci: Pull in GCC 9 from Debian testing in x86_test-gl/vk images
Michel Dänzer [Tue, 26 May 2020 09:04:19 +0000 (11:04 +0200)]
gitlab-ci: Pull in GCC 9 from Debian testing in x86_test-gl/vk images

The GCC 8 packages from buster are no longer compatible with libc6 from
testing. We could use the GCC 8 packages from testing instead, but this
is easier.

v2:
* Update piglit-quick_gl test results, due to the piglit issue fixed by
  https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/294

Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>

19 months agogitlab-ci: x86_test-base image as common base for x86_test-gl/vk
Michel Dänzer [Sat, 16 May 2020 15:17:23 +0000 (17:17 +0200)]
gitlab-ci: x86_test-base image as common base for x86_test-gl/vk

Making use of the relatively recent FDO_BASE_IMAGE feature of the
templates, the x86_test-base image contents are shared as a separate
layer by the x86_test-gl/vk images (meaning the former only needs to be
downloaded once for either or both of the latter). This should be more
efficient in terms of overall network bandwidth and storage, in
particular if the base image changes less often than the -gl/vk ones.

v2:
* List x86_test-base in needs: along with x86_test-gl/vk (see parent
  commit)
* Always put $STABLE/TESTING_EPHEMERAL on separate lines, will make it
  easier to add any non-ephemeral packages

Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>

19 months agogitlab-ci: Also list arm/x86_build in needs: of test jobs
Michel Dänzer [Sat, 16 May 2020 10:07:42 +0000 (12:07 +0200)]
gitlab-ci: Also list arm/x86_build in needs: of test jobs

Without this, the test jobs may spuriously run if the arm/x86_build
jobs fail.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>

19 months agointel: Add helper to calculate GPGPU_WALKER::RightExecutionMask
Caio Marcelo de Oliveira Filho [Wed, 27 May 2020 15:05:41 +0000 (08:05 -0700)]
intel: Add helper to calculate GPGPU_WALKER::RightExecutionMask

Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agoiris, i965: Update limits for ARB_compute_variable_group_size
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 06:32:18 +0000 (23:32 -0700)]
iris, i965: Update limits for ARB_compute_variable_group_size

The CS compiler now produces multiple SIMD variants, so the previous
trade-off between "always using SIMD32" and "having a smaller max
invocations" is now gone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agoiris, i965: Drop max_variable_local_size
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 06:55:23 +0000 (23:55 -0700)]
iris, i965: Drop max_variable_local_size

This was used to decide which SIMD width to generate code for
ARB_compute_variable_group_size.  Now that compiler will generate
multiple SIMD widths, this information is unused.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agointel/fs: Generate multiple CS SIMD variants for variable group size
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 08:56:54 +0000 (01:56 -0700)]
intel/fs: Generate multiple CS SIMD variants for variable group size

This will make the GL drivers pick the right SIMD variant for a given
group size set during dispatch.  The heuristic implemented in
brw_cs_simd_size_for_group_size() is the same as in brw_compile_cs().

The cs_prog_data::simd_size field was removed.  The generated SIMD
sizes are marked in a bitmask, which is already used via
brw_cs_simd_size_for_group_size() by the drivers.

When in variable group size, it is OK if larger SIMD shader spill,
since we'd need it for the cases where the smaller one can't hold all
the invocations.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agoanv: Use new helper functions to pick SIMD variant for CS
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 07:17:27 +0000 (00:17 -0700)]
anv: Use new helper functions to pick SIMD variant for CS

Also combine the existing individual anv helpers into a single one for
all CS related parameters.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agoiris: Use new helper functions to pick SIMD variant for CS
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 07:09:19 +0000 (00:09 -0700)]
iris: Use new helper functions to pick SIMD variant for CS

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agoiris: Set CS KernelStatePointer at dispatch
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 09:34:52 +0000 (02:34 -0700)]
iris: Set CS KernelStatePointer at dispatch

There's an update for INTERFACE_DESCRIPTOR_DATA at dispatch, so we can
just move the KSP assignment there.  This flexibility will later allow
variable group size to pick the right SIMD variant.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agoi965: Use new helper functions to pick SIMD variant for CS
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 07:51:44 +0000 (00:51 -0700)]
i965: Use new helper functions to pick SIMD variant for CS

Also expand the existing i965 helper to return the other CS related
paramters.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agointel/fs: Add helper to get prog_offset and simd_size
Caio Marcelo de Oliveira Filho [Thu, 21 May 2020 09:26:21 +0000 (02:26 -0700)]
intel/fs: Add helper to get prog_offset and simd_size

This indirection will be used by the variable group size case in a
later change.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agointel/fs: Support INTEL_DEBUG=no8,no32 in compute shaders
Caio Marcelo de Oliveira Filho [Tue, 19 May 2020 17:08:12 +0000 (10:08 -0700)]
intel/fs: Support INTEL_DEBUG=no8,no32 in compute shaders

The "no32" flag will have precedence over "do32", like is done for FS.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agointel/fs: Remove min_dispatch_width spilling decision from RA
Caio Marcelo de Oliveira Filho [Tue, 19 May 2020 21:37:44 +0000 (14:37 -0700)]
intel/fs: Remove min_dispatch_width spilling decision from RA

Move the decision one level up, let brw_compile_*() functions use the
spilling information to decide whether or not a certain width
compilation can spill (passed via run_*() functions).

The min_dispatch_width was used to compare with the dispatch_width and
decide whether "a previous shader is already available, so don't
accept spill".

This is replaced by:

- Not calling run_*() functions if it is know beforehand a smaller width
  already spilled -- since the larger width will spill and fail;

- Explicitly passing whether or not a shader is allowed to spill.  For
  the cases where the smaller width is available and haven't spilled,
  the larger width will be compiled but is only useful if it won't
  spill.

Moving the decision to this level will be useful later for variable
group size, which is a case where we want all the widths to be allowed
to spill.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

19 months agodocs: update calendar, add news item, and link releases notes for 20.1.0
Eric Engestrom [Wed, 27 May 2020 20:27:17 +0000 (22:27 +0200)]
docs: update calendar, add news item, and link releases notes for 20.1.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5234>

19 months agodocs: Add release notes for 20.1.0
Eric Engestrom [Wed, 27 May 2020 21:46:48 +0000 (23:46 +0200)]
docs: Add release notes for 20.1.0

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5234>

19 months agozink: always use logical eq ops in ntv with 1bit inputs
Mike Blumenkrantz [Wed, 27 May 2020 19:28:42 +0000 (15:28 -0400)]
zink: always use logical eq ops in ntv with 1bit inputs

integer and float compare ops cannot take boolean types, so the bit size
of the inputs should be checked here so that we can swap to the logical
equality functions if we're being passed a bool value

resolves tons of validator errors in glsl piglit tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5231>

19 months agopan/bi: Initialize struct fma_op_info member extended.
Vinson Lee [Wed, 27 May 2020 00:26:47 +0000 (17:26 -0700)]
pan/bi: Initialize struct fma_op_info member extended.

Fix warning reported by Coverity Scan.

Uninitialized scalar variable (UNINIT)
uninit_use: Using uninitialized value info. Field info.extended is
uninitialized.

Fixes: 8c79c710d4e1 ("pan/bi: Identify extended FMA opcodes")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5224>

19 months agolima/ppir: use a ready list in node_to_instr
Erico Nunes [Sun, 17 May 2020 13:56:42 +0000 (15:56 +0200)]
lima/ppir: use a ready list in node_to_instr

After the recent optimizations in ppir lowering that increase options
for combining, node_to_instr now may have multiple options of nodes to
insert and needs to decide which is better.
For example, if an instruction uses both a varying and a texture, there
are two nodes nodes that can be inserted to the load varying slot in the
same instruction (ld_var and ld_coords). It is much more advantageous to
pipeline the load texture coords since that enables the higher precision
path for texture coordinates. However, with the current recursive
expansion, this cannot be influenced.

This simple ready list implementation in node_to_instr allows it to
choose the next node to expand based on a priority score, rather than
relying on the random order coming from the recursive expansion.

Other than preferring nodes with pipeline output (which covers ld_coords
vs ld_var), nodes using later slots in the pipeline are now expanded
first, allowing node_to_instr to make all of the earlier (pipelineable)
nodes available in the ready list so the best one can be chosen when
picking nodes for the earlier slots.

Fixes: 632a921bd0d lima/ppir: optimize tex loads with single successor
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5092>

19 months agopan/bi: Suppress inf/nan for now
Alyssa Rosenzweig [Wed, 27 May 2020 18:53:05 +0000 (14:53 -0400)]
pan/bi: Suppress inf/nan for now

This is a (hopefully temporary) hack. The blob does it for ES2 at any
rate.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Add CSEL.16 packing tests
Alyssa Rosenzweig [Wed, 27 May 2020 16:32:28 +0000 (12:32 -0400)]
pan/bi: Add CSEL.16 packing tests

Passing but let's increase coverage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Pack compact vertex texturing
Alyssa Rosenzweig [Wed, 27 May 2020 15:52:57 +0000 (11:52 -0400)]
pan/bi: Pack compact vertex texturing

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Add f16 TEXC.vtx op
Alyssa Rosenzweig [Wed, 27 May 2020 15:43:37 +0000 (11:43 -0400)]
pan/bi: Add f16 TEXC.vtx op

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Allow vertex txl with lod=0 as compact
Alyssa Rosenzweig [Wed, 27 May 2020 15:41:42 +0000 (11:41 -0400)]
pan/bi: Allow vertex txl with lod=0 as compact

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Document compute_lod bit for compact tex
Alyssa Rosenzweig [Wed, 27 May 2020 15:33:26 +0000 (11:33 -0400)]
pan/bi: Document compute_lod bit for compact tex

At least I assume this works this way.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Also add compact vertex texturing
Alyssa Rosenzweig [Wed, 27 May 2020 15:28:11 +0000 (11:28 -0400)]
pan/bi: Also add compact vertex texturing

This implies lod=0.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/bi: Add TEX.vtx opcode for vertex texturing
Alyssa Rosenzweig [Wed, 27 May 2020 15:24:49 +0000 (11:24 -0400)]
pan/bi: Add TEX.vtx opcode for vertex texturing

Always has an LOD.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopan/decode: Decode Bifrost shader flags
Alyssa Rosenzweig [Wed, 27 May 2020 20:38:47 +0000 (16:38 -0400)]
pan/decode: Decode Bifrost shader flags

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Set MALI_BIFROST_EARLY_Z as necessary
Alyssa Rosenzweig [Tue, 26 May 2020 23:48:25 +0000 (19:48 -0400)]
panfrost: Set MALI_BIFROST_EARLY_Z as necessary

Fixes blending.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Identify MALI_BIFROST_EARLY_Z flag
Alyssa Rosenzweig [Wed, 27 May 2020 20:29:01 +0000 (16:29 -0400)]
panfrost: Identify MALI_BIFROST_EARLY_Z flag

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Add defines for bifrost unk1 flags
Alyssa Rosenzweig [Wed, 27 May 2020 20:26:29 +0000 (16:26 -0400)]
panfrost: Add defines for bifrost unk1 flags

Instead of open-coding.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Document Midgard Inf/NaN suppress bit
Alyssa Rosenzweig [Wed, 27 May 2020 20:07:00 +0000 (16:07 -0400)]
panfrost: Document Midgard Inf/NaN suppress bit

We should probably not be setting this..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Ensure nonlinear strides are 16-aligned
Alyssa Rosenzweig [Wed, 27 May 2020 14:58:17 +0000 (10:58 -0400)]
panfrost: Ensure nonlinear strides are 16-aligned

To match how they are encoded.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: bde19c0e7ba ("panfrost: Fix tiled texture "stride"s on Bifrost")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Identify Bifrost texture format swizzle
Alyssa Rosenzweig [Tue, 26 May 2020 23:48:29 +0000 (19:48 -0400)]
panfrost: Identify Bifrost texture format swizzle

We don't force w=1 for Bifrost textures. We already compose this into
the swizzle as necessary, so we can just ignore this field I think. But
let's identify it so we don't forget what it is.

The blob uses it to force w=1 for <= 3-channel formats (0x10), as well
as a flag to swap r/b for BGRA (0x4). There are probably other flags
here but it doesn't.. really matter to us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Set unk2 to accomodate blending
Alyssa Rosenzweig [Tue, 26 May 2020 22:50:29 +0000 (18:50 -0400)]
panfrost: Set unk2 to accomodate blending

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Share MRT blend flag calculation with Bifrost
Alyssa Rosenzweig [Tue, 26 May 2020 22:48:04 +0000 (18:48 -0400)]
panfrost: Share MRT blend flag calculation with Bifrost

As far as I know the field is the same.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Force Z/S tiling on Bifrost
Alyssa Rosenzweig [Tue, 26 May 2020 22:21:57 +0000 (18:21 -0400)]
panfrost: Force Z/S tiling on Bifrost

Like we do on SFBD since we don't know the format bits yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Tweak Bifrost colour buffer magic
Alyssa Rosenzweig [Tue, 26 May 2020 22:20:56 +0000 (18:20 -0400)]
panfrost: Tweak Bifrost colour buffer magic

For tiled or linear.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Tweak zsbuf magic numbers for Bifrost
Alyssa Rosenzweig [Tue, 26 May 2020 22:19:19 +0000 (18:19 -0400)]
panfrost: Tweak zsbuf magic numbers for Bifrost

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Adjust null_rt for Bifrost
Alyssa Rosenzweig [Tue, 26 May 2020 22:16:51 +0000 (18:16 -0400)]
panfrost: Adjust null_rt for Bifrost

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agopanfrost: Fix Bifrost blending with depth-only FBO
Alyssa Rosenzweig [Mon, 4 May 2020 16:48:50 +0000 (12:48 -0400)]
panfrost: Fix Bifrost blending with depth-only FBO

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

19 months agoac/gpu_info: Correct Acturus cu bitmap
James Zhu [Tue, 26 May 2020 13:28:41 +0000 (09:28 -0400)]
ac/gpu_info: Correct Acturus cu bitmap

The cu bitmap in amd gpu info structure is
4x4 size array, and it's usually suitable for Vega
ASICs which has 4*2 SE/SH layout.
But for Arcturus, SE/SH layout is changed to 8*1.
To mostly reduce the impact, we make it compatible
with current bitmap array as below:
SE4,SH0 --> cu_bitmap[0][1]
SE5,SH0 --> cu_bitmap[1][1]
SE6,SH0 --> cu_bitmap[2][1]
SE7,SH0 --> cu_bitmap[3][1]

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5212>

19 months agointel/fs: Work around dual-source blending hangs in combination with SIMD16
Danylo Piliaiev [Thu, 14 May 2020 12:29:36 +0000 (15:29 +0300)]
intel/fs: Work around dual-source blending hangs in combination with SIMD16

It was found that dual-source blending hangs with SIMD16 dispatch in some
specific but unknown situation. Which in the wild happen when rgba
anti-aliasing is enabled for fonts.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5037>

19 months agozink: use general-layout when blitting to/from same resource
Erik Faye-Lund [Mon, 25 May 2020 10:06:04 +0000 (12:06 +0200)]
zink: use general-layout when blitting to/from same resource

This avoids a validator warning when for instance generating mipmaps.

Fixes: d2bb63c8d4c ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5199>

19 months agoradeonsi/drirc: enable zerovram option for 7 Days to Die
Pierre-Eric Pelloux-Prayer [Fri, 22 May 2020 16:38:24 +0000 (18:38 +0200)]
radeonsi/drirc: enable zerovram option for 7 Days to Die

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2686
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5168>

19 months agoturnip: support VkImageDrmFormatModifierExplicitCreateInfoEXT
Jonathan Marek [Tue, 12 May 2020 23:51:29 +0000 (19:51 -0400)]
turnip: support VkImageDrmFormatModifierExplicitCreateInfoEXT

This will be used to import images which have different layout from what
turnip uses by default. For example non-UBWC (linear) images from the video
decoder on some hardware have a 512 pitch alignment.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4596>

19 months agofreedreno/layout: add explicit offset/pitch argument to fdl6_layout
Jonathan Marek [Tue, 12 May 2020 23:38:48 +0000 (19:38 -0400)]
freedreno/layout: add explicit offset/pitch argument to fdl6_layout

fdl6_layout will return false when the explicit pitch is not valid.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4596>