mesa.git
2 years agoetnaviv: drm: Use mesa's atomic definitions
Guido Günther [Fri, 31 May 2019 12:35:06 +0000 (14:35 +0200)]
etnaviv: drm: Use mesa's atomic definitions

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoetnaviv: drm: Drop drm_{public,private}
Guido Günther [Fri, 31 May 2019 12:35:06 +0000 (14:35 +0200)]
etnaviv: drm: Drop drm_{public,private}

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoetnaviv: drm: Drop inexistent headers
Guido Günther [Fri, 31 May 2019 12:35:06 +0000 (14:35 +0200)]
etnaviv: drm: Drop inexistent headers

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoetnaviv: Add libdrm code as of 922d92994267743266024ecceb734ce0ebbca808
Guido Günther [Fri, 31 May 2019 12:35:06 +0000 (14:35 +0200)]
etnaviv: Add libdrm code as of 922d92994267743266024ecceb734ce0ebbca808

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoetnaviv: untabify
Guido Günther [Fri, 31 May 2019 12:35:06 +0000 (14:35 +0200)]
etnaviv: untabify

Two driver files had tabs mixed with spaces. Remove the tabs.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agopanfrost: bifrost: Fix format string in disassembler
Tomeu Vizoso [Wed, 5 Jun 2019 06:44:05 +0000 (08:44 +0200)]
panfrost: bifrost: Fix format string in disassembler

The compiler configuration was hardened to fail on format warnings and
things stopped building.

Fixes: c9c1e2610647 ("mesa: prevent common string formatting security issues")
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-By: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agoiris: Free the buffer when reading from the disk cache.
Kenneth Graunke [Wed, 5 Jun 2019 05:02:24 +0000 (22:02 -0700)]
iris: Free the buffer when reading from the disk cache.

2 years agopanfrost/midgard: Don't promote non-SSA to pipeline registers
Alyssa Rosenzweig [Tue, 4 Jun 2019 21:35:47 +0000 (21:35 +0000)]
panfrost/midgard: Don't promote non-SSA to pipeline registers

Fixes: 33800f4612 ("panfrost/midgard: Implement "pipeline register"
prepass")

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agofreedreno: Drop invalid scissor optimization.
Eric Anholt [Fri, 17 May 2019 16:55:40 +0000 (09:55 -0700)]
freedreno: Drop invalid scissor optimization.

We do support TF now, so it's no longer valid.  Besides, if we want this
optimization, we should probably have mesa/st doing it right for everyone.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agofreedreno: Reuse glsl_get_sampler_coordinate_components().
Eric Anholt [Wed, 15 May 2019 00:18:40 +0000 (17:18 -0700)]
freedreno: Reuse glsl_get_sampler_coordinate_components().

We have the GLSL type, so we can just ask it how many coordinates there
are.  The GLSL function already has Vulkan cases that we'd probably want
eventually.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agofreedreno: Improve the pi approximations in trig lowering.
Eric Anholt [Mon, 3 Jun 2019 23:12:14 +0000 (16:12 -0700)]
freedreno: Improve the pi approximations in trig lowering.

When comparing our sin/cos behavior to the closed source driver, I
noticed that we were off by a bit (or, in the case of 1/2pi, 3 bits).

Fixes:
dEQP-GLES3.functional.shaders.random.trigonometric.vertex.52
dEQP-GLES3.functional.shaders.random.all_features.vertex.0

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agoac: rename LLVM <= 7 helpers for readability
Marek Olšák [Fri, 24 May 2019 22:57:10 +0000 (18:57 -0400)]
ac: rename LLVM <= 7 helpers for readability

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoac: fix a typo in ac_build_wg_scan_bottom
Marek Olšák [Wed, 22 May 2019 22:23:27 +0000 (18:23 -0400)]
ac: fix a typo in ac_build_wg_scan_bottom

Cc: 19.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoglx: Fix error message when no driverName is available
Caio Marcelo de Oliveira Filho [Tue, 4 Jun 2019 22:23:41 +0000 (15:23 -0700)]
glx: Fix error message when no driverName is available

Just provide a "(null)" literal in case driverName is NULL.

  In file included from ../src/glx/dri3_glx.c:76:
  ../src/glx/dri3_glx.c: In function ‘dri3_create_screen’:
  ../src/glx/dri_common.h:70:36: error: ‘%s’ directive argument is null [-Werror=format-overflow=]
     70 | #define CriticalErrorMessageF(...) dri_message(_LOADER_FATAL, __VA_ARGS__)
        |                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  ../src/glx/dri3_glx.c:1002:4: note: in expansion of macro ‘CriticalErrorMessageF’
   1002 |    CriticalErrorMessageF("failed to load driver: %s\n", driverName);
        |    ^~~~~~~~~~~~~~~~~~~~~
  ../src/glx/dri3_glx.c:1002:50: note: format string is defined here
   1002 |    CriticalErrorMessageF("failed to load driver: %s\n", driverName);
        |                                                  ^~
  cc1: some warnings being treated as errors

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agovirgl: resolve to correct level during texture read
Chia-I Wu [Mon, 3 Jun 2019 18:39:34 +0000 (11:39 -0700)]
virgl: resolve to correct level during texture read

When PIPE_TRANSFER_READ requires a resolve, we blit from the host
storage to a temporary storage, and do a format conversion from the
temporary storage to the guest storage.  This change makes sure we
convert to the correct level of the guest storage.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2 years agovirgl: fix texture resolving with compressed formats
Chia-I Wu [Mon, 3 Jun 2019 22:19:18 +0000 (15:19 -0700)]
virgl: fix texture resolving with compressed formats

util_format_translate_3d expects the source box to be aligned to the
block size.  When resolving, make sure the size of the staging
buffer is aligned to the block size.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2 years agofreedreno: Add printf pattern string.
Bas Nieuwenhuizen [Tue, 4 Jun 2019 21:19:27 +0000 (23:19 +0200)]
freedreno: Add printf pattern string.

Some new flag setting disallows it due to being a security risk.

Fixes: c9c1e261064 "mesa: prevent common string formatting security issues"
Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agoRevert "vl: Enable DRM by default."
Bas Nieuwenhuizen [Tue, 4 Jun 2019 21:14:56 +0000 (23:14 +0200)]
Revert "vl: Enable DRM by default."

Reason:

meson.build:586:7: ERROR: Unknown variable "dep_libdrm".

if building without x11 platform.

This reverts commit 392c60928a5debbe6782ed1aa136597504bfbc5b.

2 years agopanfrost/midgard: .pos propagation
Alyssa Rosenzweig [Thu, 23 May 2019 03:01:32 +0000 (03:01 +0000)]
panfrost/midgard: .pos propagation

A previous optimization converts fmax(x, 0.0) instructions to fmov.pos.
This pass then propagates the .pos from the move up to the source
instruction (when possible). From there, copy propagation will eliminate
the move.

In the future, we might prefer to do this in common NIR code like we do
for saturate, as Bifrost can also benefit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Cleanup copy propagation
Alyssa Rosenzweig [Thu, 23 May 2019 02:23:39 +0000 (02:23 +0000)]
panfrost/midgard: Cleanup copy propagation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Implement "pipeline register" prepass
Alyssa Rosenzweig [Thu, 23 May 2019 01:40:23 +0000 (01:40 +0000)]
panfrost/midgard: Implement "pipeline register" prepass

This prepass, run after scheduling but before RA, specializes to
pipeline registers where possible. It walks the IR, checking whether
sources are ever used outside of the immediate bundle in which they are
written. If they are not, they are rewritten to a pipeline register (r24
or r25), valid only within the bundle itself. This has theoretical
benefits for power consumption and register pressure (and performance by
extension). While this is tested to work, it's not clear how much of a
win it really is, especially without an out-of-order scheduler (yet!).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Helpers for pipeline
Alyssa Rosenzweig [Thu, 23 May 2019 01:56:03 +0000 (01:56 +0000)]
panfrost/midgard: Helpers for pipeline

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Refactor schedule/emit pipeline
Alyssa Rosenzweig [Wed, 22 May 2019 04:33:21 +0000 (04:33 +0000)]
panfrost/midgard: Refactor schedule/emit pipeline

First, this moves the scheduler and emitter out of midgard_compile.c
into their own dedicated files.

More interestingly, this slims down midgard_bundle to be essentially an
array of _pointers_ to midgard_instructions (plus some bundling
metadata), rather than the instructions and packing themselves. The
difference is critical, as it means that (within reason, i.e. as long as
it doesn't affect the schedule) midgard_instrucitons can now be modified
_after_ scheduling while having changes updated in the final binary.

On a more philosophical level, this removes an IR. Previously, the IR
before scheduling (MIR) was separate from the IR after scheduling
(post-schedule MIR), requiring a separate set of utilities to traverse,
using different idioms. There was no good reason for this, and it
restricts our flexibility with the RA. So unify all the things!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Cleanup RA (stylistic changes)
Alyssa Rosenzweig [Wed, 22 May 2019 04:32:55 +0000 (04:32 +0000)]
panfrost/midgard: Cleanup RA (stylistic changes)

Trivial.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Share MIR utilities
Alyssa Rosenzweig [Wed, 22 May 2019 04:32:17 +0000 (04:32 +0000)]
panfrost/midgard: Share MIR utilities

These are more generally useful than the files they were constrained to.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Misc. cleanup for readibility
Alyssa Rosenzweig [Tue, 21 May 2019 04:09:43 +0000 (04:09 +0000)]
panfrost/midgard: Misc. cleanup for readibility

Mostly, this fixes a number of instances of lines >> 80 chars,
refactoring them into something legible.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Extend RA to non-vec4 sources
Alyssa Rosenzweig [Wed, 22 May 2019 02:45:42 +0000 (02:45 +0000)]
panfrost/midgard: Extend RA to non-vec4 sources

This represents a major break with the former RA design. We now use
conflicting register classes to represent the subdivision of Midgard's
128-bit registers into varying sizes and arrangement. We determine class
based on the number of components in the instructions' masks. To support
this, we include a number of helpers in the RA to allow composing
swizzles and masks, such that MIR written implicitly assuming .xyzw
sources can be transformed to use actual (non-aligned) sources.

The net result is a marked decrease in register pressure on
non-vec4-exclusive shaders. We could still be doing much better. Not
implemented yet are:

   - Register spilling
   - Per-component liveness

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Set masks on ld_vary
Alyssa Rosenzweig [Wed, 22 May 2019 02:44:12 +0000 (02:44 +0000)]
panfrost/midgard: Set masks on ld_vary

These masks distinguish scalar/vec2/vec3 loads from the default vec4,
which helps with assembly readability (since it's immediately obvious
how many components are _actually_ affected, rather than doing
mysterious things to an unknown number of unused components). Later in
the series, this will enable smarter register allocation, as the unused
components will not be interpreted abnormally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Fix liveness analysis bugs
Alyssa Rosenzweig [Wed, 22 May 2019 02:41:51 +0000 (02:41 +0000)]
panfrost/midgard: Fix liveness analysis bugs

This fixes liveness analysis with respect to inline constants and
branching. in practice, the symptom is abnormally high register
pressure.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Set int outmod for "pasted" code
Alyssa Rosenzweig [Wed, 22 May 2019 02:40:41 +0000 (02:40 +0000)]
panfrost/midgard: Set int outmod for "pasted" code

These snippets of integer assembly are injected for various purposes.
Eventually, we'll want to implement these in NIR directly. Regardless,
the "default" output modifier is different between floats and ints, so
let's set the right one.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Hoist some utility functions
Alyssa Rosenzweig [Wed, 22 May 2019 02:39:48 +0000 (02:39 +0000)]
panfrost/midgard: Hoist some utility functions

These were static to midgard_compile.c but are more generally useful
across the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agopanfrost/midgard: Remove pinning
Alyssa Rosenzweig [Mon, 20 May 2019 00:46:48 +0000 (00:46 +0000)]
panfrost/midgard: Remove pinning

This mechanism is only used by blend shaders, so just use a move here.
Ideally, it'll be copy-propped and DCE'd away; this removes a source of
considerable indirection and will simplify RA logic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2 years agonir/algebraic: Simplify max(abs(a), 0.0) -> abs(a)
Alyssa Rosenzweig [Tue, 4 Jun 2019 19:54:12 +0000 (19:54 +0000)]
nir/algebraic: Simplify max(abs(a), 0.0) -> abs(a)

This pattern was noticed in glmark's jellyfish scene.

v2: Add inexact qualifier due to NaN behaviour.

Minimal shader-db changes (slightly helped).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Elie Tournier <tournier.elie@gmail.com>
2 years agomesa: prevent common string formatting security issues
Mark Janes [Mon, 3 Jun 2019 23:59:45 +0000 (16:59 -0700)]
mesa: prevent common string formatting security issues

Adds a compile-time error for obvious security issues like:

  printf(string_var);

The proposed flag is more tolerant than -Wformat-nonliteral.
Specifically, it tolerates common mesa formatting like:

  static const char *shader_template = "really long string %d";
  printf(shader_template, uniform_number);

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110833
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2 years agointel/fs: Add an UNDEF instruction to avoid excess live ranges
Jason Ekstrand [Wed, 29 May 2019 22:46:55 +0000 (17:46 -0500)]
intel/fs: Add an UNDEF instruction to avoid excess live ranges

With 8 and 16-bit types and anything where we have to use non-trivial
strides registersto deal with restrictions, we end up with things that
look like partial writes even though we don't care about any values in
the register except those written by that instruction.  This is
particularly important when dealing with loops because liveness sees
is_partial_write and the fact that an old version from a previous loop
iteration may be valid at that point and extends all purely partially
written values to the entire loop.

This commit adds a new UNDEF instruction which does nothing (the
generator doesn't emit anything) but which does a fake write to the
register.  This informs liveness that we don't care about any values
before that point so it won't consider those registers to be falsely
live.  We can safely emit UNDEF instructions for all SSA values that
come in from NIR and nearly all temporaries generated by various stages
of the compiler.  In particular, we need to insert UNDEF instructions
when we handle region restrictions because the newly allocated registers
are almost guaranteed to be partially written.

No shader-db changes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110432
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agospirv: Update the OpenCL.std.h header
Caio Marcelo de Oliveira Filho [Mon, 3 Jun 2019 21:41:46 +0000 (14:41 -0700)]
spirv: Update the OpenCL.std.h header

This corresponds to commit 8b911bd2ba37677037b38c9bd286c7c05701bcda on
GitHub.

We previously tweaked OpenCL.std.h from upstream to be included in C
code.  Now upstream header can be included, however the symbol names
are slightly different (include an OpenCLstd_ prefix), so this patch
also fixes vtn_opencl.c to use those.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2 years agoradv: Use bo metadata for imported image tiling on Android.
Bas Nieuwenhuizen [Mon, 13 May 2019 12:09:55 +0000 (14:09 +0200)]
radv: Use bo metadata for imported image tiling on Android.

This way we handle linear images etc. correctly.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agovl: Enable DRM by default.
Bas Nieuwenhuizen [Thu, 30 May 2019 18:34:06 +0000 (20:34 +0200)]
vl: Enable DRM by default.

If libdrm is found the pipe loader enables drm anyway, and that is
pretty much the only extra dependency this code has.

This enables creating libva display using a drm fd without having
to enable the DRM (GBM really) backend of EGL, which is completely
unrelated.

Leaving the X11 platforms alone as they would still result in the
additional inclusion of extra deps.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2 years agoanv: Advertise support for VK_EXT_fragment_shader_interlock
Jason Ekstrand [Fri, 17 May 2019 16:33:23 +0000 (11:33 -0500)]
anv: Advertise support for VK_EXT_fragment_shader_interlock

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agospirv: Implement SPV_EXT_fragment_shader_interlock
Jason Ekstrand [Fri, 17 May 2019 16:32:10 +0000 (11:32 -0500)]
spirv: Implement SPV_EXT_fragment_shader_interlock

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agospirv: Update the headers from latest Khronos master
Jason Ekstrand [Fri, 17 May 2019 16:20:13 +0000 (11:20 -0500)]
spirv: Update the headers from latest Khronos master

This corresponds to 8b911bd2ba37677037b38c9bd286c7c05701bcda in
https://github.com/KhronosGroup/SPIRV-Headers.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agovulkan: Update the XML and headers to 1.1.110
Jason Ekstrand [Fri, 17 May 2019 16:01:20 +0000 (11:01 -0500)]
vulkan: Update the XML and headers to 1.1.110

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agoac/nir: mark some texture intrinsics as convergent
Rhys Perry [Wed, 29 May 2019 15:07:44 +0000 (16:07 +0100)]
ac/nir: mark some texture intrinsics as convergent

Otherwise LLVM can sink them and their texture coordinate calculations
into divergent branches.

v2: simplify the conditions on which the intrinsic is marked as convergent
v3: only mark as convergent in FS and CS with derivative groups

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoradv: fix some compiler warnings
Rhys Perry [Thu, 30 May 2019 14:55:11 +0000 (15:55 +0100)]
radv: fix some compiler warnings

Fixes -Woverflow warnings with GCC 9.1.1

v2: use a cast instead of a bitwise and

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agointel/fs: Skip registers faster when setting spill costs
Jason Ekstrand [Mon, 3 Jun 2019 22:09:12 +0000 (17:09 -0500)]
intel/fs: Skip registers faster when setting spill costs

This might be slightly faster since we're doing one read rather than
two before we decide to skip.  The more important reason, however, is
because no_spill prevents us from re-spilling spill registers.  In the
new world in which we don't re-calculate liveness every spill, we may
not have valid liveness for spill registers so we shouldn't even look
their live ranges up.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110825
Fixes: e99081e76d4 "intel/fs/ra: Spill without destroying the..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
2 years agoradeonsi/nir: Fix type in bindless address computation
Connor Abbott [Fri, 24 May 2019 13:08:06 +0000 (15:08 +0200)]
radeonsi/nir: Fix type in bindless address computation

Bindless handles in GL are 64-bit. This fixes an assert failure in LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoetnaviv: implement set_active_query_state(..) for hw queries
Christian Gmeiner [Tue, 28 May 2019 19:43:51 +0000 (21:43 +0200)]
etnaviv: implement set_active_query_state(..) for hw queries

Clear w/ quad uses a normal draw which adds up to OQ. st/meta
uses set_active_query_state(..) to tell the driver to pause
queries in such cases.

Fixes spec@arb_occlusion_query@occlusion_query_meta_save piglit.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2 years agoradv: do not use gfx fast depth clears for layered depth/stencil images
Samuel Pitoiset [Mon, 3 Jun 2019 15:52:56 +0000 (17:52 +0200)]
radv: do not use gfx fast depth clears for layered depth/stencil images

The driver should only fast depth clears with the graphics path
when the view covers all image layers, otherwise this might
corrupt layers when HTILE is enabled.

Cc: 19.0 19.1 mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoac,radv: do not emit vec3 for raw load/store on SI
Samuel Pitoiset [Mon, 3 Jun 2019 13:09:38 +0000 (15:09 +0200)]
ac,radv: do not emit vec3 for raw load/store on SI

It's unsupported, only load/store format with vec3 are supported.

Fixes: 6970a9a6ca9 ("ac,radv: remove the vec3 restriction with LLVM 9+")"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agointel/compiler: Fix assertions in brw_alu3
Sagar Ghuge [Tue, 16 Apr 2019 06:26:47 +0000 (23:26 -0700)]
intel/compiler: Fix assertions in brw_alu3

v2: Fix assertion for src1 (Ian Romanick)

Fixes: 3b967e17 (intel/compiler: Avoid false positive assertions)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoiris: Fix SO stride units for DrawTransformFeedback
Kenneth Graunke [Mon, 3 Jun 2019 23:52:59 +0000 (16:52 -0700)]
iris: Fix SO stride units for DrawTransformFeedback

Mesa measures in DWords.  The hardware also claims to measure in DWords.
Except the SO_WRITE_OFFSET field is actually bits 31:2, with 1:0 MBZ.
Which means that it really measures in bytes.  So, convert to bytes.

Without this, our offset / stride denominator was 1/4th the size it
should be, leading to 4x the vertex count that we should have had.

Fixes GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_two_buffers

2 years agost/glsl: make sure to propagate initialisers to driver storage
Timothy Arceri [Wed, 29 May 2019 03:13:44 +0000 (13:13 +1000)]
st/glsl: make sure to propagate initialisers to driver storage

This essentially reverts 20234cfe3a20.

Fixes piglit test:
tests/spec/arb_get_program_binary/execution/uniform-after-restore.shader_test

Fixes: 20234cfe3a20 "st/mesa: don't propagate uniforms when restoring from cache"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110784

2 years agospirv: Like Uniform, do nothing for UniformId
Caio Marcelo de Oliveira Filho [Fri, 26 Apr 2019 20:21:56 +0000 (13:21 -0700)]
spirv: Like Uniform, do nothing for UniformId

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agospirv: Implement SpvOpCopyLogical
Caio Marcelo de Oliveira Filho [Thu, 25 Apr 2019 08:30:24 +0000 (01:30 -0700)]
spirv: Implement SpvOpCopyLogical

This is the same as SpvOpCopyObject but without the type checking,
which is how vtn_composite_copy works, so we just need to hook the
operation.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agospirv: Generalize OpSelect
Caio Marcelo de Oliveira Filho [Mon, 22 Apr 2019 16:45:53 +0000 (09:45 -0700)]
spirv: Generalize OpSelect

SPIR-V 1.4 supports OpSelect over any composite type, and also allows
scalar boolean condition for vector types -- a case which we already
handled to support old GLSLang.

Added a helper function to recursively perform nir_bcsel, that makes
easier to support structs.

v2: Replace asserts() with vtn_fail_if().  (Jason)

v3: Simplify Condition and Result types verifications.  (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agospirv: Move OpSelect handling to a function
Caio Marcelo de Oliveira Filho [Mon, 3 Jun 2019 22:30:33 +0000 (15:30 -0700)]
spirv: Move OpSelect handling to a function

This will make a later change easier to review.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir/vars_to_ssa: Handle UNDEF_NODE in more places
Caio Marcelo de Oliveira Filho [Mon, 3 Jun 2019 21:13:16 +0000 (14:13 -0700)]
nir/vars_to_ssa: Handle UNDEF_NODE in more places

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110832
Fixes: 911ea2c66fc "nir/vars_to_ssa: Use a non-null UNDEF_NODE pointer"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoac/registers: don't use the si, cik, vi names, use gfxN
Marek Olšák [Mon, 3 Jun 2019 21:07:16 +0000 (17:07 -0400)]
ac/registers: don't use the si, cik, vi names, use gfxN

trivial

2 years agoamd/common: use generated register header
Nicolai Hähnle [Mon, 6 May 2019 23:08:43 +0000 (01:08 +0200)]
amd/common: use generated register header

2 years agoamd/common: use SH{0,1}_CU_EN definitions only of COMPUTE_STATIC_THREAD_MGMT_SE0
Nicolai Hähnle [Mon, 6 May 2019 23:46:28 +0000 (01:46 +0200)]
amd/common: use SH{0,1}_CU_EN definitions only of COMPUTE_STATIC_THREAD_MGMT_SE0

The automatic header generation unifies identical registers in a series
and only emits definitions for the first one. This is mostly to avoid
emitting excessive definitions for CB registers, but special-casing
an exception for this family of registers doesn't seem worth it.

2 years agoamd/common: unify PITCH_GFX6 and PITCH_GFX9
Nicolai Hähnle [Mon, 6 May 2019 23:44:52 +0000 (01:44 +0200)]
amd/common: unify PITCH_GFX6 and PITCH_GFX9

The definition of the fields differs, but PITCH_GFX9 is a mere extension
of PITCH_GFX6 that does not conflict with any other fields.

This aligns the definitions with what will be generated from the
register JSON.

The information about how large the fields really are is preserved in
the register database.

2 years agoamd/common: rename R_3F2_CONTROL to IB_CONTROL for disambiguation
Nicolai Hähnle [Mon, 6 May 2019 12:47:40 +0000 (14:47 +0200)]
amd/common: rename R_3F2_CONTROL to IB_CONTROL for disambiguation

This "register" name collides with R_370_CONTROL.

This aligns the definitions with what will be generated from the
register JSON.

2 years agoamd/common: cleanup DATA_FORMAT/NUM_FORMAT field names
Nicolai Hähnle [Mon, 13 Nov 2017 15:35:59 +0000 (16:35 +0100)]
amd/common: cleanup DATA_FORMAT/NUM_FORMAT field names

The field layout wasn't actually changed in gfx9, so having the suffix
isn't very useful. The field *contents* were changed, but this is
reflected in the V_xxx_xxx definitions and is taken into account by
the ac_debug logic based on the register JSON.

This aligns the definitions with what will be generated from the
register JSON.

2 years agoamd/common: derive ac_debug tables from register JSON
Nicolai Hähnle [Mon, 6 May 2019 22:20:23 +0000 (00:20 +0200)]
amd/common: derive ac_debug tables from register JSON

2 years agoamd/registers: add JSON description of packet3 fields
Nicolai Hähnle [Mon, 6 May 2019 12:48:58 +0000 (14:48 +0200)]
amd/registers: add JSON description of packet3 fields

2 years agoamd/registers: add JSON descriptions of registers
Nicolai Hähnle [Mon, 6 May 2019 08:33:05 +0000 (10:33 +0200)]
amd/registers: add JSON descriptions of registers

The descriptions are mostly derived from parsing the existing
register headers.

2 years agoamd/registers: scripts for processing register descriptions in JSON
Nicolai Hähnle [Mon, 6 May 2019 08:31:19 +0000 (10:31 +0200)]
amd/registers: scripts for processing register descriptions in JSON

We will derive both the debugging tables and (the majority of) the
register headers from descriptions in JSON, instead of deriving the
debugging tables from an awkward parsing of the register headers.

Some of the scripts are useful for maintaining the register database
itself. The scripts are designed to output reasonably readable JSON
by default.

2 years agofreedreno: Fix GCC build error.
Vinson Lee [Thu, 30 May 2019 21:47:37 +0000 (14:47 -0700)]
freedreno: Fix GCC build error.

../src/freedreno/vulkan/tu_device.c:900:4: error: initializer element is not constant
    .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
    ^

Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110698
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agomesa: Use string literals for format strings
Mark Janes [Mon, 3 Jun 2019 22:42:22 +0000 (15:42 -0700)]
mesa: Use string literals for format strings

Android build settings require format strings to be string literals.

Fixes: d2906293c43 "mesa: EXT_dsa add selectorless matrix stack functions"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110833
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Always reserve binding table space for NIR constants
Caio Marcelo de Oliveira Filho [Wed, 29 May 2019 22:30:51 +0000 (15:30 -0700)]
iris: Always reserve binding table space for NIR constants

Don't have a separate mechanism for NIR constants to be removed from
the table.  If unused, we will compact it away.  The use_null_surface
is needed when INTEL_DISABLE_COMPACT_BINDING_TABLE is set.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Print binding tables when INTEL_DEBUG=bt
Caio Marcelo de Oliveira Filho [Thu, 23 May 2019 21:17:41 +0000 (14:17 -0700)]
iris: Print binding tables when INTEL_DEBUG=bt

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Compact binding tables
Caio Marcelo de Oliveira Filho [Thu, 23 May 2019 21:17:59 +0000 (14:17 -0700)]
iris: Compact binding tables

Change the iris_binding_table to keep track of what surfaces are
actually going to be used, then assign binding table indices just for
those.  Reducing unused bytes on those are valuable because we use a
reduced space for those tables in Iris.

The rest of the driver can go from "group indices" (i.e. UBO #2) to
BTI and vice-versa using helper functions.  The value
IRIS_SURFACE_NOT_USED is returned to indicate a certain group index is
not used or a certain BTI is not valid.

The environment variable INTEL_DISABLE_COMPACT_BINDING_TABLE can be
set to skip compacting binding table.

v2: (all from Ken)
    Use BITFIELD64_MASK helper. Improve comments.
    Assert all group is marked as used when we have indirects.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Create an enum for the surface groups
Caio Marcelo de Oliveira Filho [Thu, 23 May 2019 15:44:29 +0000 (08:44 -0700)]
iris: Create an enum for the surface groups

This will make convenient to handle compacting and printing the
binding table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Handle binding table in the driver
Caio Marcelo de Oliveira Filho [Thu, 23 May 2019 05:17:27 +0000 (22:17 -0700)]
iris: Handle binding table in the driver

Stop using brw_compiler to lower the final binding table indices for
surface access.  This is done by simply not setting the
'prog_data->binding_table.*_start' fields.  Then make the driver
perform this lowering.

This is a better place to perfom the binding table assignments, since
the driver has more information and will also later consume those
assignments to upload resources.

This also prepares us for two changes: use ibc without having to
implement binding table logic there; and remove unused entries from
the binding table.

Since the `block` field in brw_ubo_range now refers to the final
binding table index, we need to adjust it before using to index
shs->constbuf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Pull brw_nir_analyze_ubo_ranges() call out setup_uniforms
Caio Marcelo de Oliveira Filho [Thu, 23 May 2019 08:08:15 +0000 (01:08 -0700)]
iris: Pull brw_nir_analyze_ubo_ranges() call out setup_uniforms

We'll change iris to perform lowering of the binding table indices
earlier (before the backend kick in), but the backend compiler uses
the result of the analysis to identify load_ubo intrinsics, so we do
the analysis after the lowering to have the right indices.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agospirv: Implement OpPtrEqual, OpPtrNotEqual and OpPtrDiff
Caio Marcelo de Oliveira Filho [Thu, 16 May 2019 22:17:31 +0000 (15:17 -0700)]
spirv: Implement OpPtrEqual, OpPtrNotEqual and OpPtrDiff

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir: Add functions to subtract and compare addresses
Caio Marcelo de Oliveira Filho [Thu, 16 May 2019 22:11:07 +0000 (15:11 -0700)]
nir: Add functions to subtract and compare addresses

v2: Fix comparing addresses from formats that have more than one
    component by using nir_ball_iequal().  (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir: Add nir_ball_iequal() helper
Caio Marcelo de Oliveira Filho [Fri, 31 May 2019 20:48:34 +0000 (13:48 -0700)]
nir: Add nir_ball_iequal() helper

Similar to nir_bany_inequal().  Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agomesa: ARB program parser should clean parameters
Sergii Romantsov [Tue, 28 May 2019 09:24:36 +0000 (12:24 +0300)]
mesa: ARB program parser should clean parameters

Program parser allocates parameter list.
In case of parsing error some variables will not be freed.
Patch adds freeing of it.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2 years agofreedreno/ir3: fix counting and printing for half registers.
Hyunjun Ko [Sat, 4 May 2019 13:23:03 +0000 (13:23 +0000)]
freedreno/ir3: fix counting and printing for half registers.

v2: defining 0x100 and use this for setting the FS_OUTPUT_REG.HALF_PRECISION
Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: Fix up the half reg source even when src instr==NULL
Neil Roberts [Fri, 15 Mar 2019 13:32:27 +0000 (14:32 +0100)]
freedreno/ir3: Fix up the half reg source even when src instr==NULL

Previously the loop for assigning registers was bailing out early if
the register had a null source. I think the intention is that in this
case it isn’t necessary to assign a register. However it was also
missing out the part to fix up the types. This can happen if the
instruction is copy propagated to be a move from a constant half-float
input register. In that case it still needs to fix up the types.

Fixes assert in
dEQP-GLES3.functional.shaders.invariance.highp.subexpression_precision_mediump

when lowering the precision of the variables.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: Add a 16-bit implementation of nir_op_imul
Neil Roberts [Thu, 28 Feb 2019 15:13:56 +0000 (16:13 +0100)]
freedreno/ir3: Add a 16-bit implementation of nir_op_imul

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: set dst type of alu instructions correctly.
Hyunjun Ko [Tue, 19 Mar 2019 07:17:40 +0000 (07:17 +0000)]
freedreno/ir3: set dst type of alu instructions correctly.

Though it should be fixed in RA pass, it needs to be set correctly from
the beginning according to the bitsize of NIR dest.

v2: Would be better for mad,fddx,fddy to fixup later in RA pass.

[small cleanup of fallout from imov/fmov removal fallout]
Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: adjust the bitsize of regs when an array loading.
Hyunjun Ko [Mon, 22 Apr 2019 06:16:48 +0000 (06:16 +0000)]
freedreno/ir3: adjust the bitsize of regs when an array loading.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: convert back to 32-bit values for half constant registers.
Hyunjun Ko [Thu, 21 Mar 2019 08:30:11 +0000 (17:30 +0900)]
freedreno/ir3: convert back to 32-bit values for half constant registers.

It seems to handle only 32-bit values for half constant registers
within floating point opcodes according to the blob driver.
So we need to convert back to 32-bit values from 16-bit values, when a
lower precision pass is in effect.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: check the type of regs of absneg opcode in is_same_type_mov.
Hyunjun Ko [Mon, 15 Apr 2019 03:42:23 +0000 (03:42 +0000)]
freedreno/ir3: check the type of regs of absneg opcode in is_same_type_mov.

If the type of dest reg and src reg of absneg opcode are different,
it shouldn't be considered as same type mov.

This patch becomes meaningful when we start to use mediump information for
doing precision lowering to 16bit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: set proper dst type for uniform according to the type of nir dest.
Hyunjun Ko [Tue, 26 Feb 2019 08:33:34 +0000 (08:33 +0000)]
freedreno/ir3: set proper dst type for uniform according to the type of nir dest.

eg. uniform mediump vec4 f;

This patch means nothing since there's no mediump lowering pass for now,
but will be meaningful when the pass land in the near future.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: Use output type size to set OUTPUT_REG_HALF_PRECISION
Neil Roberts [Tue, 4 Dec 2018 17:32:15 +0000 (18:32 +0100)]
freedreno/ir3: Use output type size to set OUTPUT_REG_HALF_PRECISION

Previously the A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION was set depending
on whether half_precision was set in the shader key. With support for
mediump precision, it is possible to have different outputs use
different precisions. That means we can’t have a global shader state
to specify it. Instead it now tries to copy the half-float-ness
from the nir_variable for the output into the ir3_shader_variant. This
is then used to decide whether to set half-precision for each output.

The a6xx version is copied from the a5xx code but it has not been
tested.

v2. [Hyunjun Ko (zzoon@igalia.com)] There's the half flag recently
added, which represents precision based on IR3_REG_HALF. Now use this
flag to avoid duplication.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: Fix loading half-float immediate vectors
Neil Roberts [Sun, 2 Dec 2018 17:15:52 +0000 (18:15 +0100)]
freedreno/ir3: Fix loading half-float immediate vectors

Previously the code to load from a constant instruction was always
using the u32 pointer. If the constant is actually a 16-bit source
this would end up with the wrong values because the pointer would be
offset by the wrong size. This fixes it to use the u16 pointer.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/ir3: immediately schedule meta instructions
Rob Clark [Tue, 28 May 2019 16:42:26 +0000 (09:42 -0700)]
freedreno/ir3: immediately schedule meta instructions

The aren't real instructions, and don't change # of live values, so no
point in them competing with real instructions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: scheduler improvements
Rob Clark [Thu, 30 May 2019 17:44:16 +0000 (10:44 -0700)]
freedreno/ir3: scheduler improvements

For instructions that increase the # of live values, apply a threshold
to avoid scheduling them too early.  And factor the net change of # of
live values that would result from scheduling an instruction, to
prioritize instructions that reduce number of live values as the number
of live values increases.

For manhattan:

  total instructions in shared programs: 27869 -> 28413 (1.95%)
  instructions in affected programs: 26756 -> 27300 (2.03%)
  helped: 102
  HURT: 87

  total full in shared programs: 1903 -> 1719 (-9.67%)
  full in affected programs: 1390 -> 1206 (-13.24%)
  helped: 124
  HURT: 9

The reduction in register usage nets ~20% gain in manhattan.  (So
getting mediump support should be a huge win for gles gfxbench.)

Also significantly helps some of the more complex shadertoy shaders,
like IQ's Piano (32 to 18 regs, doubles fps).

The effect is less pronounced on smaller shaders.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: sched should mark outputs used
Rob Clark [Fri, 24 May 2019 16:19:55 +0000 (09:19 -0700)]
freedreno/ir3: sched should mark outputs used

Account for shader outputs and values live in any direct/indirect
successor block.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agomesa: EXT_dsa add selectorless matrix stack functions
Pierre-Eric Pelloux-Prayer [Tue, 7 May 2019 09:20:51 +0000 (11:20 +0200)]
mesa: EXT_dsa add selectorless matrix stack functions

Allows the legacy matrix stacks to be manipulated without disturbing the
matrix mode selector.

Adapted from a patch from Chris Forbes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: factor out enum -> matrix stack lookup
Pierre-Eric Pelloux-Prayer [Tue, 7 May 2019 09:20:20 +0000 (11:20 +0200)]
mesa: factor out enum -> matrix stack lookup

Split this out from glMatrixMode since we're about to need it
independently for EXT_DSA.

Adapted from Chris Forbes commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: add new EXT_direct_state_access tokens
Timothy Arceri [Thu, 16 Aug 2018 01:20:37 +0000 (11:20 +1000)]
mesa: add new EXT_direct_state_access tokens

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoglapi: add EXT_direct_state_access
Chris Forbes [Thu, 17 Jan 2013 09:02:39 +0000 (22:02 +1300)]
glapi: add EXT_direct_state_access

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: add a list of EXT_direct_state_access to dispatch sanity
Timothy Arceri [Sat, 8 Sep 2018 04:01:16 +0000 (14:01 +1000)]
mesa: add a list of EXT_direct_state_access to dispatch sanity

This extension is huge and this gives us a TODO list of functions
to implement.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoradeonsi: init sctx->dma_copy before using it
Pierre-Eric Pelloux-Prayer [Fri, 31 May 2019 12:39:46 +0000 (14:39 +0200)]
radeonsi: init sctx->dma_copy before using it

Commit a1378639ab19 reordered context functions initializations but broke
sctx->b.resource_copy_region init when using AMD_DEBUG=forcedma.

In this case sctx->dma_copy was assigned a value after being used in:
   sctx->b.resource_copy_region = sctx->dma_copy;

This commit moves the FORCE_DMA special case after sctx->dma_copy initialization.

See https://bugs.freedesktop.org/show_bug.cgi?id=110422

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2 years agod3dadapter9: Revert to old throttling limit value
Axel Davy [Sun, 26 May 2019 20:59:30 +0000 (22:59 +0200)]
d3dadapter9: Revert to old throttling limit value

Recently PIPE_CAP_MAX_FRAMES_IN_FLIGHT was changed from 2
to 1:
20909284f204091757c050aa40cfffaf3f981b9c

No driver seems to overwrite the default value.

One user reports severe regressions for some games.
For now, revert to the value 2 for nine.

Cc: "19.1" mesa-stable@lists.freedesktop.org
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
2 years agoac: use amdgpu-flat-work-group-size
Marek Olšák [Fri, 31 May 2019 19:38:39 +0000 (15:38 -0400)]
ac: use amdgpu-flat-work-group-size

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>