mesa.git
23 months agomeson: move the generic symbols check arguments to a common variable
Eric Engestrom [Tue, 29 Oct 2019 21:32:05 +0000 (21:32 +0000)]
meson: move the generic symbols check arguments to a common variable

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
23 months agomeson: add variable to control the symbols checks
Eric Engestrom [Tue, 29 Oct 2019 14:21:08 +0000 (14:21 +0000)]
meson: add variable to control the symbols checks

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
23 months agomesa: fix call to _mesa_lookup_vao_err
Pierre-Eric Pelloux-Prayer [Tue, 5 Nov 2019 17:35:01 +0000 (18:35 +0100)]
mesa: fix call to _mesa_lookup_vao_err

Fixes: 3e842a0b0ea ("mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2055
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
23 months agomeson: Add dep_glvnd to egl deps when building with glvnd
Dylan Baker [Thu, 10 Oct 2019 22:10:56 +0000 (15:10 -0700)]
meson: Add dep_glvnd to egl deps when building with glvnd

Otherwise if glvnd is not installed systemwide, but only in a prefix,
it's headers wont be found. This happens because if it's headers are in
/usr/include/ then another dependence will provide the necessary -I
arguments and compilation will work.

Fixes: 035ec7a2bb2d5e413ac945b8f012185a0e187d5e
       ("meson: Add support for EGL glvnd")
Acked-by: Eric Engestrom <eric@engestrom.ch>
23 months agoutil/u_endian: Add error checks
Dylan Baker [Thu, 24 Oct 2019 17:16:15 +0000 (10:16 -0700)]
util/u_endian: Add error checks

As suggested by Eric Engestrom and Michel Dänzer.

23 months agoutil: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIAN
Dylan Baker [Sat, 10 Nov 2018 00:23:08 +0000 (16:23 -0800)]
util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIAN

As requested by Tim.

This was generated with:
grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g

v2: - add this patch

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agogallium/osmesa: Use PIPE_ARCH_*_ENDIAN instead of little_endian function
Dylan Baker [Tue, 22 Oct 2019 18:30:09 +0000 (11:30 -0700)]
gallium/osmesa: Use PIPE_ARCH_*_ENDIAN instead of little_endian function

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agomesa/main: delete now unused _mesa_little_endian
Dylan Baker [Thu, 6 Sep 2018 22:15:40 +0000 (15:15 -0700)]
mesa/main: delete now unused _mesa_little_endian

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agomesa/swrast: replace instances of _mesa_little_endian with preprocessor
Dylan Baker [Thu, 6 Sep 2018 22:15:13 +0000 (15:15 -0700)]
mesa/swrast: replace instances of _mesa_little_endian with preprocessor

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agomesa/main: replace uses of _mesa_little_endian with preprocessor
Dylan Baker [Thu, 6 Sep 2018 22:14:24 +0000 (15:14 -0700)]
mesa/main: replace uses of _mesa_little_endian with preprocessor

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agoutil/u_endian: set PIPE_ARCH_*_ENDIAN to 1
Dylan Baker [Thu, 6 Sep 2018 22:13:22 +0000 (15:13 -0700)]
util/u_endian: set PIPE_ARCH_*_ENDIAN to 1

This will allow it to be used as a drop in replacement for
_mesa_little_endian in a number of cases.

v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN,
      define the one that reflects the host system to 1 and the other to 0
    - replace all uses of #ifdef, #ifndef, and #if defined() with #if
      and #if ! with PIPE_ARCH_*_ENDIAN

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agoutil/u_endian: Use _WIN32 instead of _MSC_VER
Dylan Baker [Mon, 8 Jul 2019 21:25:16 +0000 (14:25 -0700)]
util/u_endian: Use _WIN32 instead of _MSC_VER

_WIN32 is defined by basically all windows compilers (MSVC, ICL, MinGW),
wereas _MSC_VER is not defined by MinGW. Without this change MinGW falls
through and doesn't define PIPE_ARCH at all, and is caught by some extra
code in gallium.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agodri/osmesa: use preprocessor for selecting endian code paths
Dylan Baker [Thu, 6 Sep 2018 21:23:34 +0000 (14:23 -0700)]
dri/osmesa: use preprocessor for selecting endian code paths

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agor100: Use preprocessor to select big vs little endian paths
Dylan Baker [Thu, 6 Sep 2018 21:17:51 +0000 (14:17 -0700)]
r100: Use preprocessor to select big vs little endian paths

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agor200: use preprocessor for big vs little endian checks
Dylan Baker [Thu, 6 Sep 2018 21:17:12 +0000 (14:17 -0700)]
r200: use preprocessor for big vs little endian checks

Instead of using a function at runtime we can just build the right code
for the right platform.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
23 months agosvga: check return value of define_query_vgpu{9,10}
Philipp Sieweck [Tue, 15 Oct 2019 19:45:39 +0000 (21:45 +0200)]
svga: check return value of define_query_vgpu{9,10}

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
23 months agogitlab-ci: Run only LAVA jobs in special-named branches
Tomeu Vizoso [Fri, 1 Nov 2019 08:36:49 +0000 (09:36 +0100)]
gitlab-ci: Run only LAVA jobs in special-named branches

Run only jobs needed for testing on LAVA devices if a branch starts with
lava-ci-.

This allows developers to have faster test cycles as these pipelines
take only a bit above 8 minutes. Also has the advantage of conserving
resources.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
23 months agomesa: add EXT_dsa glGetVertexArray* 4 functions
Pierre-Eric Pelloux-Prayer [Sat, 26 Oct 2019 08:42:07 +0000 (10:42 +0200)]
mesa: add EXT_dsa glGetVertexArray* 4 functions

The implementation doesn't share much with get.c because:
  * the refactoring needed for get.c to not depend on ctx->Array.VAO would
    be quite large
  * glGetVertexArray* would still need to filter pname to only accept the one
    specified by the spec
  * these functions are getter, the implementation is trivial (the complexity
    is in the correct filtering of pname input)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: extract helper function from _mesa_GetPointerv
Pierre-Eric Pelloux-Prayer [Mon, 28 Oct 2019 14:31:02 +0000 (15:31 +0100)]
mesa: extract helper function from _mesa_GetPointerv

Will be used by EXT_dsa gllGetVertexArrayPointervEXT implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: add EXT_dsa EnableVertexArrayAttribEXT / DisableVertexArrayAttribEXT
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 14:11:21 +0000 (16:11 +0200)]
mesa: add EXT_dsa EnableVertexArrayAttribEXT / DisableVertexArrayAttribEXT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: add EXT_dsa glEnableVertexArrayEXT / glDisableVertexArrayEXT
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 13:20:31 +0000 (15:20 +0200)]
mesa: add EXT_dsa glEnableVertexArrayEXT / glDisableVertexArrayEXT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: add gl_vertex_array_object parameter to client state helpers
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 13:05:43 +0000 (15:05 +0200)]
mesa: add gl_vertex_array_object parameter to client state helpers

This will allow to use the same helper for the EXT_direct_state_access
implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: add EXT_dsa glVertexArray* functions implementation
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 12:29:46 +0000 (14:29 +0200)]
mesa: add EXT_dsa glVertexArray* functions implementation

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: add vao/vbo lookup helper for EXT_dsa
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 12:28:21 +0000 (14:28 +0200)]
mesa: add vao/vbo lookup helper for EXT_dsa

Add a single helper dealing with the lookup of both the vao
and the vbo to avoid duplicating this code in all the
glVertexArray* functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 13:20:09 +0000 (15:20 +0200)]
mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa

ARB_dsa and EXT_dsa slightly differs when an uninitialized VAO
is requested.
In this case ARB_dsa fails while EXT_dsa requires to initialize
the object.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: add EXT_dsa glVertexArray* functions declarations
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 09:06:21 +0000 (11:06 +0200)]
mesa: add EXT_dsa glVertexArray* functions declarations

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agomesa: pass vao as a function paramter
Pierre-Eric Pelloux-Prayer [Fri, 25 Oct 2019 08:46:43 +0000 (10:46 +0200)]
mesa: pass vao as a function paramter

This change will allow reusing the same function for the
EXT_direct_state_access implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agogitlab-ci: Set arm job CCACHE_DIR properly
Michel Dänzer [Mon, 4 Nov 2019 11:30:12 +0000 (12:30 +0100)]
gitlab-ci: Set arm job CCACHE_DIR properly

$PWD doesn't work for variables:, it ended up as "/ccache", always
starting with an empty cache.

v2:
* Use relative path and realpath
v3:
* Use $CI_PROJECT_DIR (Eric Anholt)
* Clear ccache stats in before_script if the cache is in $CI_PROJECT_DIR

Fixes: c9df92bf795a "ci: Switch over to an autoscaling GKE cluster for
                     builds."
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
23 months agonir: Handle image arrays when setting variable data
Kenneth Graunke [Tue, 5 Nov 2019 01:14:10 +0000 (17:14 -0800)]
nir: Handle image arrays when setting variable data

Fixes a ton of regressions in image load store tests.

Fixes: 4319cc8c0f5 ("nir: pack nir_variable::data::xfb_*")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agointel/compiler: remove the operand restriction for src1 on GLK
Paulo Zanoni [Fri, 1 Nov 2019 21:28:48 +0000 (14:28 -0700)]
intel/compiler: remove the operand restriction for src1 on GLK

Commit 5847de6e9afe implemented a restriction that applies to ICL, but
wrongly marked it as also applying to GLK. Reviewers or MR !1125
pointed this, and the commit history shows removal of GLK to parts of
the patch, but it turns there was still a left-over GLK check in the
code.

This code was breaking some of the i8vec2 tests on GLK, for example:
  dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2

Removing the GLK check solves the issue for GLK. I don't see a reason
on why implementing this restriction would actually break GLK, so
there's still more to investigate here since this bug may be affecting
ICL+, but let's apply the real GLK fix while we analyze and discuss
the other possible issues.

Fixes: 5847de6e9afe ("intel/compiler: don't use byte operands for src1
on ICL")
BSpec: 3017
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
23 months agonir: pack nir_variable::data::xfb_*
Marek Olšák [Fri, 25 Oct 2019 19:18:32 +0000 (15:18 -0400)]
nir: pack nir_variable::data::xfb_*

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agonir: pack nir_variable::data::stream
Marek Olšák [Fri, 25 Oct 2019 18:55:06 +0000 (14:55 -0400)]
nir: pack nir_variable::data::stream

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agonir/algebraic: Mark other comparison exact when removing a == a
Ian Romanick [Thu, 24 Oct 2019 21:41:20 +0000 (14:41 -0700)]
nir/algebraic: Mark other comparison exact when removing a == a

This prevents some additional optimizations that would change the
original result.  This includes things like (b < a && b < c) => b <
min(a, c) and !(a < b) => b >= a.  Both of these optimizations were
specifically observed in the piglit tests added in piglit!160.

This was discovered while investigating
https://gitlab.freedesktop.org/mesa/mesa/issues/1958.  However, the
problem in that issue was Chrome or Angle is replacing calls to isnan()
with some stuff that we (correctly) optimize to false.  If they had left
the calls to isnan() alone, everything would have just worked.

No shader-db changes on any Intel platform.

I also tried marking the comparison generated by the isnan() function
precise.  The precise marker "infects" every computation involved in
calculating the parameter to the isnan() function, and this severely
hurt all of the (few) shaders in shader-db that use isnan().

I also considered adding a new ir_unop_isnan opcode that would implement
the functionality.  During GLSL IR-to-NIR translation, the resulting
comparison operation would be marked exact (and the samething would need
to happen in SPIR-V translation).

This approach taken by this patch seemed easier, but we may want to do
the ir_unop_isnan thing anyway.

Fixes: d55835b8bdf ("nir/algebraic: Add optimizations for "a == a && a CMP b"")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agonir/algebraic: Add the ability to mark a replacement as exact
Ian Romanick [Thu, 24 Oct 2019 20:41:59 +0000 (13:41 -0700)]
nir/algebraic: Add the ability to mark a replacement as exact

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agocompiler: make variable::data::binding unsigned
Marek Olšák [Fri, 25 Oct 2019 20:36:15 +0000 (16:36 -0400)]
compiler: make variable::data::binding unsigned

Nothing seems to set a negative value.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agost/mesa: call nir_lower_flrp only once per shader
Marek Olšák [Fri, 25 Oct 2019 04:15:37 +0000 (00:15 -0400)]
st/mesa: call nir_lower_flrp only once per shader

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agost/mesa: call nir_opt_access only once
Marek Olšák [Fri, 25 Oct 2019 04:06:34 +0000 (00:06 -0400)]
st/mesa: call nir_opt_access only once

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
23 months agoac: add missing Arcturus to the info of pc lines
Leo Liu [Mon, 4 Nov 2019 16:18:46 +0000 (11:18 -0500)]
ac: add missing Arcturus to the info of pc lines

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
23 months agopanfrost/ci: Update T760 expectations
Alyssa Rosenzweig [Mon, 4 Nov 2019 20:35:23 +0000 (15:35 -0500)]
panfrost/ci: Update T760 expectations

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Extend default_phys_reg to !32-bit
Alyssa Rosenzweig [Thu, 31 Oct 2019 18:57:54 +0000 (14:57 -0400)]
pan/midgard: Extend default_phys_reg to !32-bit

We can pass through a size.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Extend swizzle packing for vec4/16-bit
Alyssa Rosenzweig [Thu, 31 Oct 2019 18:56:45 +0000 (14:56 -0400)]
pan/midgard: Extend swizzle packing for vec4/16-bit

We would like to pack not just xyzw swizzles but also efgh swizzles.
This should work for vec4/16-bit. More work will be needed to pack
swizzles for vec8/16-bit and even more work for 8-bit, of course.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Extend offset_swizzle to non-32-bit
Alyssa Rosenzweig [Thu, 31 Oct 2019 18:57:35 +0000 (14:57 -0400)]
pan/midgard: Extend offset_swizzle to non-32-bit

We take a size parameter; use it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: offset_swizzle doesn't need dstsize
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:44:54 +0000 (10:44 -0500)]
pan/midgard: offset_swizzle doesn't need dstsize

This argument should be omitted.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Add bizarre corner case
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:40:37 +0000 (10:40 -0500)]
pan/midgard: Add bizarre corner case

Someone really needs to look into this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Compute bundle interference
Alyssa Rosenzweig [Tue, 22 Oct 2019 01:32:35 +0000 (21:32 -0400)]
pan/midgard: Compute bundle interference

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Fix quadword_count handling
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:32:49 +0000 (10:32 -0500)]
pan/midgard: Fix quadword_count handling

Spilling can mess with this considerably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Validate tags when branching
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:09:31 +0000 (10:09 -0500)]
pan/midgard: Validate tags when branching

Midgard prefetches instructions based on tag (ALU, LD/ST, texture *
size). To do so, the shader descriptor specifies the tag of the first
instruction, all instructions specify the tag of the next linear
instruction is, and all branches explicitly specify the tag of the
branch target.

If you mess this up, you get an INSTR_TYPE_MISMATCH, which unambiguously
refers to this problem, but it's still annoying to try to work out all
the branch targets in your head to debug.

Instead, let's track the tags of various blocks over time, so we can
automatically validate tags of branch targets, to make
INSTR_TYPE_MISMATCH issues immediately obvious in a disassembly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agoaco: fix accidential reordering of instructions when scheduling
Daniel Schürmann [Thu, 31 Oct 2019 16:33:35 +0000 (17:33 +0100)]
aco: fix accidential reordering of instructions when scheduling

Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
23 months agoaco: only use single-dword loads/stores for spilling
Daniel Schürmann [Fri, 1 Nov 2019 08:06:26 +0000 (09:06 +0100)]
aco: only use single-dword loads/stores for spilling

Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
23 months agoaco: fix immediate offset for spills if scratch is used
Daniel Schürmann [Thu, 31 Oct 2019 12:25:44 +0000 (13:25 +0100)]
aco: fix immediate offset for spills if scratch is used

Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
23 months agoanv: Properly handle host query reset of performance queries
Lionel Landwerlin [Wed, 30 Oct 2019 11:51:08 +0000 (13:51 +0200)]
anv: Properly handle host query reset of performance queries

The host query reset entry point didn't use the availability offset
for performance queries.

To fix this, reorder the availability of performance queries to match
other queries.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
23 months agostate_tracker: Handle texture view min level in st_generate_mipmap()
Paul Gofman [Mon, 4 Nov 2019 12:31:10 +0000 (15:31 +0300)]
state_tracker: Handle texture view min level in st_generate_mipmap()

Signed-off-by: Paul Gofman <gofmanp@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
23 months agoiris: try to set the specified tiling when importing a dmabuf
James Xiong [Thu, 4 Apr 2019 15:27:33 +0000 (08:27 -0700)]
iris: try to set the specified tiling when importing a dmabuf

When importing a dmabuf with a specified tiling, the dmabuf user
should always try to set the tiling mode because: 1) the exporter
can set tiling AFTER exporting/importing. 2) a dmabuf could be
exported from a kernel driver other than i915, in this case the
dmabuf user and exporter need to set tiling separately.

This patch fixes a problem when running vkmark under weston with
iris on ICL, it crashed to console with the following assert. i965
doesn't have this problem as it always tries to set the specified
tiling mode.

weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
23 months agoiris: Fix "Force Zero RTA Index Enable" setting again
Kenneth Graunke [Mon, 4 Nov 2019 07:50:38 +0000 (23:50 -0800)]
iris: Fix "Force Zero RTA Index Enable" setting again

In 2ca0d913ea8, we began updating cso_fb->layers to the actual layer
count, rather than 0.  This fixed cases where we were setting "Force
Zero RTA Index Enable" even when doing layered rendering.  Sadly, it
also broke the check entirely: cso_fb->layers is now 1 for non-layered
cases, but the Force Zero RTA Index check was still comparing for 0.

Fixes: 2ca0d913ea8 ("iris: Fix framebuffer layer count")
23 months agonir: correct use of identity check in python
Dylan Baker [Fri, 25 Oct 2019 20:48:38 +0000 (13:48 -0700)]
nir: correct use of identity check in python

Python has the identity operator `is`, and the equality operator `==`.
Using `is` with strings sometimes works in CPython due to optimizations
(they have some kind of cache), but it may not always work.

Fixes: 96c4b135e34d0804e41bfbc28fc1b5050c49d71e
       ("nir/algebraic: Don't put quotes around floating point literals")
Reviewed-by: Matt Turner <mattst88@gmail.com>
23 months agopanfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASK
Boris Brezillon [Mon, 4 Nov 2019 10:57:22 +0000 (11:57 +0100)]
panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASK

MALI_DEPTH_TEST should only be set when depth->writemask is true,
not when the depth test is enabled. Let's rename the flag and patch
panfrost_bind_depth_stencil_state() to do the right thing.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agovulkan: bump headers/registry to 1.1.127
Lionel Landwerlin [Mon, 4 Nov 2019 08:21:00 +0000 (10:21 +0200)]
vulkan: bump headers/registry to 1.1.127

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
23 months agoradv: fix compute pipeline keys when optimizations are disabled
Samuel Pitoiset [Fri, 1 Nov 2019 08:34:12 +0000 (09:34 +0100)]
radv: fix compute pipeline keys when optimizations are disabled

If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.

Fixes: ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
23 months agonv50/ir: fix crash in isUniform for undefined values
Karol Herbst [Sat, 2 Nov 2019 23:57:28 +0000 (00:57 +0100)]
nv50/ir: fix crash in isUniform for undefined values

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
23 months agomesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv
Lionel Landwerlin [Fri, 1 Nov 2019 17:43:00 +0000 (19:43 +0200)]
mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agolima: set dithering flag when necessary
Vasily Khoruzhick [Sat, 26 Oct 2019 02:08:57 +0000 (19:08 -0700)]
lima: set dithering flag when necessary

Bit 13 in aux1 enables dithering

Reviewed-by: Qiang.Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
23 months agoglsl: encode struct/interface types better
Marek Olšák [Thu, 31 Oct 2019 00:38:44 +0000 (20:38 -0400)]
glsl: encode struct/interface types better

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
23 months agoglsl: encode array types better
Marek Olšák [Thu, 31 Oct 2019 00:27:08 +0000 (20:27 -0400)]
glsl: encode array types better

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
23 months agoglsl: encode explicit_stride for basic types better
Marek Olšák [Thu, 31 Oct 2019 00:22:49 +0000 (20:22 -0400)]
glsl: encode explicit_stride for basic types better

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
23 months agoglsl: encode vector_elements and matrix_columns better
Marek Olšák [Thu, 31 Oct 2019 00:18:05 +0000 (20:18 -0400)]
glsl: encode vector_elements and matrix_columns better

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
23 months agoglsl: encode/decode types using a union with bitfields for readability
Marek Olšák [Thu, 31 Oct 2019 00:15:36 +0000 (20:15 -0400)]
glsl: encode/decode types using a union with bitfields for readability

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
23 months agolima: ignore flags while looking for BO in cache
Vasily Khoruzhick [Fri, 25 Oct 2019 05:14:05 +0000 (22:14 -0700)]
lima: ignore flags while looking for BO in cache

Any BO would work, we don't have any BO types yet anyway. Moreover
lima_submit_add_bo() changes BO flags so they won't match allocation
flags.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
23 months agolima: align size before trying to fetch BO from cache
Vasily Khoruzhick [Fri, 25 Oct 2019 05:12:30 +0000 (22:12 -0700)]
lima: align size before trying to fetch BO from cache

Otherwise we may be looking in wrong bucket

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
23 months agolima: add debug prints for BO cache
Vasily Khoruzhick [Fri, 25 Oct 2019 03:16:06 +0000 (20:16 -0700)]
lima: add debug prints for BO cache

LIMA_DEBUG=bocache now activates debug prints for BO allocation,
destruction and BO cache.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
23 months agopan/midgard: Use fp32 blend shaders
Alyssa Rosenzweig [Thu, 31 Oct 2019 19:50:45 +0000 (15:50 -0400)]
pan/midgard: Use fp32 blend shaders

Clearly we do want to have fp16 at some point ... but I kind of give up
debugging and it turns out the issues with fp16 support in 'frost are so
deeply rooted that I might as well disable this non-opt and land
LCRA now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agoradv: Close all unnecessary fds in secure compile.
Bas Nieuwenhuizen [Fri, 1 Nov 2019 00:07:02 +0000 (01:07 +0100)]
radv: Close all unnecessary fds in secure compile.

The seccomp filter allows read/write, let us make sure nobody can
do anything with this.

Fixes: cff53da3748 "radv: enable secure compile support"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
23 months agoanv: remove incorrect polygonMode=point early-out
Erik Faye-Lund [Mon, 28 Oct 2019 15:25:10 +0000 (16:25 +0100)]
anv: remove incorrect polygonMode=point early-out

This is incorrect, because polygonMode only applies if the final
primitive type is a polygon; polygonMode doesn't apply to
line-primitives as the comment suggests.

The Vulkan 1.1 spec, section 26.11, "Polygons" defines that polygons are
separate from points and line segments:

" A polygon results from the decomposition of a triangle strip, triangle
  fan or a series of independent triangles. Like points and line segments,
  polygon rasterization is controlled by several variables in the
  VkPipelineRasterizationStateCreateInfo structure. "

Further, section 26.11.2, "Polygon Mode", only define polygonMode to
apply to polygons:

" Possible values of the VkPipelineRasterizationStateCreateInfo::polygonMode
  property of the currently active pipeline, specifying the method of
  rasterization for polygons, are: "

This seems to clearly define that polygonMode doesn't apply to points
and lines, so let's make sure that we don't early out with the wrong
value.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
23 months agopan/midgard: Eliminate blank_alu_src
Alyssa Rosenzweig [Wed, 30 Oct 2019 20:29:28 +0000 (16:29 -0400)]
pan/midgard: Eliminate blank_alu_src

We don't need it in practice, so this is some more cleanup.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Refactor swizzles
Alyssa Rosenzweig [Sat, 26 Oct 2019 18:06:17 +0000 (14:06 -0400)]
pan/midgard: Refactor swizzles

Rather than having hw-specific swizzles encoded directly in the
instructions, have a unified swizzle arary so we can manipulate swizzles
generically.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Add a dummy source for loads
Alyssa Rosenzweig [Sat, 26 Oct 2019 19:50:38 +0000 (15:50 -0400)]
pan/midgard: Add a dummy source for loads

We want symmetry between loads and stores, so we add a dummy source. So
we get, e.g.

   st_int4 _,    val, arg_1, arg_2
   ld_int4 dest,   _, arg_1, arg_2

Semantically, this dummy source represents the data itself, as if the
load is simply a move. That means it has a swizzle that acts as a
source.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agopan/midgard: Remove OP_IS_STORE_VARY
Alyssa Rosenzweig [Sat, 26 Oct 2019 19:50:26 +0000 (15:50 -0400)]
pan/midgard: Remove OP_IS_STORE_VARY

Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
23 months agoglsl: disable lower_fragdata_array() for NIR drivers
Timothy Arceri [Wed, 30 Oct 2019 00:34:27 +0000 (11:34 +1100)]
glsl: disable lower_fragdata_array() for NIR drivers

This function was added in 7e414b58640a to work around a defect in
lower_output_reads(). As of the previous commit no NIR driver calls
lower_output_reads().

This change means we don't need the special GLSL IR style
gl_FragData handling for building the resource list in a NIR based
linker.

No shader-db change on SKL i965.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agoglsl: just use NIR to lower outputs when driver can't read outputs
Timothy Arceri [Wed, 30 Oct 2019 00:24:37 +0000 (11:24 +1100)]
glsl: just use NIR to lower outputs when driver can't read outputs

This will allow us to stop lowering gl_FragData in GLSL IR for NIR
drivers which means we won't need the special GLSL IR type
handling for building the resource list in a NIR based linker.

i965 has been doing this since b828f7a27b2b.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agolima: support indexed draw with bias
Icenowy Zheng [Tue, 22 Oct 2019 14:14:56 +0000 (22:14 +0800)]
lima: support indexed draw with bias

When doing an indexed draw with index_bias set to a non-zero value (e.g.
by glDrawElementsBaseVertex), the vertex buffer should be offseted by
index_bias vertices.

Add this offset when setting the vertex buffer address.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
23 months agoanv: Move the RT BTI flush workaround to begin_subpass
Jason Ekstrand [Wed, 30 Oct 2019 20:05:29 +0000 (15:05 -0500)]
anv: Move the RT BTI flush workaround to begin_subpass

Now that we're no longer compacting binding table entries, the only time
they can possibly change is when we actually switch subpasses.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
23 months agoanv: Stop compacting render targets in the binding table
Jason Ekstrand [Wed, 30 Oct 2019 19:07:47 +0000 (14:07 -0500)]
anv: Stop compacting render targets in the binding table

Instead, always emit one entry for every color attachment in the subpass
or one NULL if there are no color attachments.  This will let us adjust
an Ice Lake workaround so we don't get a stall on every draw call.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
23 months agoanv: Don't claim the null RT as a valid color target
Jason Ekstrand [Wed, 30 Oct 2019 20:53:11 +0000 (15:53 -0500)]
anv: Don't claim the null RT as a valid color target

If it's NULL, we can let the compiler go ahead and delete it or flag it
as NULL.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
23 months agoanv: Don't delete fragment shaders that write sample mask
Jason Ekstrand [Wed, 30 Oct 2019 20:50:51 +0000 (15:50 -0500)]
anv: Don't delete fragment shaders that write sample mask

Also, use color_outputs_valid rather than nr_color_outputs since it
should be a bit more accurate.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
23 months agoglsl: Enable textureSize for samplerExternalOES
Yevhenii Kolesnikov [Mon, 7 Oct 2019 12:59:52 +0000 (15:59 +0300)]
glsl: Enable textureSize for samplerExternalOES

From OES_EGL_image_external_essl3

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1901
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
23 months agoci: Switch over to an autoscaling GKE cluster for builds.
Eric Anholt [Mon, 21 Oct 2019 20:36:14 +0000 (13:36 -0700)]
ci: Switch over to an autoscaling GKE cluster for builds.

The GKE pool we're using is 1-3 32-core VMs, preemptible (to keep
costs down), with 8 jobs concurrent per system.  We have plenty of
memory (4G/core), so we run make -j8 to try to keep the cores busy even
when one job is in a single-threaded step (docker image download, git
clone, artifacts processing, etc.)  When all jobs are generating work
for all the cores, they'll be scheduled fairly.

The nodes in the pool have 300GB boot disks (over-provisioned in space
to provide enough iops and throughput) mounted to /ccache, and
CACHE_DIR set pointing to them.  This means that once a new
autoscaled-up node has run some jobs, it should have a hot ccache from
then on (instead of having to rely on the docker container cache
having our ccache laying around and not getting wiped out by some
other fd.o job).  Local SSDs would provide higher performance, but
unfortunately are not supported with the cluster autoscaler.

For now, the softpipe/llvmpipe test runs are still on the shared
runners, until I can get them ported onto Bas's runner so they can be
parallelized in a single job.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
23 months agoci: Make lava inherit the ccache setup of the .build script.
Eric Anholt [Mon, 28 Oct 2019 22:21:44 +0000 (15:21 -0700)]
ci: Make lava inherit the ccache setup of the .build script.

It was just duplicating the code.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
23 months agomeson: revert glvnd workaround
Eric Engestrom [Wed, 25 Sep 2019 16:38:49 +0000 (17:38 +0100)]
meson: revert glvnd workaround

This effectively reverts MR !2112.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
23 months agomeson: require glvnd 1.2.0
Eric Engestrom [Wed, 25 Sep 2019 16:42:18 +0000 (17:42 +0100)]
meson: require glvnd 1.2.0

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
23 months agogitlab-ci: build a recent enough version of GLVND (ie. 1.2.0)
Eric Engestrom [Wed, 25 Sep 2019 19:18:27 +0000 (20:18 +0100)]
gitlab-ci: build a recent enough version of GLVND (ie. 1.2.0)

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
23 months agomeson: move idep_xmlconfig_headers to xmlpool/
Eric Engestrom [Thu, 31 Oct 2019 15:35:29 +0000 (15:35 +0000)]
meson: move idep_xmlconfig_headers to xmlpool/

That's where `xmlpool_options_h` is defined, and this way we can make sure
nobody starts making use of it in the future :)

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agoanv: Use the new BO alloc API for Android
Jason Ekstrand [Thu, 31 Oct 2019 15:28:05 +0000 (10:28 -0500)]
anv: Use the new BO alloc API for Android

Fixes: a44f5ee0d8b "anv: Rework the internal BO allocation API"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
23 months agozink: emit line-width when using polygon line-mode
Erik Faye-Lund [Wed, 30 Oct 2019 12:57:21 +0000 (13:57 +0100)]
zink: emit line-width when using polygon line-mode

When switching this to dynamic state, I forgot that this also needs to
be emitted when we use a polygon-mode set to lines.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 6d30abb4f14 ("zink: use dynamic state for line-width")
23 months agoradeon: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:55:52 +0000 (00:55 +0100)]
radeon: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agor200: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:55:45 +0000 (00:55 +0100)]
r200: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agonouveau: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:55:37 +0000 (00:55 +0100)]
nouveau: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agoi915: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:55:30 +0000 (00:55 +0100)]
i915: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agodri: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:55:06 +0000 (00:55 +0100)]
dri: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agotargets/xvmc: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:54:49 +0000 (00:54 +0100)]
targets/xvmc: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agotargets/xa: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:54:38 +0000 (00:54 +0100)]
targets/xa: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
23 months agotargets/vdpau: replace xmlpool_options_h with idep_xmlconfig_headers
Eric Engestrom [Sat, 26 Oct 2019 23:54:28 +0000 (00:54 +0100)]
targets/vdpau: replace xmlpool_options_h with idep_xmlconfig_headers

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>