mesa.git
2 years agoradeonsi/gfx10: jump over the shader query atomic if the queries are disabled
Marek Olšák [Fri, 21 Jun 2019 22:38:58 +0000 (18:38 -0400)]
radeonsi/gfx10: jump over the shader query atomic if the queries are disabled

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: cosmetic changes
Marek Olšák [Fri, 14 Jun 2019 01:29:47 +0000 (21:29 -0400)]
radeonsi/gfx10: cosmetic changes

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set cache control registers
Marek Olšák [Thu, 6 Jun 2019 04:25:40 +0000 (00:25 -0400)]
radeonsi/gfx10: set cache control registers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders
Marek Olšák [Thu, 6 Jun 2019 00:20:47 +0000 (20:20 -0400)]
radeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set PA_SC_TILE_STEERING_OVERRIDE
Marek Olšák [Wed, 5 Jun 2019 19:04:45 +0000 (15:04 -0400)]
radeonsi/gfx10: set PA_SC_TILE_STEERING_OVERRIDE

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: add a workaround for stencil HTILE with mipmapping
Marek Olšák [Wed, 5 Jun 2019 05:54:46 +0000 (01:54 -0400)]
radeonsi/gfx10: add a workaround for stencil HTILE with mipmapping

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: disable DCC with MSAA
Marek Olšák [Wed, 5 Jun 2019 05:37:01 +0000 (01:37 -0400)]
radeonsi/gfx10: disable DCC with MSAA

It was only enabled for 2x MSAA anyway.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitives
Marek Olšák [Thu, 30 May 2019 00:06:16 +0000 (20:06 -0400)]
radeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitives

We need to tell PA to accept edge flags generated by the input assembler,
because decomposed primitives shouldn't draw inner edges.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix NGG GS color clamping
Marek Olšák [Wed, 29 May 2019 20:32:17 +0000 (16:32 -0400)]
radeonsi/gfx10: fix NGG GS color clamping

Just need to pass the input from ES to GS. Everything else is done.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix vertex color clamping for TES
Marek Olšák [Tue, 28 May 2019 23:55:09 +0000 (19:55 -0400)]
radeonsi/gfx10: fix vertex color clamping for TES

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: unbind NGG shaders when destroyed
Marek Olšák [Wed, 29 May 2019 02:29:08 +0000 (22:29 -0400)]
radeonsi/gfx10: unbind NGG shaders when destroyed

This fixes glsl-max-varyings, which creates shaders, draws, and then
destroys them.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: don't use the GS workaround for triangle strips w/ adjancency
Marek Olšák [Wed, 29 May 2019 02:06:52 +0000 (22:06 -0400)]
radeonsi/gfx10: don't use the GS workaround for triangle strips w/ adjancency

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: don't do the query buffer atomic for blit shaders
Marek Olšák [Wed, 29 May 2019 02:01:09 +0000 (22:01 -0400)]
radeonsi/gfx10: don't do the query buffer atomic for blit shaders

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: update spi_map if API VS (as NGG) changes and PS doesn't
Marek Olšák [Tue, 28 May 2019 23:56:08 +0000 (19:56 -0400)]
radeonsi/gfx10: update spi_map if API VS (as NGG) changes and PS doesn't

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0
Marek Olšák [Tue, 28 May 2019 23:52:53 +0000 (19:52 -0400)]
radeonsi/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: prefetch HW GS when NGG is used
Marek Olšák [Tue, 28 May 2019 22:55:30 +0000 (18:55 -0400)]
radeonsi/gfx10: prefetch HW GS when NGG is used

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoamd/common/gfx10: set DLC for llvm.amdgcn.s.buffer.load
Nicolai Hähnle [Mon, 27 May 2019 14:16:39 +0000 (16:16 +0200)]
amd/common/gfx10: set DLC for llvm.amdgcn.s.buffer.load

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix PS exports for SPI_SHADER_32_AR
Marek Olšák [Sat, 25 May 2019 02:49:27 +0000 (22:49 -0400)]
radeonsi/gfx10: fix PS exports for SPI_SHADER_32_AR

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set DLC for loads when GLC is set
Marek Olšák [Fri, 24 May 2019 22:48:39 +0000 (18:48 -0400)]
radeonsi/gfx10: set DLC for loads when GLC is set

This fixes L1 shader array cache coherency.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix shader images
Marek Olšák [Fri, 24 May 2019 21:25:04 +0000 (17:25 -0400)]
radeonsi/gfx10: fix shader images

Don't promote 2D image instructions to 3D, and don't set z=BASE_ARRAY.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set the DCC constant encoding flag
Marek Olšák [Thu, 23 May 2019 18:20:27 +0000 (14:20 -0400)]
radeonsi/gfx10: set the DCC constant encoding flag

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix intensity formats
Marek Olšák [Wed, 22 May 2019 22:21:55 +0000 (18:21 -0400)]
radeonsi/gfx10: fix intensity formats

move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: allocate GDS BOs for streamout
Marek Olšák [Wed, 5 Jun 2019 02:08:41 +0000 (22:08 -0400)]
radeonsi/gfx10: allocate GDS BOs for streamout

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: make sure GDS is idle between IBs
Marek Olšák [Wed, 5 Jun 2019 02:02:25 +0000 (22:02 -0400)]
radeonsi/gfx10: make sure GDS is idle between IBs

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement streamout
Nicolai Hähnle [Fri, 21 Sep 2018 20:07:01 +0000 (22:07 +0200)]
radeonsi/gfx10: implement streamout

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement streamout-related queries
Nicolai Hähnle [Wed, 19 Sep 2018 12:53:35 +0000 (14:53 +0200)]
radeonsi/gfx10: implement streamout-related queries

The NGG hardware pipeline doesn't track these statistics automatically,
and in fact *cannot* track them automatically when API geometry shaders
are involved, so we accumulate statistics in the shader using atomic
adds.

This implementation accumulates statistics via the memory system and
the RW buffer descriptor setup. We could use GDS, but since these
atomics aren't latency-sensitive, that basically just trades off
L2$ bandwidth vs. export bus bandwidth. One single memory transaction
per shader workgroup doesn't seem too bad. The result ring buffer in
memory is needed either way to avoid pipeline stalls.

The shader code contains the atomic unconditionally, though the
GFX10_GS_QUERY_BUF is a null buffer when no queries are active. The
atomic is simply discarded by the shader hardware in that case.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: enable the workaround for unaligned vertex fetch
Nicolai Hähnle [Mon, 1 Apr 2019 13:58:31 +0000 (15:58 +0200)]
radeonsi/gfx10: enable the workaround for unaligned vertex fetch

Yes, really. Note that non-format buffer loads are unaffected and work
just fine with unaligned pointers (as long as SH_MEM_CONFIG is setup
correctly, which amdgpu ensures).

Fixes e.g. KHR-GL45.vertex_attrib_64bit.vao

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: re-order the initialization order in si_compile_tgsi_main
Nicolai Hähnle [Thu, 20 Sep 2018 08:18:07 +0000 (10:18 +0200)]
radeonsi/gfx10: re-order the initialization order in si_compile_tgsi_main

It's useful to be able to access gs_ngg_scratch before creating the
main wrapping branch.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: apply DCC MSAA blend workaround
Nicolai Hähnle [Tue, 18 Sep 2018 12:16:43 +0000 (14:16 +0200)]
radeonsi/gfx10: apply DCC MSAA blend workaround

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_emit_global_shader_pointers
Nicolai Hähnle [Thu, 7 Feb 2019 17:53:27 +0000 (18:53 +0100)]
radeonsi/gfx10: implement si_emit_global_shader_pointers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_init_tess_factor_ring
Nicolai Hähnle [Fri, 31 Aug 2018 17:59:48 +0000 (19:59 +0200)]
radeonsi/gfx10: implement si_init_tess_factor_ring

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: initialize EXEC for TES-as-NGG (without geometry shader)
Nicolai Hähnle [Fri, 31 Aug 2018 17:59:36 +0000 (19:59 +0200)]
radeonsi/gfx10: initialize EXEC for TES-as-NGG (without geometry shader)

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: use correct VGPR for instance ID in LS shader
Nicolai Hähnle [Fri, 31 Aug 2018 17:58:35 +0000 (19:58 +0200)]
radeonsi/gfx10: use correct VGPR for instance ID in LS shader

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_shader_hs
Nicolai Hähnle [Fri, 31 Aug 2018 17:54:59 +0000 (19:54 +0200)]
radeonsi/gfx10: implement si_shader_hs

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_create_sampler_state
Nicolai Hähnle [Fri, 31 Aug 2018 17:53:52 +0000 (19:53 +0200)]
radeonsi/gfx10: implement si_create_sampler_state

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: double the number of tessellation offchip buffers per SE
Nicolai Hähnle [Thu, 30 Aug 2018 15:06:52 +0000 (17:06 +0200)]
radeonsi/gfx10: double the number of tessellation offchip buffers per SE

Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale
the number of offchip buffers accordingly.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement get_tess_ring_descriptor
Nicolai Hähnle [Tue, 28 Aug 2018 14:00:28 +0000 (16:00 +0200)]
radeonsi/gfx10: implement get_tess_ring_descriptor

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: mask DCC tile swizzle by alignment
Nicolai Hähnle [Mon, 23 Jul 2018 07:47:19 +0000 (09:47 +0200)]
radeonsi/gfx10: mask DCC tile swizzle by alignment

DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement hardware MSAA resolve
Nicolai Hähnle [Mon, 2 Jul 2018 16:50:48 +0000 (18:50 +0200)]
radeonsi/gfx10: implement hardware MSAA resolve

MSAA is only supported for 64KB_{R,Z}_X modes, so the micro tile
optimization that we use on gfx9 and earlier does not work.

Be very explicit about how the swizzle mode of the temporary surface is
selected.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: fix binding on si_update_scratch_relocs
Nicolai Hähnle [Thu, 21 Jun 2018 12:56:54 +0000 (14:56 +0200)]
radeonsi/gfx10: fix binding on si_update_scratch_relocs

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set llvm_has_working_vgpr_indexing
Nicolai Hähnle [Tue, 19 Jun 2018 15:44:24 +0000 (17:44 +0200)]
radeonsi/gfx10: set llvm_has_working_vgpr_indexing

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement load_const_buffer_desc_fast_path
Nicolai Hähnle [Fri, 1 Jun 2018 14:04:02 +0000 (16:04 +0200)]
radeonsi/gfx10: implement load_const_buffer_desc_fast_path

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: take PRIMID from the correct output when exported by GS
Nicolai Hähnle [Fri, 1 Jun 2018 14:03:31 +0000 (16:03 +0200)]
radeonsi/gfx10: take PRIMID from the correct output when exported by GS

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: change location of instance ID shader input
Nicolai Hähnle [Wed, 30 May 2018 20:47:10 +0000 (22:47 +0200)]
radeonsi/gfx10: change location of instance ID shader input

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set USER_DATA_ADDR offset for geometry shaders
Nicolai Hähnle [Wed, 30 May 2018 20:45:06 +0000 (22:45 +0200)]
radeonsi/gfx10: set USER_DATA_ADDR offset for geometry shaders

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_emit_derived_tess_state
Nicolai Hähnle [Tue, 7 May 2019 22:54:46 +0000 (00:54 +0200)]
radeonsi/gfx10: implement si_emit_derived_tess_state

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_shader_gs
Nicolai Hähnle [Wed, 8 May 2019 01:10:21 +0000 (03:10 +0200)]
radeonsi/gfx10: implement si_shader_gs

This is only used in the legacy, non-NGG path.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement preload_ring_buffers
Nicolai Hähnle [Wed, 8 May 2019 01:09:42 +0000 (03:09 +0200)]
radeonsi/gfx10: implement preload_ring_buffers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_set_ring_buffer
Nicolai Hähnle [Tue, 14 Nov 2017 15:59:35 +0000 (16:59 +0100)]
radeonsi/gfx10: implement si_set_ring_buffer

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: allow rectangle outputs from NGG primitive shader
Nicolai Hähnle [Wed, 8 May 2019 00:54:01 +0000 (02:54 +0200)]
radeonsi/gfx10: allow rectangle outputs from NGG primitive shader

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATE
Nicolai Hähnle [Tue, 7 May 2019 23:40:29 +0000 (01:40 +0200)]
radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATE

With NGG, the VGT_GS_OUT_PRIM_TYPE can change without a shader change.

The VS_STATE is required for both streamout and culling from a vertex
shader without pre-compiling outprim-specific variants.

We could consider compiling specialized variants in the future. We
could also consider compiling the NGG logic as an epilog.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: NGG geometry shader PM4 and upload
Nicolai Hähnle [Wed, 23 May 2018 20:31:41 +0000 (22:31 +0200)]
radeonsi/gfx10: NGG geometry shader PM4 and upload

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: generate geometry shaders for NGG
Nicolai Hähnle [Wed, 23 May 2018 20:20:15 +0000 (22:20 +0200)]
radeonsi/gfx10: generate geometry shaders for NGG

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: use the correct register for image descriptor dumping
Nicolai Hähnle [Wed, 13 Dec 2017 12:25:23 +0000 (13:25 +0100)]
radeonsi/gfx10: use the correct register for image descriptor dumping

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode
Nicolai Hähnle [Sun, 19 Nov 2017 14:40:12 +0000 (15:40 +0100)]
radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET
Nicolai Hähnle [Sun, 19 Nov 2017 14:24:28 +0000 (15:24 +0100)]
radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: setup registers for OpenGL compute
Nicolai Hähnle [Sat, 18 Nov 2017 20:16:26 +0000 (21:16 +0100)]
radeonsi/gfx10: setup registers for OpenGL compute

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set user data base registers
Nicolai Hähnle [Sat, 18 Nov 2017 19:55:56 +0000 (20:55 +0100)]
radeonsi/gfx10: set user data base registers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement gfx10_shader_ngg
Nicolai Hähnle [Tue, 7 May 2019 21:50:01 +0000 (23:50 +0200)]
radeonsi/gfx10: implement gfx10_shader_ngg

For pipelines without API GS. We will later expand this to cover NGG
geometry shaders as well.

Note that the vtx offset passed into the GS part is just the
vertex index multiplied by VGT_ESGS_RING_ITEMSIZE.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: add NGG registers to si_init_config
Nicolai Hähnle [Sat, 18 Nov 2017 13:32:59 +0000 (14:32 +0100)]
radeonsi/gfx10: add NGG registers to si_init_config

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: update shader-related fields in si_init_config
Nicolai Hähnle [Sat, 18 Nov 2017 13:32:34 +0000 (14:32 +0100)]
radeonsi/gfx10: update shader-related fields in si_init_config

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_shader_ps
Nicolai Hähnle [Sat, 18 Nov 2017 12:27:55 +0000 (13:27 +0100)]
radeonsi/gfx10: implement si_shader_ps

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: generate VS and TES as NGG merged ESGS shaders
Nicolai Hähnle [Thu, 16 Nov 2017 16:00:50 +0000 (17:00 +0100)]
radeonsi/gfx10: generate VS and TES as NGG merged ESGS shaders

This does not support geometry shading yet. Also missing are streamout
and NGG-specific optimizations.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: distinguish between merged shaders and multi-part shaders
Nicolai Hähnle [Fri, 17 Nov 2017 12:40:18 +0000 (13:40 +0100)]
radeonsi/gfx10: distinguish between merged shaders and multi-part shaders

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: update si_get_shader_name
Nicolai Hähnle [Fri, 17 Nov 2017 12:39:45 +0000 (13:39 +0100)]
radeonsi/gfx10: update si_get_shader_name

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: add as_ngg shader key bit
Nicolai Hähnle [Tue, 7 May 2019 21:27:24 +0000 (23:27 +0200)]
radeonsi/gfx10: add as_ngg shader key bit

Also add the shader main part NGG variant, so that in principle
we can switch between legacy in NGG modes.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_update_shaders
Nicolai Hähnle [Thu, 16 Nov 2017 16:02:41 +0000 (17:02 +0100)]
radeonsi/gfx10: implement si_update_shaders

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_build_vgt_shader_config
Nicolai Hähnle [Tue, 7 May 2019 21:23:03 +0000 (23:23 +0200)]
radeonsi/gfx10: implement si_build_vgt_shader_config

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: keep track of whether NGG is used
Nicolai Hähnle [Tue, 7 May 2019 21:00:43 +0000 (23:00 +0200)]
radeonsi/gfx10: keep track of whether NGG is used

We always use NGG by default, except when tessellation is enabled with
extreme geometry shader amplification.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: document NGG shader stages
Nicolai Hähnle [Thu, 16 Nov 2017 16:02:13 +0000 (17:02 +0100)]
radeonsi/gfx10: document NGG shader stages

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement gfx10_emit_cache_flush
Nicolai Hähnle [Thu, 16 Nov 2017 12:33:36 +0000 (13:33 +0100)]
radeonsi/gfx10: implement gfx10_emit_cache_flush

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: add si_context::emit_cache_flush
Nicolai Hähnle [Thu, 16 Nov 2017 11:16:52 +0000 (12:16 +0100)]
radeonsi/gfx10: add si_context::emit_cache_flush

The introduction of GCR_CNTL makes cache flush handling on gfx10
sufficiently different that it makes sense to just use a separate
function.

Since emit_cache_flush is called quite early during context init,
we initialize the pointer explicitly in si_create_context.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement DB registers
Nicolai Hähnle [Thu, 16 Nov 2017 10:18:52 +0000 (11:18 +0100)]
radeonsi/gfx10: implement DB registers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set CB registers
Nicolai Hähnle [Thu, 16 Nov 2017 09:22:15 +0000 (10:22 +0100)]
radeonsi/gfx10: set CB registers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: always set up sample locations
Nicolai Hähnle [Wed, 15 Nov 2017 20:29:56 +0000 (21:29 +0100)]
radeonsi/gfx10: always set up sample locations

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth textures
Nicolai Hähnle [Wed, 15 Nov 2017 20:10:28 +0000 (21:10 +0100)]
radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth textures

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement vertex format changes
Nicolai Hähnle [Wed, 15 Nov 2017 19:50:19 +0000 (20:50 +0100)]
radeonsi/gfx10: implement vertex format changes

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_set_{constant,shader}_buffer
Nicolai Hähnle [Tue, 14 Nov 2017 15:55:34 +0000 (16:55 +0100)]
radeonsi/gfx10: implement si_set_{constant,shader}_buffer

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_make_buffer_descriptor
Nicolai Hähnle [Tue, 7 May 2019 20:43:32 +0000 (22:43 +0200)]
radeonsi/gfx10: implement si_make_buffer_descriptor

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_set_mutable_tex_desc_fields
Nicolai Hähnle [Tue, 14 Nov 2017 15:36:16 +0000 (16:36 +0100)]
radeonsi/gfx10: implement si_set_mutable_tex_desc_fields

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: gfx10 can render up to 8192 layers
Nicolai Hähnle [Tue, 14 Nov 2017 15:10:10 +0000 (16:10 +0100)]
radeonsi/gfx10: gfx10 can render up to 8192 layers

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: add gfx10_make_texture_descriptor
Nicolai Hähnle [Sun, 15 Apr 2018 17:09:14 +0000 (19:09 +0200)]
radeonsi/gfx10: add gfx10_make_texture_descriptor

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: add pipe_screen::make_texture_descriptor
Nicolai Hähnle [Tue, 14 Nov 2017 15:03:48 +0000 (16:03 +0100)]
radeonsi/gfx10: add pipe_screen::make_texture_descriptor

Texture descriptors in gfx10 are very different.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: determine view->is_integer based on the pipe_format
Nicolai Hähnle [Tue, 14 Nov 2017 14:37:36 +0000 (15:37 +0100)]
radeonsi/gfx10: determine view->is_integer based on the pipe_format

It was convenient, but NUM_FORMAT no longer exists in gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: implement si_is_format_supported
Nicolai Hähnle [Tue, 14 Nov 2017 14:20:06 +0000 (15:20 +0100)]
radeonsi/gfx10: implement si_is_format_supported

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: generate gfx10_format_table.h
Nicolai Hähnle [Tue, 14 Nov 2017 14:01:13 +0000 (15:01 +0100)]
radeonsi/gfx10: generate gfx10_format_table.h

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: set MAX_ALLOC_COUNT
Nicolai Hähnle [Tue, 24 Oct 2017 11:43:30 +0000 (11:43 +0000)]
radeonsi/gfx10: set MAX_ALLOC_COUNT

The number for Vega was copied from PAL and has no effect because of MIN2.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi/gfx10: require LLVM 9
Nicolai Hähnle [Mon, 13 May 2019 19:58:30 +0000 (21:58 +0200)]
radeonsi/gfx10: require LLVM 9

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: update for new vcn enc interface
Boyuan Zhang [Wed, 13 Mar 2019 23:14:13 +0000 (19:14 -0400)]
radeon/vcn: update for new vcn enc interface

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi: enable jpeg decode for navi10
Boyuan Zhang [Tue, 5 Mar 2019 22:51:23 +0000 (17:51 -0500)]
radeonsi: enable jpeg decode for navi10

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: implement vcn 2.0 jpeg decode
Boyuan Zhang [Tue, 5 Mar 2019 22:49:57 +0000 (17:49 -0500)]
radeon/vcn: implement vcn 2.0 jpeg decode

Use direct register to implement vcn 2.0 jpeg deocde

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: add direct register bool
Boyuan Zhang [Tue, 5 Mar 2019 22:48:52 +0000 (17:48 -0500)]
radeon/vcn: add direct register bool

VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: add defines for vcn 2.0 jpeg
Boyuan Zhang [Tue, 5 Mar 2019 21:51:37 +0000 (16:51 -0500)]
radeon/vcn: add defines for vcn 2.0 jpeg

Add neccesary register defines for vcn 2.0 jpeg deocde

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: use variable to assign ib cmd
Boyuan Zhang [Sat, 2 Mar 2019 02:14:50 +0000 (21:14 -0500)]
radeon/vcn: use variable to assign ib cmd

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: implement vcn 2.0 encode
Boyuan Zhang [Sat, 2 Mar 2019 02:14:06 +0000 (21:14 -0500)]
radeon/vcn: implement vcn 2.0 encode

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: add vcn2.0 encode skeleton
Boyuan Zhang [Thu, 1 Nov 2018 19:47:58 +0000 (15:47 -0400)]
radeon/vcn: add vcn2.0 encode skeleton

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
(v2: build fix -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: move vcn1.0 specific defines to c
Boyuan Zhang [Thu, 1 Nov 2018 19:35:04 +0000 (15:35 -0400)]
radeon/vcn: move vcn1.0 specific defines to c

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: assign function pointer with ib functions
Boyuan Zhang [Wed, 31 Oct 2018 18:11:17 +0000 (14:11 -0400)]
radeon/vcn: assign function pointer with ib functions

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: add function pointer for ib functions
Boyuan Zhang [Tue, 30 Oct 2018 18:57:59 +0000 (14:57 -0400)]
radeon/vcn: add function pointer for ib functions

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon/vcn: move header related algorithm to vcn_enc
Boyuan Zhang [Tue, 30 Oct 2018 18:14:35 +0000 (14:14 -0400)]
radeon/vcn: move header related algorithm to vcn_enc

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>