mesa.git
3 years agodrisw/glx: implement getImageShm
Marc-André Lureau [Mon, 15 Jun 2015 13:07:34 +0000 (15:07 +0200)]
drisw/glx: implement getImageShm

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agodrisw: use getImageShm() if available
Marc-André Lureau [Mon, 15 Jun 2015 13:09:58 +0000 (15:09 +0200)]
drisw: use getImageShm() if available

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agodrisw: learn to query shmid handle type
Marc-André Lureau [Mon, 15 Jun 2015 12:48:27 +0000 (14:48 +0200)]
drisw: learn to query shmid handle type

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agodrisw/glx: use XShm if possible
Marc-André Lureau [Wed, 10 Jun 2015 15:58:31 +0000 (17:58 +0200)]
drisw/glx: use XShm if possible

Implements putImageShm from DRIswrastLoaderExtension.

If XShm extension is not available, or fails, it will fallback on
regular XPutImage().

Tested on Linux only with 16bpp and 32bpp visual.

(airlied: tested on 24bpp as well)

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agodrisw: use shared memory when possible
Marc-André Lureau [Wed, 10 Jun 2015 15:45:11 +0000 (17:45 +0200)]
drisw: use shared memory when possible

If drisw_loader_funcs implements put_image_shm, allocates display
target data with shared memory and display with put_image_shm().

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agodrisw: use putImageShm if available
Marc-André Lureau [Wed, 10 Jun 2015 15:34:15 +0000 (17:34 +0200)]
drisw: use putImageShm if available

If the DRIswrastLoaderExtension implements putImageShm, bind it to
drisw_loader_funcs.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agodri: add putImageShm and getImageShm to swrastLoader
Marc-André Lureau [Wed, 10 Jun 2015 15:28:47 +0000 (17:28 +0200)]
dri: add putImageShm and getImageShm to swrastLoader

Add new API to put and get an image using shared memory. Instead of only
passing the data pointer, 3 arguments are given: the shmid, the data
offset and the shmaddr.

Bump interface version.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
3 years agogallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*
Dave Airlie [Tue, 29 May 2018 01:21:38 +0000 (11:21 +1000)]
gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*

This just renames this as we want to add an shm handle which
isn't really drm related.

Originally by: Marc-André Lureau <marcandre.lureau@gmail.com>
(airlied: I used this sed script instead)
This was generated with:
 git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g'

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agogallium: move winsys handle to it's own file.
Marc-André Lureau [Tue, 29 May 2018 01:17:11 +0000 (11:17 +1000)]
gallium: move winsys handle to it's own file.

This will be used in the drisw interface later, which isn't
drm specific.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agointel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.
Francisco Jerez [Fri, 13 Jan 2017 22:01:45 +0000 (14:01 -0800)]
intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.

When using multiple RT write messages to the same RT such as for
dual-source blending or all RT writes in SIMD32, we have to set the
"Last Render Target Select" bit on all write messages that target the
last RT but only set EOT on the last RT write in the shader.
Special-casing for dual-source blend works today because that is the
only case which requires multiple RT write messages per RT.  When we
start doing SIMD32, this will become much more common so we add a
dedicated bit for it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel/fs: Replace the CINTERP opcode with a simple MOV
Francisco Jerez [Fri, 18 May 2018 22:20:43 +0000 (15:20 -0700)]
intel/fs: Replace the CINTERP opcode with a simple MOV

The only reason it was it's own opcode was so that we could detect it
and adjust the source register based on the payload setup.  Now that
we're using the ATTR file for FS inputs, there's no point in having a
magic opcode for this.

v2 (Jason Ekstrand):
 - Break the bit which removes the CINTERP opcode into its own patch

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel/fs: Use the ATTR file for FS inputs
Francisco Jerez [Tue, 26 Apr 2016 01:33:22 +0000 (18:33 -0700)]
intel/fs: Use the ATTR file for FS inputs

This replaces the special magic opcodes which implicitly read inputs
with explicit use of the ATTR file.

v2 (Jason Ekstrand):
 - Break into multiple patches
 - Change the units of the FS ATTR to be in logical scalars

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel/fs: Rename a local variable so it doesn't shadow component()
Francisco Jerez [Fri, 18 May 2018 22:13:25 +0000 (15:13 -0700)]
intel/fs: Rename a local variable so it doesn't shadow component()

v2 (Jason Ekstrand):
 - Break the refactor into its own patch

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel/eu: Remove brw_codegen::compressed_stack.
Francisco Jerez [Fri, 6 Jan 2017 03:26:13 +0000 (19:26 -0800)]
intel/eu: Remove brw_codegen::compressed_stack.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel/fs: Use groups for SIMD16 LINTERP on gen11+
Jason Ekstrand [Thu, 17 May 2018 00:33:17 +0000 (17:33 -0700)]
intel/fs: Use groups for SIMD16 LINTERP on gen11+

This is better than compression control because it naturally extends to
SIMD32.

v2:
 - Push/pop instruction state around adjusted codegen (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agointel/fs: Assert that the gen4-6 plane restrictions are followed
Jason Ekstrand [Thu, 17 May 2018 00:30:04 +0000 (17:30 -0700)]
intel/fs: Assert that the gen4-6 plane restrictions are followed

The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.

Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agotravis: Add clover llvm-6.0 build
Jan Vesely [Tue, 22 May 2018 22:36:32 +0000 (18:36 -0400)]
travis: Add clover llvm-6.0 build

v2: Don't force build using gcc-4.8
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-By: Aaron Watry <awatry@gmail.com>
3 years agoclover: Cleanup compat code for llvm < 3.9
Jan Vesely [Tue, 22 May 2018 22:27:39 +0000 (18:27 -0400)]
clover: Cleanup compat code for llvm < 3.9

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-By: Aaron Watry <awatry@gmail.com>
3 years agoclover: Fix build after llvm r332881.
Jan Vesely [Tue, 22 May 2018 21:52:30 +0000 (17:52 -0400)]
clover: Fix build after llvm r332881.

v2: fix whitespace and indentation

r332881 added an extra parameter to the emit function.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106619
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-By: Aaron Watry <awatry@gmail.com>
Tested-By: Aaron Watry <awatry@gmail.com>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
3 years agoi965: Only emit VF cache invalidations when the high bits changes
Chris Wilson [Tue, 29 May 2018 16:28:07 +0000 (17:28 +0100)]
i965: Only emit VF cache invalidations when the high bits changes

Commit 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit
addressing bugs with softpin.") tried to only emit the VF invalidate if
the high bits changed, but it accidentally always set need_invalidate to
true; causing it to emit unconditionally emit the pipe control before
every primitive.

Fixes: 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106708
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agovulkan: don't free uninitialised memory
Eric Engestrom [Fri, 18 May 2018 16:12:53 +0000 (17:12 +0100)]
vulkan: don't free uninitialised memory

The modifiers array hasn't been initialised by then, much less with data
that would need freeing.
Move the label after the loop to fix this.

Fixes: c80c08e22603 ("vulkan/wsi/x11: Add support for DRI3 v1.2")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agodri: replace two-way switch case with a table lookup
Eric Engestrom [Fri, 18 May 2018 14:58:58 +0000 (15:58 +0100)]
dri: replace two-way switch case with a table lookup

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
---
v2: rebased on top of 432df741e0b85c021da0 "dri_util: Add
R10G10B10{A,X}2 translation between DRI and mesa_format."

3 years agodri: fix error value returned by driGLFormatToImageFormat()
Eric Engestrom [Fri, 18 May 2018 14:53:58 +0000 (15:53 +0100)]
dri: fix error value returned by driGLFormatToImageFormat()

0 is not a valid value for the __DRI_IMAGE_FORMAT_* enum.
It is, however, the value of MESA_FORMAT_NONE, which two of the callers
(i915 & i965) checked for.

The other callers (that check for errors, ie. st/dri) already check for
__DRI_IMAGE_FORMAT_NONE.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoegl/x11: fix build with DRI3 disabled
Eric Engestrom [Tue, 29 May 2018 15:59:18 +0000 (16:59 +0100)]
egl/x11: fix build with DRI3 disabled

Fixes: 473af0b541b2583f4c72 "egl/x11: deduplicate depth-to-format logic"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Yogesh Marathe <yogesh.marathe@intel.com>
3 years agomeson: require shared glapi when using DRI based libGL
Emil Velikov [Fri, 23 Feb 2018 19:32:03 +0000 (19:32 +0000)]
meson: require shared glapi when using DRI based libGL

Just like we do in the autotools build.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agomeson: remove unreachable with_glx == 'auto' check
Emil Velikov [Fri, 23 Feb 2018 19:32:02 +0000 (19:32 +0000)]
meson: remove unreachable with_glx == 'auto' check

Cannot happen since, props to the autodetection further up.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agotegra: Treat resources with modifiers as scanout
Thierry Reding [Wed, 4 Apr 2018 14:04:25 +0000 (16:04 +0200)]
tegra: Treat resources with modifiers as scanout

Resources created with modifiers are treated as scanout because there is
no way for applications to specify the usage (though that capability may
be useful to have in the future). Currently all the resources created by
applications with modifiers are for scanout, so make sure they have bind
flags set accordingly.

This is necessary in order to properly export buffers for such resources
so that they can be shared with scanout hardware.

Tested-by: Daniel Kolesa <daniel@octaforge.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
3 years agotegra: Fix scanout resources without modifiers
Thierry Reding [Thu, 15 Mar 2018 20:59:02 +0000 (21:59 +0100)]
tegra: Fix scanout resources without modifiers

Resources created for scanout but without modifiers need to be treated
as pitch-linear. This is because applications that don't use modifiers
to create resources must be assumed to not understand modifiers and in
turn won't be able to create a DRM framebuffer and passing along which
modifiers were picked by the implementation.

Tested-by: Daniel Kolesa <daniel@octaforge.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
3 years agotegra: Remove usage of non-stable UAPI
Thierry Reding [Mon, 12 Mar 2018 16:53:51 +0000 (17:53 +0100)]
tegra: Remove usage of non-stable UAPI

This code path is no longer required with framebuffer modifier support.

Tested-by: Daniel Kolesa <daniel@octaforge.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
3 years agodocs: add favicon to the website
Eric Engestrom [Fri, 4 May 2018 11:46:17 +0000 (12:46 +0100)]
docs: add favicon to the website

favicon.png is just gears.png resized to 64x64, and favicon.ico is
generated using this command, adapted from the ImageMagick example [1]:

  $ convert favicon.png -background black \
      \( -clone 0 -resize 16x16 \) \
      \( -clone 0 -resize 32x32 \) \
      \( -clone 0 -resize 48x48 \) \
      \( -clone 0 -resize 64x64 \) \
      -delete 0 -alpha off -colors 256 favicon.ico

We could edit every html page to add `<link rel="icon" href="favicon.ico" />`,
but there's not much point as pretty much every browser will pick it up
automatically if the file is named `favicon.ico` and is in the root folder.

[1] http://www.imagemagick.org/Usage/thumbnails/#favicon

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agodocs: add missing html closing tag
Eric Engestrom [Tue, 29 May 2018 13:47:53 +0000 (14:47 +0100)]
docs: add missing html closing tag

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agodocs: add missing html tag
Eric Engestrom [Tue, 29 May 2018 13:47:10 +0000 (14:47 +0100)]
docs: add missing html tag

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agonir/print: fix printing of 8/16 bit constant variables
Karol Herbst [Thu, 10 May 2018 08:20:47 +0000 (10:20 +0200)]
nir/print: fix printing of 8/16 bit constant variables

v2 (Jose Maria Casanova Crespo <jmcasanova@igalia.com>): add float16 support

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
3 years agonv50/ir: Extend ImmediateValue::applyLog2 to 64-bit integers
Pierre Moreau [Sat, 6 May 2017 15:55:43 +0000 (17:55 +0200)]
nv50/ir: Extend ImmediateValue::applyLog2 to 64-bit integers

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agoutil/u_math: Implement a logbase2 function for unsigned long
Pierre Moreau [Sat, 6 May 2017 15:52:59 +0000 (17:52 +0200)]
util/u_math: Implement a logbase2 function for unsigned long

v2 (Karol Herbst <kherbst@redhat.com>):
* removed unneeded ll
* ll -> ull

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agodocs: trivial typo fix
Eric Engestrom [Tue, 29 May 2018 11:10:03 +0000 (12:10 +0100)]
docs: trivial typo fix

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoradv: emit shader descriptor pointers consecutively
Samuel Pitoiset [Fri, 25 May 2018 12:59:21 +0000 (14:59 +0200)]
radv: emit shader descriptor pointers consecutively

This reduces the number of SET_SH_REG packets which are emitted
for applications that use more than one descriptor set per stage.

We should be able to emit more SET_SH_REG packets consecutively
(like push constants and vertex buffers for the vertex stage),
but this will be improved later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: allow radv_emit_shader_pointer_head() to emit more pointers
Samuel Pitoiset [Fri, 25 May 2018 12:59:20 +0000 (14:59 +0200)]
radv: allow radv_emit_shader_pointer_head() to emit more pointers

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: split radv_emit_shader_pointer()
Samuel Pitoiset [Fri, 25 May 2018 12:59:19 +0000 (14:59 +0200)]
radv: split radv_emit_shader_pointer()

This will allow to emit consecutive shader pointers for
reducing the number of emitted SET_SH_REG packets, which
is recommended.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agogm107/ir: prevent WaW hazards in instruction scheduling
Rhys Perry [Sat, 19 May 2018 21:03:39 +0000 (22:03 +0100)]
gm107/ir: prevent WaW hazards in instruction scheduling

Previously, findFirstUse() only considered reads "uses". This fixes that
by making it check both an instruction's sources and definitions. It
also shortens both findFistUse() and findFirstDef() along the way.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agoradv: Implement VK_KHR_draw_indirect_count.
Bas Nieuwenhuizen [Sat, 26 May 2018 21:09:25 +0000 (23:09 +0200)]
radv: Implement VK_KHR_draw_indirect_count.

Literally the same as the AMD ext.

Passes *indirect_draw_count* CTS tests.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agovulkan: Update header+vk.xml to 1.1.76
Bas Nieuwenhuizen [Sat, 26 May 2018 21:08:29 +0000 (23:08 +0200)]
vulkan: Update header+vk.xml to 1.1.76

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: Implement alternate GFX9 scissor workaround.
Bas Nieuwenhuizen [Sun, 27 May 2018 16:49:57 +0000 (18:49 +0200)]
radv: Implement alternate GFX9 scissor workaround.

This improves dota2 performance for me by 11% when I force the
GPU DPM level to low (otherwise dota2 is CPU limited for 4k on my
threadripper), which should be a large part of the radv-amdvlk gap.
(For me with that was radv 60.3 -> 66.6, while AMDVLK does about 68
fps)

It looks like dota2 rendered the GUI with a bunch of draws with
a SetScissors before almost each draw, causing a lot of pipeline
stalls.

I'm not really happy with the duplication of code, but overriding
radeon_set_context_reg would also be messy since we have the
pre-recorded pipelines and a bunch of si_cmd_buffer code, as well
as some memory->context reg loads for which things would be more
complicated.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoRevert "st/nir: use NIR for asm programs"
Eric Anholt [Thu, 17 May 2018 14:53:40 +0000 (15:53 +0100)]
Revert "st/nir: use NIR for asm programs"

This reverts commit 5c33e8c7729edd5e16020ebb8703be96523e04f2.  It broke
fixed function vertex programs on vc4 and v3d, and apparently caused
trouble for radeonsi's NIR paths as well.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
https://bugs.freedesktop.org/show_bug.cgi?id=106673

3 years agoanv: move canonical_address calculation into a separate function
Scott D Phillips [Thu, 15 Mar 2018 19:53:05 +0000 (12:53 -0700)]
anv: move canonical_address calculation into a separate function

A later patch will make use of this in other places. Also, remove
dependency on undefined behavior of left-shifting a signed value.

v2: - move function into a separate header (Chris)
v3: (by Ken) Add new header to the various build systems.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agor600: Fix SSG when not all components are written
Gert Wollny [Sat, 26 May 2018 16:48:32 +0000 (18:48 +0200)]
r600: Fix SSG when not all components are written

Make sure only those components are written to that are specified in the
write mask.

Fixes:
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_vertex
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_fragment
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agor600: Correct IDIV if DST and SRC use the same temporary
Gert Wollny [Sat, 26 May 2018 16:48:31 +0000 (18:48 +0200)]
r600: Correct IDIV if DST and SRC use the same temporary

In cases like

  IDIV TEMP[0].xy TEMP[0].xx TEMP[1].yy

the result will be written to the same register that is also a source register.
Since the components are evaluated one by one, this may result in overwriting
the source value for a later operation. Work around this by adding another
temporary to store the result if the destination temporary index is equal to
one of the source temporary indices.

Fixes:
  dEQP-GLES2.functional.shaders.operator.binary_operator.div.*
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoi965: Revert recent tiled memcpy changes.
Kenneth Graunke [Sat, 26 May 2018 23:25:34 +0000 (16:25 -0700)]
i965: Revert recent tiled memcpy changes.

This reverts commit 79fe00efb474b3f3f0ba4c88826ff67c53a02aef.
This reverts commit f5e8b13f78a085bc95a1c0895e4a38ff6b87b375.
This reverts commit d21c086d819d78fb3f6abcbb14aa492970f442aa.

They broke the Android build and I'd rather not leave it broken
for the long holiday weekend.

3 years agoi965/miptree: Use cpu tiling/detiling when mapping
Scott D Phillips [Mon, 30 Apr 2018 17:25:49 +0000 (10:25 -0700)]
i965/miptree: Use cpu tiling/detiling when mapping

Rename the (un)map_gtt functions to (un)map_map (map by
returning a map) and add new functions (un)map_tiled_memcpy that
return a shadow buffer populated with the intel_tiled_memcpy
functions.

Tiling/detiling with the cpu will be the only way to handle Yf/Ys
tiling, when support is added for those formats.

v2: Compute extents properly in the x|y-rounded-down case (Chris Wilson)

v3: Add units to parameter names of tile_extents (Nanley Chery)
    Use _mesa_align_malloc for the shadow copy (Nanley)
    Continue using gtt maps on gen4 (Nanley)

v4: Use streaming_load_memcpy when detiling

v5: (edited by Ken) Move map_tiled_memcpy above map_movntdqa, so it
    takes precedence.  Add intel_miptree_access_raw, needed after
    rebasing on commit b499b85b0f2cc0c82b7c9af91502c2814fdc8e67.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoi915: Fix streaming loads for intel_tiled_memcpy
Chris Wilson [Fri, 25 May 2018 23:33:56 +0000 (00:33 +0100)]
i915: Fix streaming loads for intel_tiled_memcpy

We stream from a tiled and aligned source into an unaligned user buffer,
so we need to use _mm_storeu_si128.

Fixes: d21c086d819d78fb3f6abcbb14aa492970f442aa (i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoradeonsi: remove unused variable addr_vec
Marek Olšák [Fri, 25 May 2018 22:37:24 +0000 (18:37 -0400)]
radeonsi: remove unused variable addr_vec

trivial

3 years agointel/blorp: Support blits and clears on surfaces with offsets
Jason Ekstrand [Fri, 25 May 2018 19:27:17 +0000 (12:27 -0700)]
intel/blorp: Support blits and clears on surfaces with offsets

For certain EGLImage cases, we represent a single slice or LOD of an
image with a byte offset to a tile and X/Y intratile offsets to the
given slice.  Most of i965 is fine with this but it breaks blorp.  This
is a terrible way to represent slices of a surface in EGL and we should
stop some day but that's a very scary and thorny path.  This gets blorp
to start working with those surfaces and fixes some dEQP EGL test bugs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoradeonsi: fix passing gl_ClipVertex for GS and tess
Marek Olšák [Wed, 23 May 2018 04:34:38 +0000 (00:34 -0400)]
radeonsi: fix passing gl_ClipVertex for GS and tess

Also add the fprintf call.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoradeonsi: fix color inputs/outputs for GS and tess
Marek Olšák [Wed, 23 May 2018 04:02:10 +0000 (00:02 -0400)]
radeonsi: fix color inputs/outputs for GS and tess

GS is tested, tessellation is untested.

Have outputs_written_before_ps for HW VS and outputs_written for other
stages. The reason is that COLOR and BCOLOR alias for HW VS, which
drives elimination of VS outputs based on PS inputs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoradeonsi: fix incorrect parentheses around VS-PS varying elimination
Marek Olšák [Wed, 23 May 2018 04:16:25 +0000 (00:16 -0400)]
radeonsi: fix incorrect parentheses around VS-PS varying elimination

I don't know if it caused issues.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agost/mesa: simplify lastLevel determination in st_finalize_texture
Marek Olšák [Wed, 23 May 2018 18:41:25 +0000 (14:41 -0400)]
st/mesa: simplify lastLevel determination in st_finalize_texture

This fixes shader images where we always bind stObj->pt and not individual
gl_texture_images.

Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308
which does a similar thing but for a different reason.

This fixes GL CTS assertion failures introduced by Ilia.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoi965/tiled_memcpy: inline movntdqa loads in tiled_to_linear
Scott D Phillips [Mon, 30 Apr 2018 17:25:48 +0000 (10:25 -0700)]
i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

The reference for MOVNTDQA says:

    For WC memory type, the nontemporal hint may be implemented by
    loading a temporary internal buffer with the equivalent of an
    aligned cache line without filling this data to the cache.
    [...] Subsequent MOVNTDQA reads to unread portions of the WC
    cache line will receive data from the temporary internal
    buffer if data is available.

This hidden cache line sized temporary buffer can improve the
read performance from wc maps.

v2: Add mfence at start of tiled_to_linear for streaming loads (Chris)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoswr/rast: Adjusted avx512 primitive assembly for msvc codegen
Alok Hota [Fri, 25 May 2018 15:19:49 +0000 (10:19 -0500)]
swr/rast: Adjusted avx512 primitive assembly for msvc codegen

Optimize AVX-512 PA Assemble (PA_STATE_OPT). Reduced generated code by
about 4x, MSVC compiler was going crazy making temporaries and
split-loading inputs onto the stack unless explicit AVX-512 load ops
were added

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoswr/rast: Moved memory init out of core swr init
Alok Hota [Fri, 25 May 2018 15:19:48 +0000 (10:19 -0500)]
swr/rast: Moved memory init out of core swr init

Added two new files for a wrapper function for initialization

v2: added missing include for single architecture builds

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoswr/rast: Removed superfluous JitManager argument from passes
Alok Hota [Fri, 25 May 2018 15:19:47 +0000 (10:19 -0500)]
swr/rast: Removed superfluous JitManager argument from passes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoswr/rast: Renamed MetaData calls
Alok Hota [Fri, 25 May 2018 15:19:46 +0000 (10:19 -0500)]
swr/rast: Renamed MetaData calls

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoswr/rast: Use metadata to communicate between passes
Alok Hota [Fri, 25 May 2018 15:19:45 +0000 (10:19 -0500)]
swr/rast: Use metadata to communicate between passes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoswr/rast: Check gCoreBuckets/CORE_BUCKETS equal length at compile time
Alok Hota [Fri, 25 May 2018 15:19:44 +0000 (10:19 -0500)]
swr/rast: Check gCoreBuckets/CORE_BUCKETS equal length at compile time

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoswr/rast: Added in-place building to SCATTERPS
Alok Hota [Fri, 25 May 2018 15:19:43 +0000 (10:19 -0500)]
swr/rast: Added in-place building to SCATTERPS

SCATTERPS previously assumed it was being used with an existing basic
block

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
3 years agoradv: run the EarlyCSEMemSSA LLVM pass
Samuel Pitoiset [Thu, 24 May 2018 20:55:54 +0000 (22:55 +0200)]
radv: run the EarlyCSEMemSSA LLVM pass

It's recommended by the instruction combining pass, and
RadeonSI also runs it.

This pass used to segfault with one shader of F12017 in the
past, but it no longer crashes. Maybe the LLVM IR generated
by RADV has changed.

Polaris10:
Totals from affected shaders:
SGPRS: 441352 -> 441648 (0.07 %)
VGPRS: 310888 -> 300784 (-3.25 %)
Spilled SGPRs: 13576 -> 12983 (-4.37 %)
Code Size: 22560328 -> 22420544 (-0.62 %) bytes
Max Waves: 40755 -> 41366 (1.50 %)

Vega10:
Totals from affected shaders:
SGPRS: 442848 -> 442000 (-0.19 %)
VGPRS: 310396 -> 300460 (-3.20 %)
Spilled SGPRs: 13708 -> 12906 (-5.85 %)
Code Size: 22479428 -> 22336216 (-0.64 %) bytes
Max Waves: 45783 -> 46506 (1.58 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: fix dumping compute shader on the graphics queue
Samuel Pitoiset [Thu, 24 May 2018 11:09:14 +0000 (13:09 +0200)]
radv: fix dumping compute shader on the graphics queue

The graphics pipeline can be NULL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: add radv_dump_pipeline_state() helper
Samuel Pitoiset [Thu, 24 May 2018 11:09:13 +0000 (13:09 +0200)]
radv: add radv_dump_pipeline_state() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: rework how shaders are dumped when generating a hang report
Samuel Pitoiset [Thu, 24 May 2018 11:09:12 +0000 (13:09 +0200)]
radv: rework how shaders are dumped when generating a hang report

Use a flag for the active stages instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: remove unused parameter in radv_dump_annotated_shader()
Samuel Pitoiset [Thu, 24 May 2018 11:09:11 +0000 (13:09 +0200)]
radv: remove unused parameter in radv_dump_annotated_shader()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agomesa: do not leak ctx->Shader.ReferencedProgram references
Jose Dapena Paz [Thu, 24 May 2018 17:56:24 +0000 (19:56 +0200)]
mesa: do not leak ctx->Shader.ReferencedProgram references

When glUseProgram is used, references to the included shaders are
added in ctx->Shader.ReferencedProgram. But those references are not
decreased when the shader data is deallocated. Thus, those shaders
are leaked.

Explicitely remove the pending references to these shaders.

Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoradeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly
Marek Olšák [Wed, 16 May 2018 02:04:20 +0000 (22:04 -0400)]
radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoradeonsi: round ps_iter_samples in set_min_samples
Marek Olšák [Wed, 16 May 2018 02:03:40 +0000 (22:03 -0400)]
radeonsi: round ps_iter_samples in set_min_samples

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoradeonsi: remove redundant ps_iter_samples clamp
Marek Olšák [Wed, 16 May 2018 01:51:07 +0000 (21:51 -0400)]
radeonsi: remove redundant ps_iter_samples clamp

si_get_ps_iter_samples already does this.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoradeonsi: remove some old gfx 9.x registers
Marek Olšák [Tue, 15 May 2018 21:19:33 +0000 (17:19 -0400)]
radeonsi: remove some old gfx 9.x registers

Leftover from bring up.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoradeonsi: disable primitive binning for all blitter ops
Marek Olšák [Thu, 3 May 2018 01:03:44 +0000 (21:03 -0400)]
radeonsi: disable primitive binning for all blitter ops

same as amdvlk.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoac/surface/gfx6: don't overallocate mipmapped HTILE
Marek Olšák [Tue, 1 May 2018 18:34:19 +0000 (14:34 -0400)]
ac/surface/gfx6: don't overallocate mipmapped HTILE

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoegl/x11: deduplicate depth-to-format logic
Eric Engestrom [Thu, 17 May 2018 15:16:34 +0000 (16:16 +0100)]
egl/x11: deduplicate depth-to-format logic

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agoi965: enable OES_texture_view for gen8+
Tapani Pälli [Wed, 9 May 2018 06:12:33 +0000 (09:12 +0300)]
i965: enable OES_texture_view for gen8+

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agomesa: changes to expose OES_texture_view extension
Tapani Pälli [Wed, 9 May 2018 06:12:32 +0000 (09:12 +0300)]
mesa: changes to expose OES_texture_view extension

Functionality already covered by ARB_texture_view, patch also
adds missing 'gles guard' for enums (added in f1563e6392).

Tested via arb_texture_view.*_gles3 tests and individual app
utilizing texture view with ETC2.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agodocs: update release calendar for 18.1 series
Juan A. Suarez Romero [Wed, 23 May 2018 13:57:20 +0000 (15:57 +0200)]
docs: update release calendar for 18.1 series

v2: extend 18.1 series (Andres)
v3: fix copy/paste typo (Engestrom)

CC: Andres Gomez <agomez@igalia.com>
CC: Emil Velikov <emil.l.velikov@gmail.com>
CC: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agoradv: call nir_lower_io_to_temporaries for VS, GS, TES and FS
Samuel Pitoiset [Wed, 23 May 2018 12:31:56 +0000 (14:31 +0200)]
radv: call nir_lower_io_to_temporaries for VS, GS, TES and FS

Do not lower FS inputs because this moves all load_var
instructions at beginning of shaders and because
interp_var_at_sample (and friends) seem broken. That might
be eventually enabled later on if we really want to preload
all FS inputs at beginning.

Polaris10:
Totals from affected shaders:
SGPRS: 54072 -> 54264 (0.36 %)
VGPRS: 38580 -> 38124 (-1.18 %)
Spilled SGPRs: 652 -> 652 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 2128116 -> 2127380 (-0.03 %) bytes
Max Waves: 8048 -> 8086 (0.47 %)

Vega10:
Totals from affected shaders:
SGPRS: 52616 -> 52656 (0.08 %)
VGPRS: 37536 -> 37116 (-1.12 %)
Spilled SGPRs: 828 -> 828 (0.00 %)
Code Size: 2043756 -> 2042672 (-0.05 %) bytes
Max Waves: 9176 -> 9254 (0.85 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: call nir_split_var_copies() before nir_lower_var_copies()
Samuel Pitoiset [Wed, 23 May 2018 12:31:55 +0000 (14:31 +0200)]
radv: call nir_split_var_copies() before nir_lower_var_copies()

This doesn't nothing special currently because we don't create
any copy_var instructions, but this is needed for the next patch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoi965: Use intel_bufferobj_buffer() wrapper in image surface state setup.
Francisco Jerez [Fri, 16 Mar 2018 21:28:59 +0000 (14:28 -0700)]
i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.

Instead of directly using intel_obj->buffer.  Among other things
intel_bufferobj_buffer() will update intel_buffer_object::
gpu_active_start/end, which are used by glBufferSubData() to decide
which path to take.  Fixes a failure in the Piglit
ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests,
which could be reproduced with a non-standard glGetTexSubImage
implementation (see bug report).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351
Reported-by: Nanley Chery <nanleychery@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
3 years agoi965: Handle non-zero texture buffer offsets in buffer object range calculation.
Francisco Jerez [Fri, 16 Mar 2018 21:35:10 +0000 (14:35 -0700)]
i965: Handle non-zero texture buffer offsets in buffer object range calculation.

Otherwise the specified surface state will allow the GPU to access
memory up to BufferOffset bytes past the end of the buffer.  Found by
inspection.

v2: Protect against out-of-range BufferOffset (Nanley).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
3 years agoi965: Move buffer texture size calculation into a common helper function.
Francisco Jerez [Fri, 16 Mar 2018 20:06:26 +0000 (13:06 -0700)]
i965: Move buffer texture size calculation into a common helper function.

The buffer texture size calculations (should be easy enough, right?)
are repeated in three different places, each of them subtly broken in
a different way.  E.g. the image load/store path was never fixed to
clamp to MaxTextureBufferSize, and none of them are taking into
account the buffer offset correctly.  It's easier to fix it all in one
place.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
3 years agoRevert "mesa: simplify _mesa_is_image_unit_valid for buffers"
Francisco Jerez [Fri, 16 Mar 2018 20:43:27 +0000 (13:43 -0700)]
Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"

This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145.  It was
preventing the image format validation from being done on buffer
textures, which is required to ensure that the application doesn't
attempt to bind a buffer texture with an internal format incompatible
with the image unit format (e.g. of different texel size), which is
not allowed by the spec (it's not allowed for *any* texture target,
whether or not there is spec wording restricting this behavior
specifically for buffer textures) and will cause the driver to
calculate texel bounds incorrectly and potentially crash instead of
the expected behavior.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
3 years agoac: Use DPP for build_ddxy where possible.
Bas Nieuwenhuizen [Wed, 23 May 2018 09:34:15 +0000 (11:34 +0200)]
ac: Use DPP for build_ddxy where possible.

WQM is pretty reliable now on LLVM 7, so let us just use
DPP + WQM.

This gives approximately a 1.5% performance increase on the
vrcompositor built-in benchmark.

v2: Use ac_build_quad_swizzle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
3 years agoi965: add {X,A}BGR2101010 to 'intel_image_formats'
Miguel Casas [Mon, 7 May 2018 15:45:21 +0000 (11:45 -0400)]
i965: add {X,A}BGR2101010 to 'intel_image_formats'

This patch adds {X,A}BGR2101010 entries to the list of supported
'intel_image_formats'.

Bug: https://crbug.com/776093
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agodri_util: Add R10G10B10{A,X}2 translation between DRI and mesa_format.
Miguel Casas [Mon, 7 May 2018 15:45:20 +0000 (11:45 -0400)]
dri_util: Add R10G10B10{A,X}2 translation between DRI and mesa_format.

Add R10G10B10{A,X}2 translation between mesa_format and DRI format
to driGLFormatToImageFormat() and driImageFormatToGLFormat().

Bug: https://crbug.com/776093
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agobin/get-pick-listh.sh: force git --pretty=medium
Dylan Baker [Mon, 21 May 2018 17:30:42 +0000 (10:30 -0700)]
bin/get-pick-listh.sh: force git --pretty=medium

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Andres Gomez <agomez@igalia.com>
3 years agobin/bugzilla_mesa.sh: explicitly set the --pretty argument
Dylan Baker [Mon, 21 May 2018 17:28:34 +0000 (10:28 -0700)]
bin/bugzilla_mesa.sh: explicitly set the --pretty argument

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Andres Gomez <agomez@igalia.com>
3 years agodocs: drop unnecessary out-of-frame target
Eric Engestrom [Wed, 23 May 2018 11:47:33 +0000 (12:47 +0100)]
docs: drop unnecessary out-of-frame target

I'm guessing an earlier version of the website used to have the page
contents in <frames>, but this isn't the case anymore so just drop the
unnecessary `target="_main"` :)

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agodocs: fix various html tags mistakes
Eric Engestrom [Wed, 23 May 2018 11:46:44 +0000 (12:46 +0100)]
docs: fix various html tags mistakes

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agodocs: fix `<` & `>` used in html code
Eric Engestrom [Wed, 23 May 2018 11:46:00 +0000 (12:46 +0100)]
docs: fix `<` & `>` used in html code

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agodocs: add news notes to 18.1.0
Juan A. Suarez Romero [Tue, 22 May 2018 07:33:19 +0000 (09:33 +0200)]
docs: add news notes to 18.1.0

CC: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
3 years agotgsi/scan: add hw atomic to the list of memory accessing files
Dave Airlie [Thu, 10 May 2018 00:01:58 +0000 (01:01 +0100)]
tgsi/scan: add hw atomic to the list of memory accessing files

This fixes 4 out of 5 cases in:
arb_framebuffer_no_attachments-atomic on cayman.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
3 years agollvmpipe: improve rasterization discard logic
Roland Scheidegger [Tue, 22 May 2018 00:12:38 +0000 (02:12 +0200)]
llvmpipe: improve rasterization discard logic

This unifies the explicit rasterization discard as well as the implicit
rasterization disabled logic (which we need for another state tracker),
which really should do the exact same thing.
We'll now toss out the prims early on in setup with (implicit or
explicit) discard, rather than do setup and binning with them, which
was entirely pointless.
(We should eventually get rid of implicit discard, which should also
enable us to discard stuff already in draw, hence draw would be
able to skip the pointless clip and fallback stages in this case.)
We still need separate logic for only null ps - this is not the same
as rasterization discard. But simplify the logic there and don't count
primitives simply when there's an empty fs, regardless of depth/stencil
tests, which seems perfectly acceptable by d3d10.
While here, also fix statistics for primitives if face culling is
enabled.
No piglit changes.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
3 years agoac/surface/gfx6: Don't force a tile index for fmask.
Bas Nieuwenhuizen [Mon, 21 May 2018 13:43:19 +0000 (15:43 +0200)]
ac/surface/gfx6: Don't force a tile index for fmask.

The bpe of the fmask often differs from the bpe of the main
surface. On SI that means it has to get a different tile
index.

addrlib is capable of figuring this out itself, so just pass
-1 instead to let it know that it is not preset.

Fixes: 9bf3570fed0 "ac/surface/gfx6: compute FMASK together with the color surface"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106511
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106499
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoi965: Remove ring switching entirely
Jason Ekstrand [Sat, 12 May 2018 01:16:48 +0000 (18:16 -0700)]
i965: Remove ring switching entirely

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoi965/miptree: Move the access_raw call to the individual map functions
Jason Ekstrand [Fri, 11 May 2018 19:34:44 +0000 (12:34 -0700)]
i965/miptree: Move the access_raw call to the individual map functions

The only function that doesn't need to call access_raw is map_blit.  If
it takes the blitter path, it will happen as part of intel_miptree_copy.
If map_blit takes the blorp path, brw_blorp_copy_miptrees will handle
doing whatever resolves are needed.  This should save us resolves in
quite a few cases and will probably help performance a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>