mesa.git
2 years agov3d: clamp gl_PointSize to a minimum of 1.0
Iago Toral Quiroga [Wed, 31 Jul 2019 07:50:34 +0000 (09:50 +0200)]
v3d: clamp gl_PointSize to a minimum of 1.0

The OpenGL ES spec requires that the value of gl_PointSize is clamped
to an implementation-dependent range matching what is advertised by
GL_ALIASED_POINT_SIZE_RANGE. For V3D this is [1.0, 512.0], but the
hardware won't clamp to the minimum side of the range and won't render
points with a size strictly smaller than 1.0 either, so we need to
clamp manually. For points larger than the maximum size of the range
the hardware clamps automatically.

Fixes piglit test:
spec/!opengl 2.0/vs-point_size-zero

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agonir: add a pass to clamp gl_PointSize to a range
Iago Toral Quiroga [Wed, 31 Jul 2019 07:47:08 +0000 (09:47 +0200)]
nir: add a pass to clamp gl_PointSize to a range

The OpenGL and OpenGL ES specs require that implementations clamp the
value of gl_PointSize to an implementation-depedent range. This pass
is useful for any GPU hardware that doesn't do this automatically
for either one or both sides of the range, such as V3D.

v2:
 - Turn into a generic NIR pass (Eric).
 - Make the pass work before lower I/O so we can use the deref variable
   to inspect if we are writing to gl_PointSize (Eric).
 - Make the pass take the range to clamp as parameter and allow it
   to clamp to both sides of the range or just one side.
 - Make the pass report progress.

v3:
 - Fix copyright header (Eric)
 - use fmin/fmax instead of bcsel to clamp (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: line length style fixes
Iago Toral Quiroga [Wed, 7 Aug 2019 06:32:58 +0000 (08:32 +0200)]
v3d: line length style fixes

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: honor the write mask on store operations
Iago Toral Quiroga [Wed, 7 Aug 2019 06:20:35 +0000 (08:20 +0200)]
v3d: honor the write mask on store operations

v2:
  - Fix incremental update of the const offset when we need to emit a sequence
    with more than one write because of the writemask.
  - Do not move the tmu write emission to a separate helper.

v3:
  - Get the store writemask before the loop, use ffs to get the first component
    to write and clear writemask bits as we process the components (Eric).
  - Simplified the code that figured out the number of components for the TMU
    config based on the number of tmu writes for stores and atomics.

v4:
  - Code clean-ups (Eric).

Fixes:
KHR-GLES31.core.shader_image_load_store.advanced-cast-cs
KHR-GLES31.core.shader_image_load_store.advanced-cast-fs
KHR-GLES31.core.shader_storage_buffer_object.advanced-switchBuffers-cs
KHR-GLES31.core.shader_storage_buffer_object.advanced-switchPrograms-cs
KHR-GLES31.core.shader_storage_buffer_object.basic-operations-case1-cs

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: refactor ntq_emit_tmu_general() slightly
Iago Toral Quiroga [Tue, 6 Aug 2019 10:18:17 +0000 (12:18 +0200)]
v3d: refactor ntq_emit_tmu_general() slightly

When we implement write masks on store operations we might need to
emit multiple write sequences for a given store intrinsic. To make
that easier, let's split the emission of the tmud instructions to
their own block after we are done with the code that only needs to
run once no matter how many write sequences we need to emit.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: do not automatically flush current job for SSBOs and shader images
Iago Toral Quiroga [Mon, 12 Aug 2019 06:36:37 +0000 (08:36 +0200)]
v3d: do not automatically flush current job for SSBOs and shader images

If the current job has a sequence of draw calls involving SSBOs and/or
shader images, we would flush the job in between each draw call.
With this change, we won't flush the current job and we rely on the
application inserting correct barriers by issuing glMemoryBarrier()
when needed.

v2 (Eric):
 - When mapping a buffer for writing, we always need to flush.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: only process glMemoryBarrier() for SSBOs and images
Iago Toral Quiroga [Thu, 8 Aug 2019 10:46:43 +0000 (12:46 +0200)]
v3d: only process glMemoryBarrier() for SSBOs and images

PIPE_BARRIER_UPDATE is defined as:
PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE

Which means we were flushing for any flags other than these two, but
this was intended to only flush for ssbos and images.

Actually, the driver automatically flushes jobs as we need, including
writes/reads involving SSBOs and images, so we don't really need to
flush anything when the program emits a barrier. However, this may
lead to excessive flushing in some cases, so we will soon change this
to avoid atutomatic flushing of the current job for SSBOs and images,
meaning that we will rely on the application to emit correct memory
barriers for these that we should make sure to process here.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agov3d: fix flushing of SSBOs and shader images
Iago Toral Quiroga [Fri, 9 Aug 2019 11:02:32 +0000 (13:02 +0200)]
v3d: fix flushing of SSBOs and shader images

If the current draw call includes SSBOs, then we must flush any jobs
that are writing to the same SSBOs (so that our SSBOs reads are correct),
as well as jobs reading from the same SSBO (so that our SSBO writes don't
stomp previous SSBO reads).

The exact same logic applies to shader images. In this case we were already
flushing previous writes, but we should also flush previous reads.

Note that We don't need to call v3d_flush_jobs_reading_resource() and
v3d_flush_jobs_writing_resource() separately though, since flushing
jobs that read a resource also flushes those writing to it.

Suggested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agointel/tools: Fix aub_file initialization in intel_dump_gpu
Caio Marcelo de Oliveira Filho [Mon, 12 Aug 2019 19:55:37 +0000 (12:55 -0700)]
intel/tools: Fix aub_file initialization in intel_dump_gpu

The `device` can be set earlier either by a command line or a by
intercepting an ioctl call to get the I915_PARAM_CHIPSET_ID done by
the application early.  In both cases `aub_file` and `devinfo` would
not be initialized.

Fix by splitting the conditions

- `device == 0`: use the FD to get both device and devinfo.
- Or `devinfo.gen == 0`: use `device` to initialize it.

And separatedly, initialize aub_file the first time it is needed.

Fixes: d594d2a0524 ("intel/tools: use device info initializer")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoi965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli [Mon, 22 Jul 2019 22:49:24 +0000 (15:49 -0700)]
i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.

If the pixel pipes have a different number of subslices, emit a slice
hashing table that will ensure proper workload distribution.

v2: Set Mask field to 0xffff for workaround (Ken).

2 years agoanv/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli [Mon, 22 Jul 2019 17:56:53 +0000 (10:56 -0700)]
anv/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.

If the pixel pipes have a different number of subslices, emit a slice
hashing table that will ensure proper workload distribution.

v2: Don't need to set the mask - it's mbo (Ken).

2 years agoiris/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli [Fri, 19 Jul 2019 22:29:00 +0000 (15:29 -0700)]
iris/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.

If the pixel pipes have a different number of subslices, emit a slice
hashing table that will ensure proper workload distribution.

v2: Don't need to set the mask - it's mbo (Ken).
v3: Don't keep a reference to the resource used for emitting the table
(Ken).

2 years agointel: Get information about pixel pipes subslices.
Rafael Antognolli [Mon, 1 Jul 2019 20:34:08 +0000 (13:34 -0700)]
intel: Get information about pixel pipes subslices.

v2: Use 1 instead of 1UL (Ken).

2 years agointel/gen_decoder: Decode SLICE_HASH_TABLE.
Rafael Antognolli [Fri, 19 Jul 2019 22:30:56 +0000 (15:30 -0700)]
intel/gen_decoder: Decode SLICE_HASH_TABLE.

2 years agointel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.
Rafael Antognolli [Fri, 19 Jul 2019 20:37:25 +0000 (13:37 -0700)]
intel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.

Add these fields and the 3DSTATE_SLICE_TABLE_STATE_POINTERS instruction
so we can properly configure the slice and subslice hashing on ICL+

v2: Make 'Mask' field a mbo (Ken).

2 years agoanv: Implement VK_KHR_pipeline_executable_properties
Jason Ekstrand [Wed, 24 Apr 2019 08:02:35 +0000 (03:02 -0500)]
anv: Implement VK_KHR_pipeline_executable_properties

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: Add a ralloc context to anv_pipeline
Jason Ekstrand [Wed, 24 Apr 2019 07:21:01 +0000 (02:21 -0500)]
anv: Add a ralloc context to anv_pipeline

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: Force a full re-compile when CAPTURE_INTERNAL_REPRESENTATION_TEXT is set
Jason Ekstrand [Thu, 25 Apr 2019 00:56:39 +0000 (19:56 -0500)]
anv: Force a full re-compile when CAPTURE_INTERNAL_REPRESENTATION_TEXT is set

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv/pipeline: Split setting up per-stage keys into its own loop
Jason Ekstrand [Thu, 25 Apr 2019 00:54:14 +0000 (19:54 -0500)]
anv/pipeline: Split setting up per-stage keys into its own loop

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: Record shader compile stats in the pipeline cache
Jason Ekstrand [Wed, 24 Apr 2019 07:00:25 +0000 (02:00 -0500)]
anv: Record shader compile stats in the pipeline cache

We're going to want these to be available regardless of caching.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv/pipeline: Stash generated code in the pipeline stage
Jason Ekstrand [Wed, 24 Apr 2019 08:19:25 +0000 (03:19 -0500)]
anv/pipeline: Stash generated code in the pipeline stage

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/fs: Add SLM size to brw_cs_prog_data
Jason Ekstrand [Thu, 25 Jul 2019 17:00:23 +0000 (12:00 -0500)]
intel/fs: Add SLM size to brw_cs_prog_data

We don't need it for state setup but it's a useful statistic we want to
pass on to developers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/compiler: Fill a compiler statistics struct
Jason Ekstrand [Wed, 24 Apr 2019 04:19:56 +0000 (23:19 -0500)]
intel/compiler: Fill a compiler statistics struct

This commit is all annoying plumbing work which just adds support for a
new brw_compile_stats struct.  This struct provides a binary driver
readable form of the same statistics we dump out to stderr when we
INTEL_DEBUG is set with a shader stage.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agofreedreno: disable tiling for cubemaps
Khaled Emara [Sun, 4 Aug 2019 15:51:24 +0000 (17:51 +0200)]
freedreno: disable tiling for cubemaps

Tiling doesn't work quite well with cubemaps.
Revert to linear textures, until it's fixed.

2 years agofreedreno: add tiling parameters for 2D/2DArray/3D
Khaled Emara [Sat, 3 Aug 2019 12:59:18 +0000 (14:59 +0200)]
freedreno: add tiling parameters for 2D/2DArray/3D

2 years agofreedreno: simplified slices setup for a3xx
Khaled Emara [Sat, 3 Aug 2019 12:30:53 +0000 (14:30 +0200)]
freedreno: simplified slices setup for a3xx

a3xx doesn't support ASTC and layout_first always returns false

2 years agofreedreno: enable tiled textures for debug builds
Khaled Emara [Sat, 3 Aug 2019 12:29:43 +0000 (14:29 +0200)]
freedreno: enable tiled textures for debug builds

2 years agointel/fs: add 64 bit integer multiplication lowering
Paulo Zanoni [Thu, 11 Jul 2019 22:08:03 +0000 (15:08 -0700)]
intel/fs: add 64 bit integer multiplication lowering

While NIR's lower_imul64() solves the case of 64 bit integer multiplications
generated early, we don't have a way to lower such instructions when they are
generated by our own backend, such as the scan/reduce intrinsics. We'll need
this soon, so implement it now.

An easy way to test this is to simply disable nir_lower_imul64 to let
those operations reach the backend.

v2:
  - Fix Q/UQ copy/paste errors (Caio).
  - Transform an 'if' into 'else if' (Caio).
  - Add an extra comment to clarify the need for 64b = 32b * 32b
    (Caio).
  - Make private functions private (Caio).
v3:
  - Remove ambiguity with 'b' and 'd' variables (Caio).
  - Allocate potentially less regs for the dwords (Caio).

Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Matt Turner <matt.turner@intel.com>
Cc: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2 years agointel/compiler: invert the logic of lower_integer_multiplication()
Paulo Zanoni [Thu, 11 Jul 2019 00:03:48 +0000 (17:03 -0700)]
intel/compiler: invert the logic of lower_integer_multiplication()

Invert the logic of how progress is handled: remove the continue
statements and mark progress inside the places where it actually
happens.

We're going to add a new lowering that also looks for BRW_OPCODE_MUL,
so inverting the logic here makes the resulting code much easier to
follow.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2 years agointel/compiler: don't instantiate a builder for each instruction
Paulo Zanoni [Wed, 10 Jul 2019 23:48:01 +0000 (16:48 -0700)]
intel/compiler: don't instantiate a builder for each instruction

Don't instantiate a builder for each instruction during
lower_integer_multiplication(). Instantiate one only when needed.

On the other hand, these unneeded builders don't seem to cost much to
init, so I don't expect any significant difference in performance:
this is mostly about code organization.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2 years agointel/compiler: extract subfunctions of lower_integer_multiplication()
Paulo Zanoni [Thu, 11 Jul 2019 23:56:05 +0000 (16:56 -0700)]
intel/compiler: extract subfunctions of lower_integer_multiplication()

The lower_integer_multiplication() function is already a little too
big. I want to add more to it, so let's reorganize the existing code
first. Let's start with just extracting the current code to
subfunctions. Later we'll change them a little more.

v2: Make private functions private (Caio).
v3: Fix typo (Caio).

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2 years agonir: merge and extend nir_opt_move_comparisons and nir_opt_move_load_ubo
Rhys Perry [Wed, 24 Jul 2019 18:23:21 +0000 (19:23 +0100)]
nir: merge and extend nir_opt_move_comparisons and nir_opt_move_load_ubo

v2: add to series
v3: update Makefile.sources
v4: don't remove a comment and break statement
v4: use nir_can_move_instr

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agonir: replace nir_move_load_const() with nir_opt_sink()
Rhys Perry [Wed, 22 May 2019 19:23:03 +0000 (20:23 +0100)]
nir: replace nir_move_load_const() with nir_opt_sink()

This is mostly the same as nir_move_load_const() but can also move
undef instructions, comparisons and some intrinsics (being careful with
loops).

v2: actually delete nir_move_load_const.c
v3: fix nir_opt_sink() usage in freedreno
v3: update Makefile.sources
v4: replace get_move_def with nir_can_move_instr and nir_instr_ssa_def
v4: handle if uses
v4: fix handling of nested loops
v5: re-write adjust_block_for_loops
v5: re-write setting of use_block for if uses

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoanv/gen9: Optimize slice and subslice load balancing behavior.
Francisco Jerez [Thu, 18 Jul 2019 01:41:38 +0000 (18:41 -0700)]
anv/gen9: Optimize slice and subslice load balancing behavior.

See "i965/gen9: Optimize slice and subslice load balancing behavior."
for the rationale.  According to Jason, improves Aztec Ruins
performance by 2.7%.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
v2: Undo CPU performance micro-optimization done in i965 and iris due
    to lack of data justifying it on anv.  Use
    cmd_buffer_apply_pipe_flushes wrapper instead of emitting pipe
    control command directly.  (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agolima/ppir: Add fddx and fddy
Andreas Baierl [Thu, 4 Jul 2019 15:35:09 +0000 (17:35 +0200)]
lima/ppir: Add fddx and fddy

Lower fddx and fddy and set the right bits in codegen.

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2 years agoradv: Enable VK_KHR_pipeline_executable_properties.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 19:08:20 +0000 (21:08 +0200)]
radv: Enable VK_KHR_pipeline_executable_properties.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Implement radv_GetPipelineExecutableStatisticsKHR.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 16:48:51 +0000 (18:48 +0200)]
radv: Implement radv_GetPipelineExecutableStatisticsKHR.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.
Bas Nieuwenhuizen [Fri, 31 May 2019 00:23:44 +0000 (02:23 +0200)]
radv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Implement radv_GetPipelineExecutablePropertiesKHR.
Bas Nieuwenhuizen [Thu, 30 May 2019 23:57:43 +0000 (01:57 +0200)]
radv: Implement radv_GetPipelineExecutablePropertiesKHR.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Keep shader info when needed.
Bas Nieuwenhuizen [Thu, 30 May 2019 23:06:27 +0000 (01:06 +0200)]
radv: Keep shader info when needed.

This allows enabling the shader info keeping on a per shader basis.
Also disables the cache on a per shader basis.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Add VK_KHR_pipeline_executable_properties in disabled state.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 19:45:39 +0000 (21:45 +0200)]
radv: Add VK_KHR_pipeline_executable_properties in disabled state.

So we can add the functions.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Use string for nir dumping.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 18:54:35 +0000 (20:54 +0200)]
radv: Use string for nir dumping.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Allows us to easily dump all nir shaders for combined variants in
vega and simplifies ownership.

2 years agoradv: Get max workgroup size without nir.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 18:25:47 +0000 (20:25 +0200)]
radv: Get max workgroup size without nir.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Add utility function to calculate max waves.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 16:46:21 +0000 (18:46 +0200)]
radv: Add utility function to calculate max waves.

Not AC because a lot of it is data extraction out of radv structs.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoiris/gen9: Optimize slice and subslice load balancing behavior.
Francisco Jerez [Sat, 10 Aug 2019 19:45:46 +0000 (12:45 -0700)]
iris/gen9: Optimize slice and subslice load balancing behavior.

See "i965/gen9: Optimize slice and subslice load balancing behavior."
for the rationale.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agointel/genxml: Add GT_MODE hashing defs for Gen9.
Francisco Jerez [Thu, 18 Jul 2019 01:30:45 +0000 (18:30 -0700)]
intel/genxml: Add GT_MODE hashing defs for Gen9.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoi965/gen9: Optimize slice and subslice load balancing behavior.
Francisco Jerez [Wed, 17 Jul 2019 21:56:18 +0000 (14:56 -0700)]
i965/gen9: Optimize slice and subslice load balancing behavior.

The default pixel hashing mode settings used for slice and subslice
load balancing are far from optimal under certain conditions (see the
comments below for the gory details).  The top-of-the-line GT4 parts
suffer from a particularly severe performance problem currently due to
a subslice load balancing issue.  Fixing this seems to improve
graphics performance across the board for most of the benchmarks in my
test set, up to ~20% in some cases, e.g. from SKL GT4:

unigine/valley:                3.44% ±0.11%
gfxbench/gl_manhattan31:       3.99% ±0.13%
gputest/pixmark_piano:         7.95% ±0.33%
synmark/OglTexFilterAniso:    15.22% ±0.07%
synmark/OglTexMem128:         22.26% ±0.06%

Lower-end platforms are also affected by some subslice load imbalance
to a lesser degree, especially during CCS resolve and fast clear
operations, which are handled specially here due to rasterization
ocurring in reduced CCS coordinates, which changes the semantics of
the pixel hashing mode settings.

No regressions seen during my tests on some SKL, KBL and BXT
configurations.  Additional benchmark reports welcome on any Gen9
platforms (that includes anything with Skylake, Broxton, Kabylake,
Geminilake, Coffeelake, Whiskey Lake, Comet Lake or Amber Lake in your
renderer string).

P.S.: A similar problem is likely to be present on other non-Gen9
      platforms, especially for CCS resolve and fast clear operations.
      Will follow-up with additional patches fixing the hashing mode
      for those once I have enough performance data to justify it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agopan/midgard: Handle 64-bit address in mir_mask_of_read_components
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:40:55 +0000 (17:40 -0700)]
pan/midgard: Handle 64-bit address in mir_mask_of_read_components

This is a bit of a hack, but it'll hold us over until we have 64-bit
support wired through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Allocate separate spill indices for lowered moves
Alyssa Rosenzweig [Fri, 9 Aug 2019 17:40:23 +0000 (10:40 -0700)]
pan/midgard: Allocate separate spill indices for lowered moves

This helps RA be slightly more reasonable.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Extend liveness analysis to trinary ops
Alyssa Rosenzweig [Fri, 9 Aug 2019 17:40:01 +0000 (10:40 -0700)]
pan/midgard: Extend liveness analysis to trinary ops

Fixes RA fails with multiple indirect SSBO writes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Fix load/store pairing
Alyssa Rosenzweig [Fri, 9 Aug 2019 15:56:44 +0000 (08:56 -0700)]
pan/midgard: Fix load/store pairing

This used a delicate hack to try to find indirect inputs and skip them
as candidates for pairing. Let's use a better criterion -- no sources --
and pair based on that.

We could do better, but that would require more complex data flow
analysis than we're interested in doing here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Implement nir_intrinsic_load_num_work_groups
Alyssa Rosenzweig [Tue, 6 Aug 2019 21:07:10 +0000 (14:07 -0700)]
pan/midgard: Implement nir_intrinsic_load_num_work_groups

Just a sysval to route through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Implement some compute builtins
Alyssa Rosenzweig [Tue, 6 Aug 2019 20:47:17 +0000 (13:47 -0700)]
pan/midgard: Implement some compute builtins

We implement gl_WorkGroupID and gl_LocalInvocationID, which map to
ld_compute_id with special sources.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Rename ld_global_id -> ld_compute_id
Alyssa Rosenzweig [Tue, 6 Aug 2019 20:46:56 +0000 (13:46 -0700)]
pan/midgard: Rename ld_global_id -> ld_compute_id

It's used for more general loads within a compute shader.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Handle partial writes in liveness analysis
Alyssa Rosenzweig [Tue, 6 Aug 2019 01:17:27 +0000 (18:17 -0700)]
pan/midgard: Handle partial writes in liveness analysis

This allows liveness analysis within a loop to be more fine grained,
fixing RA failures with partial spilled movs within a loop, as well as
enabling a slight reduction of register pressure more generally:

total registers in shared programs: 350 -> 347 (-0.86%)
registers in affected programs: 12 -> 9 (-25.00%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Dump "no spill"?
Alyssa Rosenzweig [Tue, 6 Aug 2019 01:09:36 +0000 (18:09 -0700)]
pan/midgard: Dump "no spill"?

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Absorb nonexistance sources
Alyssa Rosenzweig [Tue, 6 Aug 2019 01:06:24 +0000 (18:06 -0700)]
pan/midgard: Absorb nonexistance sources

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Pretty-print destinations
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:59:53 +0000 (17:59 -0700)]
pan/midgard: Pretty-print destinations

They're not "sources" but they follow the same conventions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Pretty-print units
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:58:52 +0000 (17:58 -0700)]
pan/midgard: Pretty-print units

Since we are seeing some use of MIR post-scheduling, let's get this
printed right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Print mask in dumped MIR
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:52:56 +0000 (17:52 -0700)]
pan/midgard: Print mask in dumped MIR

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add no_spill flag
Alyssa Rosenzweig [Mon, 5 Aug 2019 22:00:11 +0000 (15:00 -0700)]
pan/midgard: Add no_spill flag

Hint for the RA to avoid infinite spilling loops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Generalize mir_mask_of_read_components
Alyssa Rosenzweig [Mon, 5 Aug 2019 21:47:28 +0000 (14:47 -0700)]
pan/midgard: Generalize mir_mask_of_read_components

This now works for load/store and texture instructions as well as ALU.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Implement SSBO access
Alyssa Rosenzweig [Thu, 1 Aug 2019 17:03:02 +0000 (10:03 -0700)]
pan/midgard: Implement SSBO access

Just laying the groundwork. Reads and writes should be supported (both
direct and indirect, either int or float, vec1/2/3/4), but no bounds
checking is done at the moment.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Pipe uniform mask through when spilling
Alyssa Rosenzweig [Mon, 5 Aug 2019 16:19:39 +0000 (09:19 -0700)]
pan/midgard: Pipe uniform mask through when spilling

This is a corner case that happens a lot with SSBOs. Basically, if we
only read a few components of a uniform, we need to only spill a few
components or otherwise we try to spill what we spilled and RA hangs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Clamp sysval component count
Alyssa Rosenzweig [Sat, 3 Aug 2019 00:10:18 +0000 (17:10 -0700)]
pan/midgard: Clamp sysval component count

We don't want to load a 128-bit sysval when 64-bits will do. Fixes RA
failures with SSBO indirect writes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Pass uploaded midgard_instruction through
Alyssa Rosenzweig [Sat, 3 Aug 2019 00:09:54 +0000 (17:09 -0700)]
pan/midgard: Pass uploaded midgard_instruction through

We want to edit it after emission in some cases.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Allow sysval destination override
Alyssa Rosenzweig [Fri, 2 Aug 2019 18:06:21 +0000 (11:06 -0700)]
pan/midgard: Allow sysval destination override

Sometimes a sysval is used to facilitate an instruction but is not the
instruction itself.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Force flush every compute job
Alyssa Rosenzweig [Fri, 9 Aug 2019 15:32:49 +0000 (08:32 -0700)]
panfrost: Force flush every compute job

This is of course suboptimal for performance, forcing each
glDispatchCompute call to be submitted separately to the kernel and
finish to completion. However, for the initial bring-up of compute jobs,
this simplifies quite a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Add SSBO system value
Alyssa Rosenzweig [Thu, 1 Aug 2019 18:03:15 +0000 (11:03 -0700)]
panfrost: Add SSBO system value

For each SSBO index we get from Gallium/NIR, we need two pieces of
information in the shader:

1. The address of the SSBO in GPU memory. Within the shader, we'll be
accessing it with raw memory load/store, so we need the actual address,
not just an index.

2. The size of the SSBO. This is not strictly necessary, but at some
point, we may like to do bounds checking on SSBO accesses.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agogallium/util: Add u_stream_outputs_for_vertices helper
Alyssa Rosenzweig [Thu, 8 Aug 2019 21:27:41 +0000 (14:27 -0700)]
gallium/util: Add u_stream_outputs_for_vertices helper

This u_prim.h helper determines the number of outputs for stream output,
given a particular primitive type and a vertex count. This is useful for
statically calculating sizes of stream output buffers (i.e. when there
is no geometry/tessellation shader in use).

This helper will be used in Panfrost's transform feedback
implementation, as you can probably guess since why else would I be
submitting it....

See also dEQP's getTransformFeedbackOutputCount routine.

v2: Simplify definition using new helpers, which also extends to non-ES2
primitive types (Eric).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoradeonsi: remove the always_nir option
Marek Olšák [Thu, 1 Aug 2019 19:49:39 +0000 (15:49 -0400)]
radeonsi: remove the always_nir option

tgsi_to_nir is no longer optional if NIR is enabled.

2 years agoradeonsi/nir: implement default tess level system values
Marek Olšák [Thu, 1 Aug 2019 18:47:03 +0000 (14:47 -0400)]
radeonsi/nir: implement default tess level system values

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agocompiler: add SYSTEM_VALUE_TESS_LEVEL_OUTER/INNER_DEFAULT
Marek Olšák [Thu, 1 Aug 2019 18:38:40 +0000 (14:38 -0400)]
compiler: add SYSTEM_VALUE_TESS_LEVEL_OUTER/INNER_DEFAULT

TCS system values for internal passthru TCS, needed by radeonsi NIR support

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agogallium: add TGSI_SEMANTIC_DEFAULT_OUTER/INNER_LEVEL
Marek Olšák [Thu, 1 Aug 2019 18:21:41 +0000 (14:21 -0400)]
gallium: add TGSI_SEMANTIC_DEFAULT_OUTER/INNER_LEVEL

for radeonsi NIR support.

2 years agotgsi_to_nir: handle tess level inner/outer varyings
Marek Olšák [Thu, 1 Aug 2019 18:16:01 +0000 (14:16 -0400)]
tgsi_to_nir: handle tess level inner/outer varyings

for internal radeonsi shaders

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agotgsi_to_nir: add support for the stencil FS output
Marek Olšák [Thu, 1 Aug 2019 16:29:05 +0000 (12:29 -0400)]
tgsi_to_nir: add support for the stencil FS output

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agotgsi_to_nir: add support for TEX_LZ
Marek Olšák [Thu, 1 Aug 2019 16:25:12 +0000 (12:25 -0400)]
tgsi_to_nir: add support for TEX_LZ

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agocompiler: add SYSTEM_VALUE_USER_DATA_AMD
Marek Olšák [Thu, 1 Aug 2019 01:52:48 +0000 (21:52 -0400)]
compiler: add SYSTEM_VALUE_USER_DATA_AMD

for internal radeonsi shaders

2 years agocompiler: add shader_info.cs.user_data_components_amd
Marek Olšák [Thu, 1 Aug 2019 01:33:37 +0000 (21:33 -0400)]
compiler: add shader_info.cs.user_data_components_amd

2 years agotgsi_to_nir: add basic compute shader support
Marek Olšák [Thu, 1 Aug 2019 01:30:22 +0000 (21:30 -0400)]
tgsi_to_nir: add basic compute shader support

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agotgsi_to_nir: add support for LOAD & STORE with SSBOs and images
Marek Olšák [Thu, 1 Aug 2019 01:17:47 +0000 (21:17 -0400)]
tgsi_to_nir: add support for LOAD & STORE with SSBOs and images

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agotgsi_to_nir: make setup_texture_info reusable
Marek Olšák [Thu, 1 Aug 2019 01:17:05 +0000 (21:17 -0400)]
tgsi_to_nir: make setup_texture_info reusable

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agotgsi_to_nir: add support for TXF_LZ
Marek Olšák [Wed, 31 Jul 2019 21:31:52 +0000 (17:31 -0400)]
tgsi_to_nir: add support for TXF_LZ

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agocompiler: add shader_info.vs.blit_sgprs_amd
Marek Olšák [Wed, 31 Jul 2019 20:55:33 +0000 (16:55 -0400)]
compiler: add shader_info.vs.blit_sgprs_amd

for internal radeonsi shaders

2 years agotgsi_to_nir: be careful about not losing any TGSI properties silently (v2)
Marek Olšák [Wed, 31 Jul 2019 21:16:23 +0000 (17:16 -0400)]
tgsi_to_nir: be careful about not losing any TGSI properties silently (v2)

v2: squash with Timur Kristof's commit

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agotgsi/scan: don't set GS_INVOCATIONS for all shader stages
Marek Olšák [Wed, 31 Jul 2019 21:15:18 +0000 (17:15 -0400)]
tgsi/scan: don't set GS_INVOCATIONS for all shader stages

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agocompiler: add ACCESS_STREAM_CACHE_POLICY
Marek Olšák [Thu, 1 Aug 2019 01:16:12 +0000 (21:16 -0400)]
compiler: add ACCESS_STREAM_CACHE_POLICY

radeonsi will use this.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agogallium: add AMD-specific compute TGSI enums
Marek Olšák [Thu, 1 Aug 2019 01:28:40 +0000 (21:28 -0400)]
gallium: add AMD-specific compute TGSI enums

for tgsi_to_nir

2 years agogallium: add TGSI_PROPERTY_VS_BLIT_SGPRS_AMD for tgsi_to_nir
Marek Olšák [Wed, 31 Jul 2019 20:45:21 +0000 (16:45 -0400)]
gallium: add TGSI_PROPERTY_VS_BLIT_SGPRS_AMD for tgsi_to_nir

needed by radeonsi NIR support

2 years agost/mesa: don't allocate mipmapped texture for NEAREST_MIPMAP_LINEAR
Marek Olšák [Fri, 2 Aug 2019 23:11:53 +0000 (19:11 -0400)]
st/mesa: don't allocate mipmapped texture for NEAREST_MIPMAP_LINEAR

Reviewed-by: Brian Paul <brianp@vmware.com>
2 years agoglsl: Optimize the SoftFP64 shader when first creating it.
Kenneth Graunke [Thu, 8 Aug 2019 08:44:52 +0000 (01:44 -0700)]
glsl: Optimize the SoftFP64 shader when first creating it.

By optimizing the shader before inlining, we avoid having to redo this
work for each inlined copy of a function.  It should also reduce the
memory consumption a bit.

This cuts the KHR-GL46.arrays_of_arrays_gl.SubroutineFunctionCalls2
runtime by 25% on my Icelake.  That test compiles many shaders, which
contain large types (dmat4) and division (expensive operations).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoetnaviv: fix compile warnings in release build
Christian Gmeiner [Mon, 12 Aug 2019 09:09:47 +0000 (11:09 +0200)]
etnaviv: fix compile warnings in release build

[27/31] Compiling C object 'src/gallium/drivers/etnaviv/df32d18@@etnaviv@sta/etnaviv_compiler_nir.c.o'.
In file included from ../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c:552:
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h: In function 'ra_assign':
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h:903:9: warning: unused variable 'ok' [-Wunused-variable]
    bool ok = ra_allocate(g);
         ^~
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c: In function 'etna_compile_shader_nir':
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c:663:9: warning: unused variable 'ok' [-Wunused-variable]
    bool ok = emit_shader(c->nir, &options, &v->num_temps, &num_consts);
         ^~

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2 years agoradv: Do not setup attachments without a framebuffer.
Bas Nieuwenhuizen [Sat, 10 Aug 2019 13:04:30 +0000 (15:04 +0200)]
radv: Do not setup attachments without a framebuffer.

Test that found this: dEQP-VK.geometry.layered.1d_array.secondary_cmd_buffer

Fixes: 49e6c2fb78c "radv: Store color/depth surface info in attachment info instead of framebuffer."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoanv: Implement VK_EXT_subgroup_size_control version 2
Jason Ekstrand [Mon, 12 Aug 2019 12:41:49 +0000 (07:41 -0500)]
anv: Implement VK_EXT_subgroup_size_control version 2

The version bump adds a proper features struct.

Fixes: d10de253097 "anv: Implement VK_EXT_subgroup_size_control"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agovulkan: Update the XML and headers to 1.1.119
Jason Ekstrand [Mon, 12 Aug 2019 12:37:54 +0000 (07:37 -0500)]
vulkan: Update the XML and headers to 1.1.119

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoradv: Hash Wave32 settings in shader key.
Bas Nieuwenhuizen [Sat, 3 Aug 2019 23:34:19 +0000 (01:34 +0200)]
radv: Hash Wave32 settings in shader key.

Can result in different shaders.

Fixes: 8a86908e9a7 "radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Properly use Wave64 for non-NGG GS and copy shader.
Bas Nieuwenhuizen [Sat, 3 Aug 2019 23:29:53 +0000 (01:29 +0200)]
radv: Properly use Wave64 for non-NGG GS and copy shader.

Fixes: 8a86908e9a7 "radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Put wave size in shader options/info.
Bas Nieuwenhuizen [Sat, 3 Aug 2019 22:48:05 +0000 (00:48 +0200)]
radv: Put wave size in shader options/info.

Instead of having the three values everywhere. This is also more
future proof if we want the driver to make those decisions eventually.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agorelnotes: Make entries for radv more consistent.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 21:06:37 +0000 (23:06 +0200)]
relnotes: Make entries for radv more consistent.

Always use 'on' as for the rest of the drivers.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agorelnotes: Add new exts on radv for 19.2.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 21:05:43 +0000 (23:05 +0200)]
relnotes: Add new exts on radv for 19.2.

Reviewed-by: Dave Airlie <airlied@redhat.com>