i965/nir: export nir_optimize

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

i965: call brw_shader_gather_info() from the callers of brw_create_nir()

This will allow us to insert a nir linking step in brw_link_shader().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

i965: create a brw_shader_gather_info() helper

This will help us call gather info at a later point and allow us
to do some linking in nir.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

nir: add some helpers for doing linking

The initial helpers add support for removing unused varyings between
stages.

V2:
- Moved the io mask helper function into this file rather than
  nir.h so it's not used elsewhere considering it doesn't handle
  all corner cases.
- Use bitmask rather than hash table to handle tcs outputs (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: mark xfb varyings as always active

This will be used by the nir linking pass so that we don't remove
otherwise unused varyings.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

nir: add always_active_io to nir variable

Will be used in nir link pass to decided if we can remove a varying
or not.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

r600: fork and import gallium/radeon

This marks the end of code sharing between r600 and radeonsi.
It's getting difficult to work on radeonsi without breaking r600.

A lot of functions had to be renamed to prevent linker conflicts.
There are also minor cleanups.

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965: Rename do_flush_locked to submit_batch().

do_flush_locked isn't a great name - especially given that there's no
locking going on in our code relating to execbuf.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Use atomic ops in get_new_program_id().

We have a nice utility function for this, which eliminates the need for
locking stuff.  This isn't really performance critical, but it's less
code to use the atomic.

p_atomic_inc_return does pre-increment rather than post-increment, so we
change screen->program_id to be initialized to 0 instead of 1.  At which
point, we can just delete the initialization because intel_screen is
rzalloc'd.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Convert brw_bufmgr to use C11 mutexes instead of pthreads.

There's no real advantage or disadvantage here, it's just for stylistic
consistency with the rest of the codebase.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Delete dead meta stencil blit program fields from brw_context.

These have been unused for a while now.

swr/rast: Handle instanceID offset / Instance Stride enable

Supported in JitGatherVertices(); FetchJit::JitLoadVertices() may require
similar changes, will need address this if it is determined that this
path is still in use.

Handle Force Sequential Access in FetchJit::Create.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove code supporting legacy llvm (<3.9)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix allocation of DS output data for USE_SIMD16_FRONTEND

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Slightly more efficient blend jit

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Properly sized null GS buffer

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Move SWR_GS_CONTEXT from thread local storage to stack

Move structure, as the size is significantly reduced due to dynamic
allocation of the GS buffers.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fetch compile state changes

Add ForceSequentialAccessEnable and InstanceIDOffsetEnable bools to
FETCH_COMPILE_STATE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: New GS state/context API

One piglit regression, which was a false pass:
  spec@glsl-1.50@execution@geometry@dynamic_input_array_index

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Add support for R10G10B10_FLOAT_A2_UNORM pixel format

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radv: save/restore all viewports/scissors for meta operations

This is needed since we don't update the number of viewports/scissors
when they are set dynamically (according to the spec). In the following
scenario:

* vkCmdSetViewport()
* vkCmdClearColorImage() (or any other meta operations)

The viewports/scissors weren't saved correctly because no pipeline
was bound before, and thus the number of viewports/scissors were 0.

This fixes a regression with:

dEQP-VK.draw.negative_viewport_height.front_ccw_cull_back

Fixes: 60878dd00c ("radv: do not update the number of viewports in vkCmdSetViewport()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

docs: update calendar, add news item and link release notes for 17.1.10

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs: add sha256 checksums for 17.1.10

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 60df95c6bd8c8cc0d440f3940bbbe936d490c67d)

docs: add release notes for 17.1.10

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 834d6c60db266c7d7dfd973729f20379dd3da287)

git_sha1_gen: fix output on python3

String handling has changed on python3.

Before this patch, on python3:
#define MESA_GIT_SHA1 "git-b'b99dcbfeb3'"
After:
#define MESA_GIT_SHA1 "git-b99dcbfeb3"

(No change on python2, it always looked ok)

Cc: Jose Fonseca <jfonseca@vmware.com>
Fixes: b99dcbfeb344390fea99 "build: Convert git_sha1_gen script to Python."
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/va/postproc: implement the DRM prime grabber

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: convert RGB buffer to YUV with color conversion

Acked-by: Christian König <christian.koenig@amd.com>

vl/csc: add a RGB to YUV CSC matrix

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: create RGB to YUV fragment shader

Acked-by: Christian König <christian.koenig@amd.com>

st/va/postproc: use progressive target buffer for scaling

Scaling between interlaced buffers, esp. for scale-up, because
blit will scale up top filed and bottom field separately. it'll
result in the weaving for these buffer with lack of accuracy.
So use shader deint for the case.

Acked-by: Christian König <christian.koenig@amd.com>

st/va: make internal func vlVaHandleSurfaceAllocate() call simpler

Acked-by: Christian König <christian.koenig@amd.com>

st/va/postproc: add a full NV12 deint support from buffer I to P

Before it's impossible to transcode an interlaced video, becasue if
in order for encoder to work, we have to force buffer to progessive,
but the deint with buffer from I to P is missing. Now along With
the new YUV deint full function, it works with weave and bob deint.

Also this will benefit transcoding video with scaling parameters.

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: add Bob top and bottom to YUV deint function

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: remove vl_compositor_yuv_deint() function

No longer used.

Acked-by: Christian König <christian.koenig@amd.com>

st/va: use new vl_compositor_yuv_deint_full() to deint

We also set src rectangle explicitly just in case of the mismatch
of size between interlaced buffer and progressive buffer

Acked-by: Christian König <christian.koenig@amd.com>

st/omx: use new vl_compositor_yuv_deint_full() to deint

v2: add dst rect to make sure no scale

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: add a new function for YUV deint

It will replace previous deint function with abilities of
scaling and field deinterlacing

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: extend YUV deint function to do field deint

It will add Bob deint ability to interlaced video for HW encoder

Acked-by: Christian König <christian.koenig@amd.com>

vl/compositor: separate YUV part from shader video buffer function

So that it can be re-used

Acked-by: Christian König <christian.koenig@amd.com>

st/va/postproc: use video original size for postprocessing

Otherwise the aligned size will make video scaled

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>

radv: Fix VK_KHR_image_format_list.

Spec adding corner cases ...

Fixes: 969537d9358 "radv: Add support for more DCC compression with VK_KHR_image_format_list."
Reviewed-by: Dave Airlie <airlied@redhat.com>

Revert "Revert "radv: fallback to an in-memory cache when no pipline cache is provided""

I tested this 10 times with
./deqp-vk --deqp-case=dEQP-VK.texture.filtering.3d.formats.r4g4b4a4*

and one full run of CTS, seems the issue is gone.

Also reduces CTS runtime by 30% or so.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

scons: use python3-compatible exceptions

These changes were generated using python's `2to3` tool.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

scons: use python3-compatible generator

These changes were generated using python's `2to3` tool.

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

scons: use python3-compatible lists

These changes were generated using python's `2to3` tool.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

scons: use python3-compatible list-key check

These changes were generated using python's `2to3` tool.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

scons: use python3-compatible print()

These changes were generated using python's `2to3` tool.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102852
Reported-by: Alex Granni <liviuprodea@yahoo.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

radv: init the trace BO before compiling meta shaders

Otherwise, the disasm string is NULL for meta shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: make radv_pipeline_init() static

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove unused variable in radv_dump_annotated_shader()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: make use of ATI_VENDOR_ID everywhere

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: fix viewport transformation for z component

In Vulkan, for 'z' (depth) component, the scale and translate values
for the viewport transformation are:

pz = maxDepth - minDepth
oz = minDepth

zf = pz × zd + oz

Being zd, the third component in vertex's normalized device coordinates.

Fixes: dEQP-VK.draw.inverted_depth_ranges.*
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org

radv: add gfx9 scissor workaround

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>

glx: Sort the GLX extension bit enum and table

Not quite asciibetical: ARB, then EXT, then vendor, just like the GL
extension enum just below. No functional change, but it bothered me.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

etnaviv: Add missing includes after 6ace0b8

Add missing includes after 6ace0b8 (etnaviv: don't enable RT
full-overwrite when logicop is enabled), otherwise the etnaviv driver
won't build because of missing macros.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Andres Gomez <agomez@igalia.com>

etnaviv: fix 16bpp clears

util_pack_color may leave undefined values in the upper half of the packed
integer. As our hardware needs the upper 16 bits to mirror the lower 16bits,
this breaks clears of those formats if the undefined values aren't masked off.

I've only observed the issue with R5G6B5_UNORM surfaces, other 16bpp
formats seem to work fine.

Fixes: d6aa2ba2b2 (etnaviv: replace translate_clear_color with util_pack_color)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

swr/rast: remove llvm fence/atomics from generated files

We currently don't use these instructions, and since their API
changed in llvm-5.0 having them in the autogen files broke the mesa
release tarballs which ship with generated autogen files.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102847
CC: mesa-stable@lists.freedesktop.org
Tested-by: Laurent Carlier <lordheavym@gmail.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

vulkan: enum generator: Generate entries for extended enums

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

vulkan: enum generator: Stop using iterparse

While using iterparse is potentially a little more efficient, the Vulkan
registry XML is not large and using regular element tree simplifies the
parsing logic substantially.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

vulkan: enum generator: generate extension number defines

New extensions can introduce additional enums. Most of the new enums
will have disjoint numbers from the initial enums. For example new
formats introduced by VK_IMG_format_pvrtc :

VK_FORMAT_ASTC_10x8_UNORM_BLOCK = 177,
VK_FORMAT_ASTC_10x8_SRGB_BLOCK = 178,
VK_FORMAT_ASTC_10x10_UNORM_BLOCK = 179,
VK_FORMAT_ASTC_10x10_SRGB_BLOCK = 180,
VK_FORMAT_ASTC_12x10_UNORM_BLOCK = 181,
VK_FORMAT_ASTC_12x10_SRGB_BLOCK = 182,
VK_FORMAT_ASTC_12x12_UNORM_BLOCK = 183,
VK_FORMAT_ASTC_12x12_SRGB_BLOCK = 184,
VK_FORMAT_PVRTC1_2BPP_UNORM_BLOCK_IMG = 1000054000,
VK_FORMAT_PVRTC1_4BPP_UNORM_BLOCK_IMG = 1000054001,
VK_FORMAT_PVRTC2_2BPP_UNORM_BLOCK_IMG = 1000054002,
VK_FORMAT_PVRTC2_4BPP_UNORM_BLOCK_IMG = 1000054003,
VK_FORMAT_PVRTC1_2BPP_SRGB_BLOCK_IMG = 1000054004,
VK_FORMAT_PVRTC1_4BPP_SRGB_BLOCK_IMG = 1000054005,
VK_FORMAT_PVRTC2_2BPP_SRGB_BLOCK_IMG = 1000054006,
VK_FORMAT_PVRTC2_4BPP_SRGB_BLOCK_IMG = 1000054007,

It's obvious we can't have a single table for handling those anymore.

Fortunately the enum values actually contain the number of the
extension that introduced the new enums. So we can build an
indirection table off the extension number and then index by
subtracting the first enum of the the format enum value.

This change makes the extension number available in the generated enum
code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

vulkan: enum generator: make registry more flexible

It will be used to store extension numbers as well.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

vulkan: enum generator: sort enums by names

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

vulkan: enum generator: align function declarations/prototypes

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

util/u_atomic: remove unnecessaty __atomic functions

They are now provided by -latomic, which should be linked as needed
since previous commit.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure: check if -latomic is needed for __atomic_*

On some platforms, gcc generates library calls when __atomic_* functions
are used, but does not link the required library (libatomic) automatically
(supposedly to allow the app to use some other atomics implementation?).

Detect this at configure time and add the library when needed. Tested
on armel (library was added) and on x86_64 (was not, as expected).

Some documentation on this is provided in GCC wiki:
https://gcc.gnu.org/wiki/Atomic/GCCMM

Fixes: 8915f0c0 "util: use GCC atomic intrinsics with explicit memory model"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102573
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

etnaviv: don't enable RT full-overwrite when logicop is enabled

Logicop is a form of blending with the framebuffer, so we must allow
framebuffer reads when logicop is enabled.

Fixes: piglit gl-1.0-logicop on GC3000, which has logicop support
Signed-off-by: Lucas Stach <dev@lynxeye.de>

Revert "intel: Remove unused Kabylake pci ids

drm-intel is in favor of keeping the unused pci-id's which
are still listed in the h/w specs. To keep it uniform
across multiple gfx stack components, I'm reverting below
Mesa patches:
b2dae9f8fd310c19e66b161a7ee9845af78f73e0
ebc5ccf3cc88990248695e833d9ff11e10d91240.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Revert "intel: Remove unused device info for KBL GT1.5"

This reverts commit 4c4c28ca70b2267a2563047e35498b1c9252664f.

GT1.5 device info is required for few reserved pci-id's.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>

gallium/util: Remove unused keymap

This is not used anywhere in the codebase. It's a hashtable
implementation that is based around cso_hash, and is therefore
(and as mentioned in a comment in the source) quite similar to
u_hash_table.

CC: Brian Paul<brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Force outputs_written to contain varyings needed by stream-out.

If transform feedback is recording a varying, it needs a slot in the
VUE map, regardless of whether or not the shader writes it.

Together with the previous patch, this fixes:
- KHR-GL45.enhanced_layouts.xfb_capture_struct

The test captures a structure where the vertex shader writes the first
and third members - but the second still needs a slot.

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>

i965: Compute VS/GS output VUE map from the NIR info.

unify_interfaces() only updates the NIR program info, not the copy
in the gl_program itself.  So, by using the old copy, we were missing
out on these updates.

The TCS/TES ones already did this correctly.

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>

i965: Handle unwritten PSIZ/VIEWPORT/LAYER outputs in vec4 shaders.

This can occur if the shader is capturing some of the values from the
VUE header for transform feedback, but the shader hasn't written all of
them.

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>

i965: Fix brw_finish_batch to grow the batchbuffer.

brw_finish_batch emits commands needed at the end of every batch buffer,
including any workarounds.  In the past, we freed up some "reserved"
batch space before calling it, so we would never have to flush during
it.  This was error prone and easy to screw up, so I deleted it a while
back in favor of growing the batch.

There were two problems:

1. We're in the middle of flushing, so brw->no_batch_wrap is guaranteed
   not to be set.  Using BEGIN_BATCH() to emit commands would cause a
   recursive flush rather than growing the buffer as intended.

2. We already recorded the throttling batch before growing, which
   replaces brw->batch.bo with a different (larger) buffer.  So growing
   would break throttling.

These are easily remedied by shuffling some code around and whacking
brw->no_batch_wrap in brw_finish_batch().  This also now includes the
final workarounds in the batch usage statistics.  Found by inspection.

Fixes: 2c46a67b4138631217141f (i965: Delete BATCH_RESERVED handling.)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Move MI_BATCHBUFFER_END handling into brw_finish_batch().

This is, by definition, finishing the batch.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

radv: Implement VK_AMD_rasterization_order

Tested with AMD's Anvil OutOfOrderRasterization demo on a RX 560.

Signed-off-by: Nicholas Miell <nmiell@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

glsl: silence signed/unsigned comparison warning

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

nv20: Enable ARB_texture_border_clamp

Fixes quite a few 'texwrap [12]d border color only' tests on NV20
(10de:0201).  All told, 40 more tests pass.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian RomanicK <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Ian RomanicK <ian.d.romanick@intel.com>

nv20: Fix GL_CLAMP

v2: Force T and R wrap modes to GL_CLAMP_TO_EDGE for 1D textures.
This fixes a regression in tex1d-2dborder.  The test uses a 1D texture
but it provides S and T texture coordinates.  Since the T wrap mode
would (correctly) be set to GL_CLAMP, the texture would gradually
blend (incorrectly) with the border color.

I also tried setting NV20_3D_TEX_FORMAT_DIMS_1D instead of
NV20_3D_TEX_FORMAT_DIMS_2D for 1D textures, but that did not help.

It is possible that the same problem exists for 2D textures with the
R-wrap mode, but I don't think there are any piglit tests for that.

No test changes on NV20 (10de:0201).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallium: Add PIPE_SHADER_CAP_INT64_ATOMICS

Denotes availability of 64bit int atomic instructions

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl/linker: properly fix output variable overlap check

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102904
Fixes: 15cae12804e ("glsl/linker: fix output variable overlap check")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

ac/surface: handle error when choosing preferred swizzle mode

CID: 1418140
Fixes: c4ac522511d2 ("ac/surface: handle S8 on gfx9")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

amd/addrlib: fix missing va_end() after va_copy()

There's no reason to use va_copy here.

CID: 1418113
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Fixes: e7fc664b91a5d886c270 ("winsys/amdgpu: add addrlib - texture
                              addressing and alignment calculator")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: copy the number of viewports/scissors at pipeline bind time

The number of viewports/scissors can only be specified at pipeline
creation time, so make sure to copy them when binding a new one
because the dynamic state is cleared in BeginCommandBuffer().

Fixes: dcf46e995d ("radv: do not update the number of scissors in vkCmdSetScissor()")
Fixes: 60878dd00c ("radv: do not update the number of viewports in vkCmdSetViewport()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

intel/blorp/hiz: Always set sample number

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/gen8: Remove unused gen8_emit_3dstate_multisample()

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

mesa: free current ComputeProgram state in _mesa_free_context_data

This is already done for other programs stages, fixes a leak when using
compute programs.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102844
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/st: fix infinite loops

Fixes: 9ac8fece63a9 (glsl: Unify ir_constant::const_elements and ::components)
Reviewed-by: Dylan Baker <dylanx.c.baker@intel.com

glsl: merge loop_controls.cpp with loop_unroll.cpp

Having this separate just makes the code harder to follow, and
requires an extra walk of the IR.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

glsl: move loop analysis helpers to loop_analysis.cpp

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

anv: Advertise VK_KHR_maintenance2

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/image: Use RENDER_SURFACE_STATE::X/Y Offset on SKL+

The Broadwell method of handling uncompressed views of compressed
textures was to make the texture linear and have a tiled shadow copy.
This isn't needed on Sky Lake because the HALIGN and VALIGN parameters
are specified in surface elements and required to be a multiple of 4.
This means that we can just use the X/Y Offset fields and we can avoid
the shadow copy song and dance.  This also makes ASTC work because ASTC
can't be linear and so the shadow copy method doesn't work there.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/blorp: Handle clearing compressed surfaces

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/blorp: Internally expose surf_convert_to_uncompressed

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/image: Support creating uncompressed views of compressed images

In order to get support everywhere, this gets a bit complicated.  On Sky
Lake and later, everything is fine because HALIGN/VALIGN are specified
in surface elements and are required to be at least 4 so any offsetting
we may need to do falls neatly within the heavy restrictions placed on
the X/Y Offset parameter of RENDER_SURFACE_STATE.  On Broadwell and
earlier, HALIGN/VALIGN are specified in pixels and are hard-coded to
align to exactly the block size of the compressed texture.  This means
that, when reinterpreted as a non-compressed texture, the tile offsets
may be anything and we can't rely on X/Y Offset.

In order to work around this issue, we fall back to linear where we can
trivially offset to whatever element we so choose.  However, since
linear texturing performance is terrible, we create a tiled shadow copy
of the image to use for texturing.  Whenever the user does a layout
transition from anything to SHADER_READ_ONLY_OPTIMAL, we use blorp to
copy the contents of the texture from the linear copy to the tiled
shadow copy.  This assumes that the client will use the image far more
for texturing than as a storage image or render target.

Even though we don't need the shadow copy on Sky Lake, we implement it
this way first to make testing easier.  Due to the hardware restriction
that ASTC must not be linear, ASTC does not work yet.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Add a new anv_surface_state struct

This struct represents a full surface state including the addresses of
the referenced main and auxiliary surfaces (if any).  This makes
relocation setup substantially simpler and allows us to move 100% of the
surface state setup logic into anv_image where it belongs.  Before, we
were manually fishing data out of surface states when emitting
relocations so we knew how to offset aux address.  It's best to keep all
of the surface state emit logic together.  This also gets us closer, at
least cosmetically, to a world of no relocations where addresses are
placed in surface states up-front.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/image: Break surface state fill logic into a helper

This gives us a single centralized place where we take an image view and
use it to fill out a surface state.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/image: Add support for the VkImageViewUsageCreateInfoKHR struct

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Advertise point clipping properties

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Add support for tessellation domain origin control

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

spirv: Flip the tessellation winding order

It's not SPIR-V that's backwards from GLSL, it's Vulkan that's backwards
from GL.  Let's make NIR consistent with the source language and do the
flipping inside the Vulkan driver instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>