mesa.git
2 years agogbm: Clarify acceptable formats for gbm_bo
Daniel Stone [Thu, 1 Nov 2018 11:30:36 +0000 (11:30 +0000)]
gbm: Clarify acceptable formats for gbm_bo

gbm_bo_create() was presumably meant to originally accept gbm_bo_format
enums, but it's accepted GBM_FORMAT_* tokens since the dawn of time.
This is good, since gbm_bo_format is rarely used and covers a lot less
ground than GBM_FORMAT_*.

Change the documentation to refer to both; this involves removing a 'see
also' for gbm_bo_format, since we can't also use \sa to refer to a
family of anonymous #defines.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reported-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoRevert "radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT"
Connor Abbott [Wed, 17 Oct 2018 14:57:01 +0000 (16:57 +0200)]
Revert "radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT"

This reverts commit 647c2b90e96a9ab8571baf958a7c67c1e816911a. There was
one recently-introduced bug in ac for dvec3 loads, but the other test
failures were actually bugs in the tests. See
https://github.com/KhronosGroup/VK-GL-CTS/commit/9429e621c48848d224e35f30a1ae45a4a079922c

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agovc4: Don't return a vc4 BO handle on a renderonly screen.
Eric Anholt [Thu, 25 Oct 2018 16:17:17 +0000 (09:17 -0700)]
vc4: Don't return a vc4 BO handle on a renderonly screen.

The handles exported need to be on the KMS device's fd, anything else is
failure.  Also, this code is assuming that the scanout resource has been
created already, so assert it.

2 years agovc4: Make sure we make ro scanout resources for create_with_modifiers.
Eric Anholt [Thu, 25 Oct 2018 16:12:50 +0000 (09:12 -0700)]
vc4: Make sure we make ro scanout resources for create_with_modifiers.

The DRI3 create_with_modifiers paths don't set tmpl.bind to SCANOUT or
SHARED, with the theory that given that you've got modifiers, that's all
you need.  However, we were looking at the tmpl.bind for setting up the
KMS handle in the renderonly case, so we'd end up trying to use vc4's
handle on the hx8357d fd.

Fixes: 84ed8b67c56b ("vc4: Set shareable BOs as T tiled if possible")
2 years agoi965: Fix calculation of layers array length for isl_view
Danylo Piliaiev [Thu, 15 Nov 2018 10:03:31 +0000 (12:03 +0200)]
i965: Fix calculation of layers array length for isl_view

Handle all cases in calculation of layers count for isl_view
taking into account texture view and image unit.
st_convert_image was taken as a reference.

When u->Layered is true the whole level is taken with respect to
image view. In other case only one layer is taken.

v3: (Józef Kucia and Ilia Mirkin)
    - Rewrote patch by taking st_convert_image as a reference
    - Removed now unused get_image_num_layers function
    - Changed commit message

v4: (Jason Ekstrand)
    - Added assert

Fixes: 5a8c8903
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agointel/compiler: Lower SSBO and shared loads/stores in NIR
Jason Ekstrand [Tue, 13 Nov 2018 00:48:10 +0000 (18:48 -0600)]
intel/compiler: Lower SSBO and shared loads/stores in NIR

We have a bunch of code to do this in the back-end compiler but it's
fairly specific to typed surface messages and the way we emit them.
This breaks it out into NIR were it's easier to do things a bit more
generally.  It also means we can easily share the code between the vec4
and FS back-ends if we wish.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agonir: Add alignment parameters to SSBO, UBO, and shared access
Jason Ekstrand [Tue, 13 Nov 2018 15:45:03 +0000 (09:45 -0600)]
nir: Add alignment parameters to SSBO, UBO, and shared access

This also changes spirv_to_nir and glsl_to_nir to set them.  The one
place that doesn't set them is shared memory access lowering in
nir_lower_io.  That will have to be updated before any consumers of it
can effectively use these new alignments.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
2 years agonir/lower_io: Add shared to get_io_offset_src
Jason Ekstrand [Wed, 14 Nov 2018 21:36:38 +0000 (15:36 -0600)]
nir/lower_io: Add shared to get_io_offset_src

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agonir/glsl: Force 32-bit for UBO and SSBO Booleans
Jason Ekstrand [Tue, 13 Nov 2018 16:19:25 +0000 (10:19 -0600)]
nir/glsl: Force 32-bit for UBO and SSBO Booleans

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agonir/spirv: Force 32-bit for UBO and SSBO Booleans
Jason Ekstrand [Tue, 13 Nov 2018 16:07:31 +0000 (10:07 -0600)]
nir/spirv: Force 32-bit for UBO and SSBO Booleans

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agonir/builder: Add a nir_pack/unpack/bitcast helpers
Jason Ekstrand [Tue, 13 Nov 2018 00:38:24 +0000 (18:38 -0600)]
nir/builder: Add a nir_pack/unpack/bitcast helpers

The new helpers can generate any pack/unpack operation including those
for which we do not have specific opcodes and they express a bitcast in
terms of these pack/unpack operations.  In particular, the new helpers
properly handle 8-bit types.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agonir/builder: Add iadd_imm and imul_imm helpers
Jason Ekstrand [Mon, 12 Nov 2018 21:58:18 +0000 (15:58 -0600)]
nir/builder: Add iadd_imm and imul_imm helpers

The pattern of adding or multiplying an integer by an immediate is
fairly common especially in deref chain handling.  This adds a helper
for it and uses it a few places.  The advantage to the helper is that
it automatically handles bit sizes for you.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2 years agonir/builder: Assert that intN_t immediates fit
Jason Ekstrand [Mon, 12 Nov 2018 22:02:23 +0000 (16:02 -0600)]
nir/builder: Assert that intN_t immediates fit

This assert won't catch all mistakes with this helper but it will at
least ensure that the top bits are all zero or all one which should help
catch bugs.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agonir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16
Jason Ekstrand [Tue, 13 Nov 2018 19:24:34 +0000 (13:24 -0600)]
nir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16

It messes up when trying to lower.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2 years agoglsl: Refactor type checking for redeclarations
Ian Romanick [Tue, 9 Oct 2018 20:37:44 +0000 (13:37 -0700)]
glsl: Refactor type checking for redeclarations

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2 years agoglsl: Omit redundant qualifier checks on redeclarations
Ian Romanick [Tue, 9 Oct 2018 19:01:22 +0000 (12:01 -0700)]
glsl: Omit redundant qualifier checks on redeclarations

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2 years agoglsl: prevent qualifiers modification of predeclared variables
Ian Romanick [Tue, 9 Oct 2018 18:34:15 +0000 (11:34 -0700)]
glsl: prevent qualifiers modification of predeclared variables

Section 3.7 (Identifiers) of the GLSL spec says:

    However, as noted in the specification, there are some cases where
    previously declared variables can be redeclared to change or add
    some property, and predeclared "gl_" names are allowed to be
    redeclared in a shader only for these specific purposes.  More
    generally, it is an error to redeclare a variable, including those
    starting "gl_".

This patch should fix piglit tests:
clip-distance-redeclare-without-inout.frag
clip-distance-redeclare-without-inout.vert

However, this causes a regression in
clip-distance-out-values.shader_test.  A fix for that test has been sent
to the piglit list for review:

    https://patchwork.freedesktop.org/patch/255201/

As far as I understood following mailing thread:
https://lists.freedesktop.org/archives/piglit/2013-October/007935.html
looks like we have accepted to remove an ability to change qualifiers
but have not done it yet. Unless I missed something)

v2 (idr): Move 'earlier->data.mode != var->data.mode' test much earlier
in the function.  Add special handling for gl_LastFragData.

Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2 years agov3d: Don't try to set PF flags on a LDTMU operation
Eric Anholt [Tue, 6 Nov 2018 17:39:40 +0000 (09:39 -0800)]
v3d: Don't try to set PF flags on a LDTMU operation

We need an ALU op in order to set PF.  Fixes a recent assertion failure in
dEQP-GLES3.functional.ubo.single_basic_type.shared.bool_vertex

2 years agov3d: Fix double-swapping of R/B on V3D 4.1
Eric Anholt [Tue, 6 Nov 2018 00:40:22 +0000 (16:40 -0800)]
v3d: Fix double-swapping of R/B on V3D 4.1

Fixes: 4018eb04e8a5 ("v3d: Use the TLB R/B swapping instead of recompiles when available.")
2 years agoegl: fix bad rebase
Eric Engestrom [Thu, 15 Nov 2018 17:48:58 +0000 (17:48 +0000)]
egl: fix bad rebase

I screwed up a rebase over a refactor and didn't notice locally because
the uncommitted refactor hid the issue.

Fixes: c9733649670243a1a6eb "egl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agointel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as dp_sampler
Sagar Ghuge [Thu, 15 Nov 2018 06:39:43 +0000 (22:39 -0800)]
intel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as dp_sampler

Both BRW_SFID_SAMPLER and GEN6_SFID_DATAPORT_SAMPLER_CACHE are getting
disassembled as "sampler", which is misleading for assembler tool.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
2 years agoegl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache
Eric Engestrom [Wed, 14 Nov 2018 12:51:38 +0000 (12:51 +0000)]
egl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache

Fixes dEQP-EGL.functional.get_proc_address.extension.egl_android_blob_cache
on builds with glvnd enabled.

Fixes: 6f5b57093b3462a54e9c7 "egl: add support for EGL_ANDROID_blob_cache"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2 years agogbm: add new entrypoint to symbols check
Eric Engestrom [Wed, 14 Nov 2018 13:05:34 +0000 (13:05 +0000)]
gbm: add new entrypoint to symbols check

Fixes: 6328536ff28ca26f2ad4e "gbm: Introduce a helper function for
                              printing GBM format names."
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agobin/get-pick-list.sh: handle reverts prior to the branchpoint
Emil Velikov [Wed, 14 Nov 2018 18:49:54 +0000 (18:49 +0000)]
bin/get-pick-list.sh: handle reverts prior to the branchpoint

Currently we detect when a breaking commit:
 - has landed in stable, and
 - is referenced by a untagged fix in master

Yet we did not consider the case of breaking commit:
 - prior to the branchpoint, and
 - is referenced by a untagged fix in master

Addressing the latter is extremely slow, due to the size of the lookup.

That said, we can trivially use the existing is_sha_nomination() helper
to catch reverts.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: use test instead of [ ]
Emil Velikov [Thu, 8 Nov 2018 15:05:21 +0000 (15:05 +0000)]
bin/get-pick-list.sh: use test instead of [ ]

Latter is rather picky wrt surrounding white space. The explicit `test`
doesn't have that problem, plus the statements read a bit easier.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: handle unofficial "broken by" tag
Emil Velikov [Thu, 8 Nov 2018 15:05:20 +0000 (15:05 +0000)]
bin/get-pick-list.sh: handle unofficial "broken by" tag

We have a number of cases were devs will use a tag "broken by".
While it's not something officially documented or recommended, checking
for it is trivial enough.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: handle fixes tag with missing colon
Emil Velikov [Thu, 8 Nov 2018 15:05:19 +0000 (15:05 +0000)]
bin/get-pick-list.sh: handle fixes tag with missing colon

Every so often, we forget to add the colon after "fixes". Trivially
tweak the script to catch it.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: flesh out is_sha_nomination
Emil Velikov [Thu, 8 Nov 2018 15:05:18 +0000 (15:05 +0000)]
bin/get-pick-list.sh: flesh out is_sha_nomination

Refactor is_fixes_nomination into a is_sha_nomination helper. This way
we can reuse it for more than the usual "Fixes:" tag.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: tweak the commit sha matching pattern
Emil Velikov [Thu, 8 Nov 2018 15:05:17 +0000 (15:05 +0000)]
bin/get-pick-list.sh: tweak the commit sha matching pattern

Currently we match on:
 - any arbitrary length of,
 - any a-z A-Z and 0-9 characters

At the same time, a commit sha consists of lowercase hexadecimal
numbers. Any sha shorter than 8 characters is ambiguous - in some cases
even 11+ are required.

So change the pattern to a-f0-9 and adjust the length to 8-40.

As we're here we could use a single grep, instead of the grep/sed combo.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: handle the fixes tag
Emil Velikov [Thu, 8 Nov 2018 15:05:16 +0000 (15:05 +0000)]
bin/get-pick-list.sh: handle the fixes tag

Having a separate script to handle the fixes tag, brings a number of
issues, so let's fold it in get-pick-list.sh.

v2:
 - pass the sha as argument to the function
 - Keep original sed pattern

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: handle "typod" usecase.
Emil Velikov [Thu, 8 Nov 2018 15:05:15 +0000 (15:05 +0000)]
bin/get-pick-list.sh: handle "typod" usecase.

As the comment in get-typod-pick-list.sh says, there's little point in
having a duplicate file.

Add the new pattern + tag to get-pick-list.sh and nuke this file.

v2:
 - pass the sha as argument to the function
 - grep -q instead of using a variable (Eric)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: prefix output with "[stable] "
Emil Velikov [Thu, 8 Nov 2018 15:05:14 +0000 (15:05 +0000)]
bin/get-pick-list.sh: prefix output with "[stable] "

With later commits we'll fold all the different scripts into one.
Add the explicit prefix, so that we know the origin of the nomination

v2:
 - pass the sha as argument to the function
 - swap $tag = none for an else statment (Juan)
 - grep -q instead of using a variable (Eric)
 - print the tag and commit oneline separately (Eric)

v3:
 - drop unused "tag=none" assignment (Juan)
 - typo nomination

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v2)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agobin/get-pick-list.sh: simplify git oneline printing
Emil Velikov [Thu, 8 Nov 2018 15:05:13 +0000 (15:05 +0000)]
bin/get-pick-list.sh: simplify git oneline printing

Currently we force disable the pager via "|cat" where --no-pager
exists. Additionally we could use git show instead of git log -n1.

Use those for a slightly more understandable code.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2 years agodocs: document the staging branch and add reference to it
Emil Velikov [Wed, 7 Nov 2018 16:02:59 +0000 (16:02 +0000)]
docs: document the staging branch and add reference to it

A while back we agreed that having a live/staging branch is beneficial.
Sadly we forgot to document that, so here is my first attempt.

Document the caveat that the branch history is not stable.

CC: Andres Gomez <agomez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2 years agodocs/submittingpatches.html: correctly handle the <p> tag
Emil Velikov [Wed, 7 Nov 2018 16:02:58 +0000 (16:02 +0000)]
docs/submittingpatches.html: correctly handle the <p> tag

As pointed out by the w3c validator.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2 years agodocs/releasing.html: polish cherry-picking/testing text
Emil Velikov [Wed, 7 Nov 2018 16:02:57 +0000 (16:02 +0000)]
docs/releasing.html: polish cherry-picking/testing text

Reword slightly and highlight the important parts of the text.

CC: Andres Gomez <agomez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2 years agoetnaviv: Make sure rs alignment checks match
Guido Günther [Mon, 17 Sep 2018 14:06:57 +0000 (16:06 +0200)]
etnaviv: Make sure rs alignment checks match

etna_resource_alloc and etna_resource_from_handle currently use different checks.
This leads to

   etna_resource_from_handle:492: target=2, format=PIPE_FORMAT_B8G8R8X8_UNORM, 1080x1920x1, array_size=1, last_level=0, nr_samples=0, usage=0, bind=8000a, flags=0
   etna_resource_from_handle:541: BO stride 4320 is too small for RS engine width padding (4352, format PIPE_FORMAT_B8G8R8X8_UNORM)

since etna_resource_from_handle wants to be aligned to a 16 byte
boundary while the etna_resource_alloc does not.

Adjust the two checks by using a common function.

Broken by baff59ebf07a114f95ad66d1f54e4b1f409eebee

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2 years agodocs: update calendar, add news item and link release notes for 18.2.5
Juan A. Suarez Romero [Thu, 15 Nov 2018 13:08:58 +0000 (13:08 +0000)]
docs: update calendar, add news item and link release notes for 18.2.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2 years agodocs: add sha256 checksums for 18.2.5
Juan A. Suarez Romero [Thu, 15 Nov 2018 13:04:37 +0000 (13:04 +0000)]
docs: add sha256 checksums for 18.2.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 79be754f9a74a43b5748dc0934241e7701cb9581)

2 years agodocs: add release notes for 18.2.5
Juan A. Suarez Romero [Thu, 15 Nov 2018 11:58:11 +0000 (11:58 +0000)]
docs: add release notes for 18.2.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit f34bddc325c414cb8ee21666bd307512577efdef)

2 years agoradeonsi: fix video APIs on Raven2
Marek Olšák [Tue, 13 Nov 2018 23:37:39 +0000 (18:37 -0500)]
radeonsi: fix video APIs on Raven2

This was missed when I added the new enum.

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2 years agoi965: avoid 'unused variable' warnings
Andrii Simiklit [Tue, 13 Nov 2018 12:19:30 +0000 (14:19 +0200)]
i965: avoid 'unused variable' warnings

1. brw_pipe_control.c:311:34: warning:
    unused variable ‘devinfo’
2. brw_program_binary.c:209:19: warning:
    unused variable ‘gen_size’
3. brw_program_binary.c:216:19: warning:
    unused variable ‘nir_size’

v2: Changes for unreproducible issues were removed

Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agocompiler: avoid 'unused variable' warnings
Andrii Simiklit [Tue, 13 Nov 2018 12:19:29 +0000 (14:19 +0200)]
compiler: avoid 'unused variable' warnings

1. nir/nir_lower_vars_to_ssa.c:691:21: warning:
       unused variable ‘var’
       nir_variable *var = path->path[0]->var;

v2: Changes for some part of 'may be used uninitialized'
    warnings were removed, seems like it is a compiler issue.
        ( Eric Engestrom <eric.engestrom@intel.com> )
    Possible like this one:
    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46684
    This issue is flagged as duplicate but an
    original one is not closed yet.

Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agointel/tools: avoid 'unused variable' warnings
Andrii Simiklit [Tue, 13 Nov 2018 12:19:28 +0000 (14:19 +0200)]
intel/tools: avoid 'unused variable' warnings

1. tools/aub_read.c:271:31: warning: unused variable ‘end’
    const uint32_t *p = data, *end = data + data_len, *next;

2. tools/aub_mem.c:292:13: warning: unused variable ‘res’
       void *res = mmap((uint8_t *)bo.map + map_offset, 4096, PROT_READ,
   tools/aub_mem.c:357:13: warning: unused variable ‘res’
       void *res = mmap((uint8_t *)bo.map + (page - bo.addr), 4096, PROT_READ,

v2: The i965_disasm.c changes was moved into a separate patch
    The 'end' variable declared separately with MAYBE_UNUSED
    to avoid effect of it to other variables.
       ( Eric Engestrom <eric.engestrom@intel.com> )

Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agost/xa: Bump minor
Thomas Hellstrom [Fri, 9 Nov 2018 14:27:48 +0000 (15:27 +0100)]
st/xa: Bump minor

Bump minor to signal support for new formats and higher precision
solid pictures.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2 years agost/xa: Support Component Alpha with trivial blending
Thomas Hellstrom [Tue, 13 Nov 2018 13:10:56 +0000 (14:10 +0100)]
st/xa: Support Component Alpha with trivial blending

Support Component Alpha for those composite operations that do not require
per-channel alpha blending.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2 years agost/xa: Minor renderer cleanups
Thomas Hellstrom [Tue, 13 Nov 2018 17:24:45 +0000 (18:24 +0100)]
st/xa: Minor renderer cleanups

constify function arguments to clean up the code a bit.

Reported-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2 years agost/xa: Fix transformations when we have both source and mask samplers
Thomas Hellstrom [Tue, 13 Nov 2018 13:13:38 +0000 (14:13 +0100)]
st/xa: Fix transformations when we have both source and mask samplers

In the case when we had both source and mask samplers, transformations were
typically not applied correctly.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2 years agost/xa: Support a couple of new formats
Thomas Hellstrom [Fri, 9 Nov 2018 12:19:12 +0000 (13:19 +0100)]
st/xa: Support a couple of new formats

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2 years agost/xa: Support higher color precision for solid pictures
Thomas Hellstrom [Wed, 7 Nov 2018 13:55:20 +0000 (14:55 +0100)]
st/xa: Support higher color precision for solid pictures

The only solid fill picture type we supported only had 8 bit color
channels. Add a new solid picture type that supports float channels.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2 years agost/xa: Render update. Better support for solid pictures
Thomas Hellstrom [Wed, 7 Nov 2018 10:14:04 +0000 (11:14 +0100)]
st/xa: Render update. Better support for solid pictures

Remove unused and obsolete code for gradients and component-alpha
Support solid source- and mask pictures using a variable number
of samplers in the composite pipeline rather than the fixed number
we used before.

Tested using rendercheck for XA.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2 years agonir: Allow to skip integer ops in nir_lower_to_source_mods
Gert Wollny [Mon, 12 Nov 2018 08:17:34 +0000 (09:17 +0100)]
nir: Allow to skip integer ops in nir_lower_to_source_mods

Some hardware supports source mods only for float operations. Make it
possible to skip lowering to source mods in these cases.

v2: use option flags instead of a boolean (Jason Ekstrand)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir/spirv: cast shift operand to u32
Karol Herbst [Thu, 26 Apr 2018 14:54:26 +0000 (16:54 +0200)]
nir/spirv: cast shift operand to u32

v2: fix for specialization constants as well

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2 years agonir: replace nir_load_system_value calls with appropiate builder functions
Karol Herbst [Thu, 19 Jul 2018 09:44:31 +0000 (11:44 +0200)]
nir: replace nir_load_system_value calls with appropiate builder functions

this helps reduce the overall code changes when a bit_size parameter is
added to nir_load_system_value

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2 years agonir: add const_index parameters to system value builder function
Karol Herbst [Thu, 19 Jul 2018 09:42:08 +0000 (11:42 +0200)]
nir: add const_index parameters to system value builder function

this allows to replace some nir_load_system_value calls with the specific
system value constructor

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2 years agoradv: make use of nir_move_out_const_to_consumer()
Timothy Arceri [Wed, 7 Nov 2018 04:20:41 +0000 (15:20 +1100)]
radv: make use of nir_move_out_const_to_consumer()

vkpipeline-db results:

Totals from affected shaders:
SGPRS: 28400 -> 28576 (0.62 %)
VGPRS: 27916 -> 27692 (-0.80 %)
Spilled SGPRs: 140 -> 138 (-1.43 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1534456 -> 1520560 (-0.91 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 3541 -> 3582 (1.16 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoanv: move helper function internally
Lionel Landwerlin [Fri, 2 Nov 2018 10:21:20 +0000 (10:21 +0000)]
anv: move helper function internally

It's only used in anv_image.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv: use image aspects rather than computed ones
Lionel Landwerlin [Tue, 30 Oct 2018 23:44:05 +0000 (23:44 +0000)]
anv: use image aspects rather than computed ones

This shouldn't make any difference but I feel uneasy to use the
expanded aspects that do not represent the image in its entirety. If
we ever change the implementation of the anv_image_aspect_to_plane()
helper, this is safer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv: associate vulkan formats with aspects
Lionel Landwerlin [Fri, 26 Oct 2018 13:35:59 +0000 (14:35 +0100)]
anv: associate vulkan formats with aspects

This will make it easier to associate an aspect with a plane number.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv/lower_ycbcr: make sure to set 0s on all components
Lionel Landwerlin [Fri, 26 Oct 2018 14:02:06 +0000 (15:02 +0100)]
anv/lower_ycbcr: make sure to set 0s on all components

To play around with debugging, we might want to disable one or the
other component. Having 0s as default values makes this work.
Otherwise we might have NULL components, leading to crashes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv/image: remove unused parameter
Lionel Landwerlin [Thu, 1 Nov 2018 16:53:48 +0000 (16:53 +0000)]
anv/image: remove unused parameter

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv: simplify internal address offset
Lionel Landwerlin [Thu, 25 Oct 2018 17:35:32 +0000 (18:35 +0100)]
anv: simplify internal address offset

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agomeson: fix wayland-less builds
Eric Engestrom [Thu, 11 Oct 2018 15:00:04 +0000 (16:00 +0100)]
meson: fix wayland-less builds

Those empty variables in the !wayland case are useless and running that
meson.build with them breaks the build:

  [287/850] Generating wayland-drm-client-protocol.h with a custom command.
  FAILED: src/egl/wayland/wayland-drm/wayland-drm-client-protocol.h
  client-header ../src/egl/wayland/wayland-drm/wayland-drm.xml src/egl/wayland/wayland-drm/wayland-drm-client-protocol.h
  /bin/sh: client-header: command not found
  ninja: build stopped: subcommand failed.

Fixes: d1992255bb29054fa5176 "meson: Add build Intel "anv" vulkan driver"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2 years agogbm: remove unnecessary meson include
Eric Engestrom [Thu, 11 Oct 2018 15:27:07 +0000 (16:27 +0100)]
gbm: remove unnecessary meson include

`inc_wayland_drm` is only used if wayland is built, and it's already
added in that case a few lines below.

Fixes: a29869e8720b385d3692f "gbm: Don't traverse backwards for includes"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2 years agomeson: only run vulkan's meson.build when building vulkan
Eric Engestrom [Thu, 11 Oct 2018 15:21:14 +0000 (16:21 +0100)]
meson: only run vulkan's meson.build when building vulkan

Fixes: d1992255bb29054fa5176 "meson: Add build Intel "anv" vulkan driver"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2 years agoxmlpool: update translation po files
Eric Engestrom [Mon, 12 Nov 2018 14:17:35 +0000 (14:17 +0000)]
xmlpool: update translation po files

These files are close to 4 years out of date; a lot's changed since.
Let's just check in a recently-regenerated version.

Changes generated by running `ninja xmlpool-{pot,update-po,gmo}`.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2 years agoREVIEWERS: add Vulkan reviewer group
Eric Engestrom [Wed, 31 Oct 2018 11:09:33 +0000 (11:09 +0000)]
REVIEWERS: add Vulkan reviewer group

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2 years agoREVIEWERS: add Emil as EGL reviewer
Eric Engestrom [Wed, 31 Oct 2018 11:08:22 +0000 (11:08 +0000)]
REVIEWERS: add Emil as EGL reviewer

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2 years agoREVIEWERS: add include path for EGL
Eric Engestrom [Wed, 31 Oct 2018 11:08:01 +0000 (11:08 +0000)]
REVIEWERS: add include path for EGL

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen11)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:12 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen11)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

v4: Added missing engine definition to MI_TOPOLOGY_FILTER.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen10)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:11 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen10)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

v4: Added missing engine definition to MI_TOPOLOGY_FILTER.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen9)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:10 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen9)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

v4: Added more missing engine definitions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen8)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:09 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen8)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen75)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:08 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen75)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen7)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:07 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen7)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen6)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:06 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen6)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions

v4: Added missing engine to MEDIA_GATEWAY_STATE

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen5)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:05 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen5)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen45)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:04 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen45)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added addition engine definitions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/genxml: Add engine definition to render engine instructions (gen4)
Toni Lönnberg [Thu, 8 Nov 2018 15:23:03 +0000 (17:23 +0200)]
intel/genxml: Add engine definition to render engine instructions (gen4)

Instructions meant for the render engine now have a definition specifying that
so that can differentiate instructions meant for different engines due to shared
opcodes.

v2: Divided into individual patches for each gen

v3: Added additional engine definitions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/decoder: tools: Use engine for decoding batch instructions
Toni Lönnberg [Wed, 7 Nov 2018 14:50:32 +0000 (16:50 +0200)]
intel/decoder: tools: Use engine for decoding batch instructions

The engine to which the batch was sent to is now set to the decoder context when
decoding the batch. This is needed so that we can distinguish between
instructions as the render and video pipe share some of the instruction opcodes.

v2: The engine is now in the decoder context and the batch decoder uses a local
function for finding the instruction for an engine.

v3: Spec uses engine_mask now instead of engine, replaced engine class enums
with the definitions from UAPI.

v4: Fix up aubinator_viewer (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/decoder: tools: gen_engine to drm_i915_gem_engine_class
Toni Lönnberg [Thu, 8 Nov 2018 12:41:01 +0000 (14:41 +0200)]
intel/decoder: tools: gen_engine to drm_i915_gem_engine_class

Removed the gen_engine enum and changed the involved functions to use the
drm_i915_gem_engine_class enum from UAPI instead.

v3: Wrong engine was being used for blocks in video ring

v4: Fixed aubinator_viewer.cpp
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/decoder: Engine parameter for instructions
Toni Lönnberg [Thu, 8 Nov 2018 12:48:20 +0000 (14:48 +0200)]
intel/decoder: Engine parameter for instructions

Preliminary work for adding handling of different pipes to gen_decoder. Each
instruction needs to have a definition describing which engine it is meant for.
If left undefined, by default, the instruction is defined for all engines.

v2: Changed to use the engine class definitions from UAPI

v3: Changed I915_ENGINE_CLASS_TO_MASK to use BITSET_BIT, change engine to
engine_mask, added check for incorrect engine and added the possibility to
define an instruction to multiple engines using the "|" as a delimiter in the
engine attribute.

v4: Fixed the memory leak.

v5: Removed an unnecessary ralloc_free().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agovirgl: Add command and flags to initiate debugging on the host (v2)
Gert Wollny [Wed, 12 Sep 2018 09:59:35 +0000 (11:59 +0200)]
virgl: Add command and flags to initiate debugging on the host (v2)

On the host VREND_DEBUG=guestallow must be set to let the guest override
the debug flags.

v2: Send flag string instead of flags, this avoids the need to keep
    the flags in sync.
v3: Only request host logging if the host actually understands the command

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2 years agomesa: Reference count shaders that are used by transform feedback objects
Gert Wollny [Mon, 12 Nov 2018 11:34:26 +0000 (12:34 +0100)]
mesa: Reference count shaders that are used by transform feedback objects

Transform feedback objects may hold a pointer to a shader program, and
at least in Gallium, this must be a valid pointer until
ctx->Driver.EndTransformFeedback in glEndTransformFeedback has been called
- which is conform with the spec that any program that is part of a
current rendering state should only be flagged for deletion by glDeleteProgram.
This was not handled properly for the transform feedback objects so that
a call sequence

  glUseProgram(x)
  glBeginTransformFreedback(...)
  glPauseTransformFeedback(...)
  glDeleteProgram(x)
  glEndTransformFeedback(...)

would result in a use after free bug. With this patch the transform
feedback object also updates the reference count to the used program
thereby keeping the program valid as long as the transform feedback
objects links to it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108713
Fixes: 654587696b4234d09a6b471b70e9629cf2887c27
       mesa: add end_transform_feedback() helper

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2 years agoradv: set optimal OVERWRITE_COMBINER_WATERMARK on GFX9
Samuel Pitoiset [Mon, 12 Nov 2018 08:46:14 +0000 (09:46 +0100)]
radv: set optimal OVERWRITE_COMBINER_WATERMARK on GFX9

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: set PA.SC_CONSERVATIVE_RASTERIZATION.NULL_SQUAD_AA_MASK_ENABLE
Samuel Pitoiset [Mon, 12 Nov 2018 20:59:29 +0000 (21:59 +0100)]
radv: set PA.SC_CONSERVATIVE_RASTERIZATION.NULL_SQUAD_AA_MASK_ENABLE

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: binding streamout buffers doesn't change context regs
Samuel Pitoiset [Mon, 12 Nov 2018 10:37:20 +0000 (11:37 +0100)]
radv: binding streamout buffers doesn't change context regs

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agonir: Don't lower the local work group size if it's variable.
Plamena Manolova [Sun, 11 Nov 2018 20:30:09 +0000 (22:30 +0200)]
nir: Don't lower the local work group size if it's variable.

If the local work group size is variable it won't be available
at compile time so we can't lower it in nir_lower_system_values().

Signed-off-by: Plamena Manolova <plamena.n.manolova@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2 years agoutil/ralloc: Make sizeof(linear_header) a multiple of 8
Matt Turner [Sun, 11 Nov 2018 21:44:41 +0000 (13:44 -0800)]
util/ralloc: Make sizeof(linear_header) a multiple of 8

Prior to this patch sizeof(linear_header) was 20 bytes in a
non-debug build on 32-bit platforms. We do some pointer arithmetic to
calculate the next available location with

   ptr = (linear_size_chunk *)((char *)&latest[1] + latest->offset);

in linear_alloc_child(). The &latest[1] adds 20 bytes, so an allocation
would only be 4-byte aligned.

On 32-bit SPARC a 'sttw' instruction (which stores a consecutive pair of
4-byte registers to memory) requires an 8-byte aligned address. Such an
instruction is used to store to an 8-byte integer type, like intmax_t
which is used in glcpp's expression_value_t struct.

As a result of the 4-byte alignment returned by linear_alloc_child() we
would generate a SIGBUS (unaligned exception) on SPARC.

According to the GNU libc manual malloc() always returns memory that has
at least an alignment of 8-bytes [1]. I think our allocator should do
the same.

So, simple fix with two parts:

   (1) Increase SUBALLOC_ALIGNMENT to 8 unconditionally.
   (2) Mark linear_header with an aligned attribute, which will cause
       its sizeof to be rounded up to that alignment. (We already do
       this for ralloc_header)

With this done, all Mesa's unit tests now pass on SPARC.

[1] https://www.gnu.org/software/libc/manual/html_node/Aligned-Memory-Blocks.html

Fixes: 47e17586924f ("glcpp: use the linear allocator for most objects")
Bug: https://bugs.gentoo.org/636326
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoutil/ralloc: Switch from DEBUG to NDEBUG
Matt Turner [Sun, 11 Nov 2018 21:36:29 +0000 (13:36 -0800)]
util/ralloc: Switch from DEBUG to NDEBUG

The debug code is all asserts, so protect it with the same thing that
controls assert.

Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agonir: add support for removing redundant stores to copy prop var
Timothy Arceri [Thu, 8 Nov 2018 04:45:34 +0000 (15:45 +1100)]
nir: add support for removing redundant stores to copy prop var

For example the following type of thing is seen in TCS from
a number of Vulkan and DXVK games:

vec1 32 ssa_557 = deref_var &oPatch (shader_out float)
vec1 32 ssa_558 = intrinsic load_deref (ssa_557) ()
vec1 32 ssa_559 = deref_var &oPatch@42 (shader_out float)
vec1 32 ssa_560 = intrinsic load_deref (ssa_559) ()
vec1 32 ssa_561 = deref_var &oPatch@43 (shader_out float)
vec1 32 ssa_562 = intrinsic load_deref (ssa_561) ()
intrinsic store_deref (ssa_557, ssa_558) (1) /* wrmask=x */
intrinsic store_deref (ssa_559, ssa_560) (1) /* wrmask=x */
intrinsic store_deref (ssa_561, ssa_562) (1) /* wrmask=x */

No shader-db changes on i965 (SKL).

vkpipeline-db results RADV (VEGA):

Totals from affected shaders:
SGPRS: 7832 -> 7728 (-1.33 %)
VGPRS: 6476 -> 6740 (4.08 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 469572 -> 456596 (-2.76 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 989 -> 960 (-2.93 %)
Wait states: 0 -> 0 (0.00 %)

The Max Waves and VGPRS changes here are misleading. What is
happening is a bunch of TCS outputs are being optimised away as
they are now recognised as unused. This results in more varyings
being compacted via nir_compact_varyings() which can result in
more register pressure when they are not packed in an optimal way.
This is an existing problem independent of this patch. I've run
some benchmarks and haven't noticed any performance regressions
in affected games.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv/i965: make use of nir_link_constant_varyings()
Timothy Arceri [Wed, 7 Nov 2018 03:29:18 +0000 (14:29 +1100)]
anv/i965: make use of nir_link_constant_varyings()

shader-db results for SLK:

total instructions in shared programs: 13106498 -> 13091573 (-0.11%)
instructions in affected programs: 1186244 -> 1171319 (-1.26%)
helped: 6186
HURT: 0

total cycles in shared programs: 332062633 -> 331961653 (-0.03%)
cycles in affected programs: 8537165 -> 8436185 (-1.18%)
helped: 5371
HURT: 862

LOST:   6
GAINED: 14

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoegl: Improve the debugging of gbm format matching in DRI configs.
Eric Anholt [Mon, 29 Oct 2018 16:28:00 +0000 (09:28 -0700)]
egl: Improve the debugging of gbm format matching in DRI configs.

Previously the debug would be:

libEGL debug: No DRI config supports native format 0x20203852
libEGL debug: No DRI config supports native format 0x38385247

but

libEGL debug: No DRI config supports native format R8
libEGL debug: No DRI config supports native format GR88

is a lot easier to understand.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2 years agogbm: Introduce a helper function for printing GBM format names.
Eric Anholt [Fri, 2 Nov 2018 21:35:06 +0000 (14:35 -0700)]
gbm: Introduce a helper function for printing GBM format names.

This requires that the caller make a little (stack) allocation to store
the string.

v2: Use gbm_format_canonicalize (suggested by Daniel)

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2 years agogbm: Move gbm_format_canonicalize() to the core.
Eric Anholt [Thu, 8 Nov 2018 17:57:32 +0000 (09:57 -0800)]
gbm: Move gbm_format_canonicalize() to the core.

I want it for the format name debugging code.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2 years agomeson: fix libatomic tests
Dylan Baker [Fri, 9 Nov 2018 20:56:00 +0000 (12:56 -0800)]
meson: fix libatomic tests

There are two problems:
1) the extra underscore in MISSING_64BIT_ATOMICS
2) we should link with libatomic if the previous test decided we needed
   it

Fixes: d1992255bb29054fa51763376d125183a9f602f3
       ("meson: Add build Intel "anv" vulkan driver")
Reviewed-and-Tested-by: Matt Turner <mattst88@gmail.com>
2 years agomesa: mark GL_SR8_EXT non-renderable on GLES
Marek Olšák [Fri, 9 Nov 2018 21:47:46 +0000 (16:47 -0500)]
mesa: mark GL_SR8_EXT non-renderable on GLES

Fixes: dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.sr8_ext
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2 years agost/mesa: disable L3 thread pinning
Marek Olšák [Mon, 12 Nov 2018 20:43:58 +0000 (15:43 -0500)]
st/mesa: disable L3 thread pinning

This implementation can have massive drawbacks.

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
2 years agonir: add lowering for ffloor
Christian Gmeiner [Sat, 1 Sep 2018 19:15:27 +0000 (21:15 +0200)]
nir: add lowering for ffloor

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoutil: Fix warning in u_cpu_detect on non-x86
Alyssa Rosenzweig [Sun, 11 Nov 2018 19:09:40 +0000 (11:09 -0800)]
util: Fix warning in u_cpu_detect on non-x86

regs is only set and used on x86; on other platforms (like ARM), this
code causes a trivial warning, solved by moving the regs declaration to
the architecture-dependent usage.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>