mesa.git
3 years agov3d: Fold comparisons for IF conditions into the flags for the IF.
Eric Anholt [Sat, 29 Dec 2018 00:31:07 +0000 (16:31 -0800)]
v3d: Fold comparisons for IF conditions into the flags for the IF.

total instructions in shared programs: 6193810 -> 6192844 (-0.02%)
instructions in affected programs: 800373 -> 799407 (-0.12%)

3 years agov3d: Don't try to fold non-SSA-src comparisons into bcsels.
Eric Anholt [Mon, 31 Dec 2018 21:09:45 +0000 (13:09 -0800)]
v3d: Don't try to fold non-SSA-src comparisons into bcsels.

There could have been a write of a src in between the comparison and the
bcsel that would invalidate the comparison.

3 years agov3d: Move the "Find the ALU instruction generating our bool" out of bcsel.
Eric Anholt [Mon, 31 Dec 2018 21:05:06 +0000 (13:05 -0800)]
v3d: Move the "Find the ALU instruction generating our bool" out of bcsel.

This will be reused for if statements.

3 years agov3d: Simplify the emission of comparisons for the bcsel optimization.
Eric Anholt [Fri, 28 Dec 2018 21:45:25 +0000 (13:45 -0800)]
v3d: Simplify the emission of comparisons for the bcsel optimization.

I wanted to reuse the comparison stuff for nir_ifs, but for that I just
want the flags and no destination value.  Splitting the conditions from
the destinations ended up cleaning the existing code up, anyway.

3 years agov3d: Don't forget to include RT writes in precompiles.
Eric Anholt [Sun, 30 Dec 2018 16:59:54 +0000 (08:59 -0800)]
v3d: Don't forget to include RT writes in precompiles.

Looking at some assembly dumps for an optimization, we were clearly
missing important parts of the shader!

3 years agov3d: Fix segfault when failing to compile a program.
Eric Anholt [Mon, 31 Dec 2018 19:51:01 +0000 (11:51 -0800)]
v3d: Fix segfault when failing to compile a program.

We'll still fail at draw time, but this avoids a regression in shader-db
execution once I enable TLB writes in precompiles.

Fixes: b38e4d313fc2 ("v3d: Create a state uploader for packing our shaders together.")
3 years agoradeonsi: always unmap texture CPU mappings on 32-bit CPU architectures
Marek Olšák [Fri, 14 Dec 2018 21:03:00 +0000 (16:03 -0500)]
radeonsi: always unmap texture CPU mappings on 32-bit CPU architectures

Team Fortress 2 32-bit version runs out of the CPU address space.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: remove unused variables in si_insert_input_ptr
Marek Olšák [Fri, 14 Dec 2018 20:08:50 +0000 (15:08 -0500)]
radeonsi: remove unused variables in si_insert_input_ptr

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: use u_decomposed_prims_for_vertices instead of u_prims_for_vertices
Marek Olšák [Sat, 10 Nov 2018 03:27:05 +0000 (22:27 -0500)]
radeonsi: use u_decomposed_prims_for_vertices instead of u_prims_for_vertices

It seems to be the same, but this doesn't use integer division with
a variable divisor.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: make si_cp_wait_mem more configurable
Marek Olšák [Mon, 3 Dec 2018 19:58:08 +0000 (14:58 -0500)]
radeonsi: make si_cp_wait_mem more configurable

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: call si_fix_resource_usage for the GS copy shader as well
Marek Olšák [Tue, 13 Nov 2018 02:29:27 +0000 (21:29 -0500)]
radeonsi: call si_fix_resource_usage for the GS copy shader as well

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: don't emit redundant PKT3_NUM_INSTANCES packets
Marek Olšák [Tue, 13 Nov 2018 01:38:46 +0000 (20:38 -0500)]
radeonsi: don't emit redundant PKT3_NUM_INSTANCES packets

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agonir: add a way to print the deref chain
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 20:13:46 +0000 (12:13 -0800)]
nir: add a way to print the deref chain

Makes debugging easier when we care about the deref chain and not the
deref instruction itself.  To make it take a const pointer, constify
some of the static functions in nir_print.c.

Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agomeson: Error out if building nouveau and using LLVM without rtti
Dylan Baker [Tue, 1 Jan 2019 03:23:52 +0000 (19:23 -0800)]
meson: Error out if building nouveau and using LLVM without rtti

Nouveau requires rtti. Often LLVM is configured without rtti, and code
with and without cannot be linked safely. Lets just error out if nouveau
is requested and llvm is built without rtti.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109202
Fixes: c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4
       ("meson: fix builds against LLVM built without rtti")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoegl/haiku: Fix reference to disp vs dpy
Alexander von Gluck IV [Thu, 27 Dec 2018 20:41:47 +0000 (20:41 +0000)]
egl/haiku: Fix reference to disp vs dpy

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 00992700c9a812a54563 "egl: set the EGLDevice when creating a display"
3 years agocompiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
Iago Toral Quiroga [Thu, 31 May 2018 08:34:03 +0000 (10:34 +0200)]
compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()

The 16-bit polynomial execution doesn't meet Khronos precision requirements.
Also, the half-float denorm range starts at 2^(-14) and with asin taking input
values in the range [0, 1], polynomial approximations can lead to flushing
relatively easy.

An alternative is to use the atan2 formula to compute asin, which is the
reference taken by Khronos to determine precision requirements, but that
ends up generating too many additional instructions when compared to the
polynomial approximation. Specifically, for the Intel case, doing this
adds +41 instructions to the program for each asin/acos call, which looks
like an undesirable trade off.

So for now we take the easy way out and fallback to using the 32-bit
polynomial approximation, which is better (faster) than the 16-bit atan2
implementation and gives us better precision that matches Khronos
requirements.

v2:
 - Fallback to 32-bit using recursion (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit frexp
Iago Toral Quiroga [Tue, 15 May 2018 08:25:10 +0000 (10:25 +0200)]
compiler/spirv: implement 16-bit frexp

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit hyperbolic trigonometric functions
Iago Toral Quiroga [Wed, 18 Apr 2018 08:14:11 +0000 (10:14 +0200)]
compiler/spirv: implement 16-bit hyperbolic trigonometric functions

v2:
 - use nir_fadd_imm and nir_fmul_imm helpers (Jason)

v3:
 - since we need to define one for fsub use it for fdiv too (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit exp and log
Iago Toral Quiroga [Wed, 18 Apr 2018 08:09:33 +0000 (10:09 +0200)]
compiler/spirv: implement 16-bit exp and log

v2
 - use nir_fmul_imm helper (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit atan2
Iago Toral Quiroga [Wed, 18 Apr 2018 08:07:54 +0000 (10:07 +0200)]
compiler/spirv: implement 16-bit atan2

v2:
 - fix huge_val for 16-bit, it was mean't to be 2^14 not 10^14.

v3:
 - rebase on top of new bool sized opcodes
 - use nir_b2f helper
 - use nir_fmul_imm helper

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit atan
Iago Toral Quiroga [Wed, 18 Apr 2018 07:36:41 +0000 (09:36 +0200)]
compiler/spirv: implement 16-bit atan

v2:
 - use nir_fadd_imm and nir_fmul_imm helpers (Jason)
 - rebased on top of new sized boolean opcodes
 - use nir_b2f helper

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit acos
Iago Toral Quiroga [Wed, 18 Apr 2018 07:15:01 +0000 (09:15 +0200)]
compiler/spirv: implement 16-bit acos

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit asin
Iago Toral Quiroga [Wed, 18 Apr 2018 06:47:53 +0000 (08:47 +0200)]
compiler/spirv: implement 16-bit asin

v2:
  - use nir_fmul_imm and nir_fadd_imm helpers (Jason)

v3:
 - missed one case where we need to replace nir_imm_float
   with nir_imm_floatN_t (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: handle 16-bit float in radians() and degrees()
Iago Toral Quiroga [Tue, 17 Apr 2018 09:39:48 +0000 (11:39 +0200)]
compiler/spirv: handle 16-bit float in radians() and degrees()

v2:
 - use nir_imm_fmul helper (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/nir: add nir_fadd_imm() and nir_fmul_imm() helpers
Iago Toral Quiroga [Fri, 14 Dec 2018 08:28:56 +0000 (09:28 +0100)]
compiler/nir: add nir_fadd_imm() and nir_fmul_imm() helpers

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/nir: add a nir_b2f() helper
Iago Toral Quiroga [Fri, 14 Dec 2018 07:54:36 +0000 (08:54 +0100)]
compiler/nir: add a nir_b2f() helper

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir: link time opt duplicate varyings
Timothy Arceri [Mon, 10 Dec 2018 08:36:47 +0000 (19:36 +1100)]
nir: link time opt duplicate varyings

If we are outputting the same value to more than one output
component rewrite the inputs to read from a single component.

This will allow the duplicate varying components to be optimised
away by the existing opts.

shader-db results i965 (SKL):

total instructions in shared programs: 12869230 -> 12860886 (-0.06%)
instructions in affected programs: 322601 -> 314257 (-2.59%)
helped: 3080
HURT: 8

total cycles in shared programs: 317792574 -> 317730593 (-0.02%)
cycles in affected programs: 2584925 -> 2522944 (-2.40%)
helped: 2975
HURT: 477

shader-db results radeonsi (VEGA):

SGPRS: 31576 -> 31664 (0.28 %)
VGPRS: 17484 -> 17064 (-2.40 %)
Spilled SGPRs: 184 -> 167 (-9.24 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 583340 -> 569368 (-2.40 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 6162 -> 6270 (1.75 %)
Wait states: 0 -> 0 (0.00 %)

vkpipeline-db results RADV (VEGA):

Totals from affected shaders:
SGPRS: 14880 -> 15080 (1.34 %)
VGPRS: 10872 -> 10888 (0.15 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 674016 -> 668396 (-0.83 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 2708 -> 2704 (-0.15 %)
Wait states: 0 -> 0 (0.00 %

V2: bunch of tidy ups suggested by Jason

Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agonir: rework nir_link_opt_varyings()
Timothy Arceri [Wed, 19 Dec 2018 09:09:42 +0000 (20:09 +1100)]
nir: rework nir_link_opt_varyings()

This just cleans things up a little and make things more safe for
derefs.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agonir: add can_replace_varying() helper
Timothy Arceri [Tue, 11 Dec 2018 00:53:54 +0000 (11:53 +1100)]
nir: add can_replace_varying() helper

This will be reused by the following patch.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agonir: rename nir_link_constant_varyings() nir_link_opt_varyings()
Timothy Arceri [Tue, 11 Dec 2018 00:49:00 +0000 (11:49 +1100)]
nir: rename nir_link_constant_varyings() nir_link_opt_varyings()

The following patches will add support for an additional
optimisation so this function will no longer just optimise varying
constants.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agost/glsl_to_nir: call nir_lower_load_const_to_scalar() in the st
Timothy Arceri [Tue, 11 Dec 2018 04:06:37 +0000 (15:06 +1100)]
st/glsl_to_nir: call nir_lower_load_const_to_scalar() in the st

This will help the new opt introduced in the following patches
allowing us to remove extra duplicate varyings.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agoradeonsi: make use of ac_are_tessfactors_def_in_all_invocs()
Timothy Arceri [Sat, 15 Dec 2018 04:27:01 +0000 (15:27 +1100)]
radeonsi: make use of ac_are_tessfactors_def_in_all_invocs()

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()
Timothy Arceri [Tue, 18 Dec 2018 01:05:31 +0000 (12:05 +1100)]
ac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()

The following patch will use this with the radeonsi NIR backend
but I've added it to ac so we can use it with RADV in future.

This is a NIR implementation of the tgsi function
tgsi_scan_tess_ctrl().

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: remove unrequired param in si_nir_scan_tess_ctrl()
Timothy Arceri [Tue, 18 Dec 2018 01:04:26 +0000 (12:04 +1100)]
radeonsi: remove unrequired param in si_nir_scan_tess_ctrl()

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agotgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()
Timothy Arceri [Fri, 14 Dec 2018 04:36:02 +0000 (15:36 +1100)]
tgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()

The previous code used a do while loop and continues after walking
a nested loop/if-statement. This means we end up evaluating the
last instruction from the nested block against the while condition
and potentially exit early if it matches the exit condition of the
outer block.

Fixes: 386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agotgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()
Timothy Arceri [Fri, 14 Dec 2018 04:09:38 +0000 (15:09 +1100)]
tgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()

This just happened not to crash/assert because all loops have at
least 1 if-statement and due to a second bug we end up matching
the same ENDIF to exit both the iteration over the if-statment
and the loop.

The second bug is fixed in the following patch.

Fixes: 386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agonv30: disable rendering to 3D textures
Ilia Mirkin [Tue, 1 Jan 2019 20:06:34 +0000 (15:06 -0500)]
nv30: disable rendering to 3D textures

There's no way to tell the 3D engine about swizzling on such textures.
While rendering to NPOT ones may be possible, there's no great way to
expose that in gallium, nor would there be any practical benefit.

Fixes the non-compressed-format "copyteximage 3D" failures. Something
odd going on with the compressed formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agoradv: Do a cache flush if needed before reading predicates.
Bas Nieuwenhuizen [Sun, 30 Dec 2018 22:37:11 +0000 (23:37 +0100)]
radv: Do a cache flush if needed before reading predicates.

This caused random failures for two conditional rendering tests:

dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_discard
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_no_discard

These wrote the predicate with the vertex shader, did a barrier and then
started the conditional rendering. However the cache flushes for the barrier
only happen on first draw, so after the predicate has been read.

Fixes: e45ba51ea45 "radv: add support for VK_EXT_conditional_rendering"
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoanv/autotools: make sure tests link with -msse2
Erik Faye-Lund [Sun, 30 Dec 2018 21:57:46 +0000 (22:57 +0100)]
anv/autotools: make sure tests link with -msse2

Without this, I get the following error when building the tests with
autotools on i686:

---8<---
src/intel/common/gen_clflush.h: In function ‘gen_clflush_range’:
src/intel/common/gen_clflush.h:37:7: warning: implicit declaration of function ‘__builtin_ia32_clflush’; did you mean ‘__builtin_ia32_pause’? [-Wimplicit-function-declaration]
       __builtin_ia32_clflush(p);
       ^~~~~~~~~~~~~~~~~~~~~~
       __builtin_ia32_pause
src/intel/common/gen_clflush.h: In function ‘gen_flush_range’:
src/intel/common/gen_clflush.h:45:4: warning: implicit declaration of function ‘__builtin_ia32_mfence’; did you mean ‘__builtin_ia32_fnclex’? [-Wimplicit-function-declaration]
    __builtin_ia32_mfence();
    ^~~~~~~~~~~~~~~~~~~~~
    __builtin_ia32_fnclex
---8<---

The erros are generated for each of these files:
- mesa/src/intel/vulkan/tests/state_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool.c
- mesa/src/intel/vulkan/tests/block_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool_free_list_only.c

This is obviously because gen_clflush.h contains code that uses
intrinsics that are only available with SSE3. Since the driver already
uses SSE3, it seems reasonable to add this to the tests as well.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Eric Engeström <eric@engestrom.ch>
3 years agoanv/meson: make sure tests link with -msse2
Erik Faye-Lund [Sun, 30 Dec 2018 21:09:06 +0000 (22:09 +0100)]
anv/meson: make sure tests link with -msse2

Without this, I get the following error when building the tests using
meson on i686:

---8<---
In file included from ../../../mesa/src/intel/vulkan/anv_private.h:46,
                 from ../../../mesa/src/intel/vulkan/tests/state_pool_no_free.c:26:
../../../mesa/src/intel/common/gen_clflush.h: In function ‘gen_clflush_range’:
../../../mesa/src/intel/common/gen_clflush.h:37:7: error: implicit declaration of function ‘__builtin_ia32_clflush’; did you mean ‘__builtin_ia32_pause’? [-Werror=implicit-function-declaration]
       __builtin_ia32_clflush(p);
       ^~~~~~~~~~~~~~~~~~~~~~
       __builtin_ia32_pause
../../../mesa/src/intel/common/gen_clflush.h: In function ‘gen_flush_range’:
../../../mesa/src/intel/common/gen_clflush.h:45:4: error: implicit declaration of function ‘__builtin_ia32_mfence’; did you mean ‘__builtin_ia32_fnclex’? [-Werror=implicit-function-declaration]
    __builtin_ia32_mfence();
    ^~~~~~~~~~~~~~~~~~~~~
    __builtin_ia32_fnclex
---8<---

The errors are generated for each of these files:
- mesa/src/intel/vulkan/tests/state_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool.c
- mesa/src/intel/vulkan/tests/block_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool_free_list_only.c

This is obviously because gen_clflush.h contains code that uses
intrinsics that are only available with SSE3. Since the driver already
uses SSE3, it seems reasonable to add this to the tests as well.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engeström <eric@engestrom.ch>
3 years agonv30: fix some s3tc layout issues
Ilia Mirkin [Mon, 31 Dec 2018 00:17:10 +0000 (19:17 -0500)]
nv30: fix some s3tc layout issues

s3tc layouts are a bit finicky - they're packed, but not swizzled.
Adjust logic to allow for that case:

  - Don't set a uniform pitch for POT-sized compressed textures
  - Adjust define_rect API to be less confused about block sizes
  - Only mark a texture as linear if it has a uniform pitch set

This has been tested to fix xonotic (as well as the s3tc-* piglits)
on nv3x and keeps it working on nv4x.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: use correct helper to get blocks in y direction
Ilia Mirkin [Thu, 27 Dec 2018 15:27:43 +0000 (10:27 -0500)]
nv30: use correct helper to get blocks in y direction

This doesn't matter since all compressed formats supported by this
hardware use square blocks, but best to use the correct helper.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: add support for multi-layer transfers
Ilia Mirkin [Thu, 27 Dec 2018 15:24:56 +0000 (10:24 -0500)]
nv30: add support for multi-layer transfers

This logic mirrors what we do on nv50. The relatively new
texture_subdata callback can cause this to happen with 3D textures,
which is triggered at least by xonotic, and probably many piglits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: fix rare issue with fp unbinding not finding the bufctx
Ilia Mirkin [Thu, 27 Dec 2018 04:01:21 +0000 (23:01 -0500)]
nv30: fix rare issue with fp unbinding not finding the bufctx

If the last-active context gets deleted, the pushbuf doesn't have a
bufctx to reference. Then there could be a sequence of binds which would
trigger a reset on that bin before validation was done. Instead we just
pass in the bufctx in question directly.

All other instances of PUSH_RESET happen strictly after a validation is
run.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102349
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: avoid setting user_priv without setting cur_ctx
Ilia Mirkin [Thu, 27 Dec 2018 03:58:54 +0000 (22:58 -0500)]
nv30: avoid setting user_priv without setting cur_ctx

The whole user_priv thing is a mess, but as long as it's there, it
basically has to map 1:1 to the cur_ctx. Unfortunately we were setting
user_priv to some context, then that context could get deleted without
any draws/validations in it, leading user_priv to become NULL, with
cur_ctx still pointing at some old context. Then we wouldn't run the
switch logic, which in turn led to a NULL bufctx being dereferenced.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102349
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agov3d: Add support for gl_HelperInvocation.
Eric Anholt [Fri, 28 Dec 2018 19:30:52 +0000 (11:30 -0800)]
v3d: Add support for gl_HelperInvocation.

We can just look at the MSF flags -- if they're unset, then we're
definitely in a helper invocation.  Fixes
dEQP-GLES31.functional.shaders.helper_invocation.* with GLES3.1 enabled.

3 years agov3d: Add support for textureSize() on MSAA textures.
Eric Anholt [Fri, 28 Dec 2018 18:09:00 +0000 (10:09 -0800)]
v3d: Add support for textureSize() on MSAA textures.

Fixes failures in
dEQP-GLES31.functional.shaders.builtin_functions.texture_size.samples_1_texture_2d
in the GLES3.1 suite.

3 years agov3d: Add support for requesting the sample offsets.
Eric Anholt [Fri, 28 Dec 2018 07:20:53 +0000 (23:20 -0800)]
v3d: Add support for requesting the sample offsets.

3 years agov3d: Add support for non-constant texture offsets.
Eric Anholt [Thu, 27 Dec 2018 07:35:22 +0000 (23:35 -0800)]
v3d: Add support for non-constant texture offsets.

Fixes
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_pot.clamp_to_edge_repeat
and others.

3 years agov3d: Force sampling from base level for tg4.
Eric Anholt [Thu, 27 Dec 2018 07:15:30 +0000 (23:15 -0800)]
v3d: Force sampling from base level for tg4.

This is what the GLSL ES 310 spec tells us to do, but apparently the
"gather mode" flag doesn't imply it in the HW.  Fixes
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8.filter_mode.min_nearest_mipmap_linear_mag_linear

3 years agov3d: Add a note for a potential performance win on multop/umul24.
Eric Anholt [Wed, 26 Dec 2018 20:54:58 +0000 (12:54 -0800)]
v3d: Add a note for a potential performance win on multop/umul24.

Noticed while debugging a testcase.

3 years agov3d: Dead-code eliminate unused flags updates.
Eric Anholt [Sat, 29 Dec 2018 20:44:22 +0000 (12:44 -0800)]
v3d: Dead-code eliminate unused flags updates.

The greedy comparison folding in bcsel means that we may have left the
original bool-generating NIR ALU instruction dead, but DCE wasn't
eliminating the VIR code for it because of the flags updates.

total instructions in shared programs: 5186024 -> 5100894 (-1.64%)
instructions in affected programs: 1448695 -> 1363565 (-5.88%)

3 years agov3d: Don't generate temps for comparisons.
Eric Anholt [Sat, 29 Dec 2018 21:20:35 +0000 (13:20 -0800)]
v3d: Don't generate temps for comparisons.

This was just generated work for vir_opt_dead_code and cluttered up the
dumps.

3 years agov3d: Move "does this instruction have flags" from sched to generic helpers.
Eric Anholt [Sat, 29 Dec 2018 19:00:25 +0000 (11:00 -0800)]
v3d: Move "does this instruction have flags" from sched to generic helpers.

I wanted to reuse it for DCE of flags updates.

3 years agov3d: Drop incorrect dependency for flpop.
Eric Anholt [Sat, 29 Dec 2018 06:02:27 +0000 (22:02 -0800)]
v3d: Drop incorrect dependency for flpop.

It is just shifting probably-means-flags bits out of a value, it doesn't
actually update the flags on its own.

3 years agov3d: Drop unused count_nir_instrs() helper.
Eric Anholt [Sat, 29 Dec 2018 20:30:19 +0000 (12:30 -0800)]
v3d: Drop unused count_nir_instrs() helper.

This was for shader-db, but I haven't cared about NIR instruction counts
in a long time.

3 years agov3d: Hook up some shader-db output to GL_ARB_debug_output.
Eric Anholt [Thu, 20 Dec 2018 15:45:58 +0000 (07:45 -0800)]
v3d: Hook up some shader-db output to GL_ARB_debug_output.

This allows the original shader-db project's run.c runner to parse things
easily, and is probably a good thing to have for GL_ARB_debug_output in
general.  I formatted it more like Intel's so I can mostly reuse their
report script.

3 years agov3d: Add a "precompile" debug flag for shader-db.
Eric Anholt [Thu, 20 Dec 2018 01:22:41 +0000 (17:22 -0800)]
v3d: Add a "precompile" debug flag for shader-db.

I've been using my apitrace-based shader-db so far, but it's slow
(apitrace decompression), intrusive (apitrace windows spamming the
screen), and doesn't have much coverage.  The original shader-db provides
a lot more coverage and compiles faster, at the expense of not having the
actual runtime variant key.  As v3d has a lot less runtime variation than
vc4 did, this tradeoff makes more sense.

3 years agov3d: Fix uniform pretty printing assertion failure with branches.
Eric Anholt [Thu, 20 Dec 2018 20:00:34 +0000 (12:00 -0800)]
v3d: Fix uniform pretty printing assertion failure with branches.

Fixes: 248a7fb392ba ("v3d: Do uniform pretty-printing in the QPU dump.")
3 years agomeson: Override C++ standard to gnu++11 when building with altivec on ppc64
Dylan Baker [Tue, 4 Dec 2018 21:52:19 +0000 (13:52 -0800)]
meson: Override C++ standard to gnu++11 when building with altivec on ppc64

Otherwise there will be symbol collisions for the vector name.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108943
Distro Bug: https://bugs.gentoo.org/673622
Fixes: 42ea0631f108d82554339530d6c88aa1b448af1e
       ("meson: build clover")
Acked-by: Matt Turner <mattst88@gmail.com>
3 years agointel/aub_viewer: highlight true booleans
Lionel Landwerlin [Sun, 18 Nov 2018 17:25:46 +0000 (17:25 +0000)]
intel/aub_viewer: highlight true booleans

Useful to spot PIPE_CONTROL flags.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: fold binding/sampler table items
Lionel Landwerlin [Sun, 12 Aug 2018 18:17:27 +0000 (19:17 +0100)]
intel/aub_viewer: fold binding/sampler table items

Makes things easier to read rather than a long block of text.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: fix shader view
Lionel Landwerlin [Wed, 19 Dec 2018 17:52:06 +0000 (17:52 +0000)]
intel/aub_viewer: fix shader view

Not decoding the shader at the right offset.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: print address of missing shader
Lionel Landwerlin [Mon, 5 Nov 2018 20:47:46 +0000 (20:47 +0000)]
intel/aub_viewer: print address of missing shader

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: fixup 0x address prefix
Lionel Landwerlin [Wed, 10 Oct 2018 21:30:04 +0000 (22:30 +0100)]
intel/aub_viewer: fixup 0x address prefix

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: fix shader get_bo
Lionel Landwerlin [Fri, 14 Sep 2018 20:19:21 +0000 (21:19 +0100)]
intel/aub_viewer: fix shader get_bo

Instruction addresses are always in ppgtt space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agoradeonsi: Enable adaptive_sync by default for radeon
Nicholas Kazlauskas [Tue, 23 Oct 2018 15:38:52 +0000 (11:38 -0400)]
radeonsi: Enable adaptive_sync by default for radeon

It's better to let most applications make use of adaptive sync
by default. Problematic applications can be placed on the blacklist
or the user can manually disable the feature.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
3 years agoloader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property
Nicholas Kazlauskas [Tue, 23 Oct 2018 15:38:51 +0000 (11:38 -0400)]
loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property

The DDX driver can be notified of adaptive sync suitability by
flagging the application's window with the _VARIABLE_REFRESH property.

This property is set on the first swap the application performs
when adaptive_sync is set to true in the drirc.

It's performed here instead of when the loader is initialized for
two reasons:

(1) The window's drawable can be missing during loader init.
    This can be observed during the Unigine Superposition benchmark.

(2) Adaptive sync will only be enabled closer to when the application
    actually begins rendering.

If adaptive_sync is false then the _VARIABLE_REFRESH property
is deleted on loader init.

The property is only managed on the glx DRI3 backend for now. This
should cover most common applications and games on modern hardware.

Vulkan support can be implemented in a similar manner but would likely
require splitting the function out into a common helper function.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
3 years agodrirc: Initial blacklist for adaptive sync
Nicholas Kazlauskas [Tue, 23 Oct 2018 15:38:50 +0000 (11:38 -0400)]
drirc: Initial blacklist for adaptive sync

Applications that don't present at a predictable rate (ie. not games)
shouldn't have adapative sync enabled. This list covers some of the
common desktop compositors, web browsers and video players.

[ Michel Dänzer: Added entry for firefox-esr ]

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
3 years agoutil: Add adaptive_sync driconf option
Nicholas Kazlauskas [Tue, 23 Oct 2018 15:38:49 +0000 (11:38 -0400)]
util: Add adaptive_sync driconf option

This option lets the user decide whether mesa should notify the
window manager / DDX driver that the current application is adaptive
sync capable.

It's off by default.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
3 years agoutil: Get program name based on path when possible
Nicholas Kazlauskas [Tue, 23 Oct 2018 15:38:48 +0000 (11:38 -0400)]
util: Get program name based on path when possible

Some programs start with the path and command line arguments in
argv[0] (program_invocation_name). Chromium is an example of
an application using mesa that does this.

This tries to query the real path for the symbolic link /proc/self/exe
to find the program name instead. It only uses the realpath if it
was a prefix of the invocation to avoid breaking wine programs.

Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoetnaviv: Consolidate buffer references from framebuffers
Tomeu Vizoso [Mon, 17 Dec 2018 08:56:00 +0000 (09:56 +0100)]
etnaviv: Consolidate buffer references from framebuffers

We were leaking surfaces because the references taken in
etna_set_framebuffer_state weren't being released on context destroy.

Instead of just directly releasing those references in
etna_context_destroy, use the util_copy_framebuffer_state helper.

Take the chance to remove the duplicated buffer references in
compiled_framebuffer_state to avoid confusion.

The leak can be reproduced with a client that continuously creates and
destroys contexts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reported-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
3 years agovirgl/vtest: fix front buffer flush with protocol version 0.
Dave Airlie [Thu, 27 Dec 2018 06:09:19 +0000 (16:09 +1000)]
virgl/vtest: fix front buffer flush with protocol version 0.

Older versions of virglrenderer before 33da7361aec486290df0aec4ad8dfa8ff6adde2c
in vtest mode, misrender gears.

Fixes: 9d81cd8e7c (virgl: Pass resource size and transfer offsets)
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
3 years agodocs/autoconf: Mark autoconf as being replaced
Dylan Baker [Thu, 20 Dec 2018 19:49:11 +0000 (11:49 -0800)]
docs/autoconf: Mark autoconf as being replaced

I know it's not what anyone wants, but how about we start with a
message in the documentation that encourages people to try meson.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engeström <eric@engestrom.ch>
3 years agodocs/install: Update python dependency section
Dylan Baker [Thu, 20 Dec 2018 21:43:29 +0000 (13:43 -0800)]
docs/install: Update python dependency section

Note that meson requires python 3, scons requires python 2, and
autotools works with either.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engeström <eric@engestrom.ch>
3 years agodocs/meson: Update LLVM section with information about native files
Dylan Baker [Thu, 20 Dec 2018 19:46:08 +0000 (11:46 -0800)]
docs/meson: Update LLVM section with information about native files

Reviewed-by: Eric Engeström <eric@engestrom.ch>
3 years agodocs/install: Add meson to the main install page
Dylan Baker [Thu, 20 Dec 2018 19:27:52 +0000 (11:27 -0800)]
docs/install: Add meson to the main install page

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engeström <eric@engestrom.ch>
3 years agodocs: update calendar, add news item and link release notes for 18.2.8
Juan A. Suarez Romero [Thu, 27 Dec 2018 16:37:33 +0000 (17:37 +0100)]
docs: update calendar, add news item and link release notes for 18.2.8

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
3 years agodocs: add sha256 checksums for 18.2.8
Juan A. Suarez Romero [Thu, 27 Dec 2018 16:34:35 +0000 (17:34 +0100)]
docs: add sha256 checksums for 18.2.8

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 24c31bc0e237148b1c44811b17c61fc71f09bd93)

3 years agodocs: add release notes for 18.2.8
Juan A. Suarez Romero [Thu, 27 Dec 2018 15:57:51 +0000 (15:57 +0000)]
docs: add release notes for 18.2.8

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 785e09e3b32980380eb2081eeb48c157306f99ba)

3 years agonv50,nvc0: add missing CAPs for unsupported features
Ilia Mirkin [Thu, 27 Dec 2018 01:27:29 +0000 (20:27 -0500)]
nv50,nvc0: add missing CAPs for unsupported features

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonvc0: enable GL_NV_shader_atomic_float on pre-Maxwell
Ilia Mirkin [Thu, 27 Dec 2018 01:01:28 +0000 (20:01 -0500)]
nvc0: enable GL_NV_shader_atomic_float on pre-Maxwell

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv50/ir: add support for converting ATOMFADD to proper ir
Ilia Mirkin [Thu, 19 Apr 2018 01:36:52 +0000 (21:36 -0400)]
nv50/ir: add support for converting ATOMFADD to proper ir

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agost/mesa: expose GL_NV_shader_atomic_float when ATOMFADD is supported
Ilia Mirkin [Wed, 5 Dec 2018 05:22:40 +0000 (00:22 -0500)]
st/mesa: expose GL_NV_shader_atomic_float when ATOMFADD is supported

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agost/mesa: select ATOMFADD when source type is float
Ilia Mirkin [Thu, 19 Apr 2018 01:16:52 +0000 (21:16 -0400)]
st/mesa: select ATOMFADD when source type is float

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agogallium: add PIPE_CAP_TGSI_ATOMFADD to indicate support
Ilia Mirkin [Wed, 5 Dec 2018 05:21:34 +0000 (00:21 -0500)]
gallium: add PIPE_CAP_TGSI_ATOMFADD to indicate support

ATOMFADD is a little special -- make drivers have to specify it
explicitly.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agotgsi: add ATOMFADD operation
Ilia Mirkin [Thu, 19 Apr 2018 01:13:22 +0000 (21:13 -0400)]
tgsi: add ATOMFADD operation

This is supported by at least NVIDIA hardware, and exposeable via GL
extensions.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agost/mesa: allow glDrawElements to work with GL_SELECT feedback
Ilia Mirkin [Wed, 19 Dec 2018 03:47:05 +0000 (22:47 -0500)]
st/mesa: allow glDrawElements to work with GL_SELECT feedback

Not sure if this ever worked, but the current logic for setting the
min/max index is definitely wrong for indexed draws. While we're at it,
bring in all the usual logic from the non-indirect drawing path.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109086
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
3 years agogallium/ttn: Fix setup of outputs_written.
Eric Anholt [Thu, 20 Dec 2018 16:12:50 +0000 (08:12 -0800)]
gallium/ttn: Fix setup of outputs_written.

We need a 64-bit value, otherwise we only handle the low 32, and happen to
sign-extend to claim to write all varying slots if VARYING_SLOT_VAR2 was
used.

Fixes: 4d0b2c7aaac3 ("ttn: Update shader->info as we generate code.")
Reviewed-by: Rob Clark <robdclark@gmail.com>
3 years agoanv: don't do partial resolve on layer > 0
Lionel Landwerlin [Mon, 3 Dec 2018 18:40:10 +0000 (18:40 +0000)]
anv: don't do partial resolve on layer > 0

We've made the choice not to use fast clears on layer > 0 with
multilayer images. This is partly because we would need to store
multiple clear colors for each layer, making the existing memory
layout, already including aux surfaces, fast clear color, image state,
etc... even more complex.

Partial resolves are the operations transfering the clear colors into
the auxiliary buffers. This operation is currently implemented in
Blorp by loading the clear color from the image's BO, into a shader
that then samples from the auxiliary buffer and writes the color only
if it isn't there already.

The problem here is that because we store only one clear color for all
layers and it is used for partial resolves. If you trigger a partial
clear on a layer > 0, then you're likely to deal with a color that is
not what you actually want. In the particular issues below, we have
multiple layers, each cleared with a different color but the partial
resolve just writes the wrong color into the auxiliary buffers for
layers > 0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108910
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
3 years agost/nine: Increase the limit of cached ff shaders
Axel Davy [Sat, 8 Dec 2018 19:42:23 +0000 (20:42 +0100)]
st/nine: Increase the limit of cached ff shaders

100 is too small for some games, which triggers recompilations
every frame. Increase to 1024.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agost/nine: Add src reference to nine_context_range_upload
Axel Davy [Mon, 3 Dec 2018 20:24:54 +0000 (21:24 +0100)]
st/nine: Add src reference to nine_context_range_upload

Just like nine_context_box_upload, nine_context_range_upload
should reference the src, which holds the ram source buffer.

Fixes: https://github.com/iXit/Mesa-3D/issues/327
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
3 years agost/nine: Bind src not dst in nine_context_box_upload
Axel Davy [Mon, 3 Dec 2018 20:15:47 +0000 (21:15 +0100)]
st/nine: Bind src not dst in nine_context_box_upload

nine_context_box_upload uploads a ram buffer (from src)
to a pipe_resource (dst).
We already have a refcount on the pipe_resource,
what needs to be protected from release is the ram buffer,
thus a reference to src.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
3 years agost/nine: Fix volumetexture dtor on ctor failure
Axel Davy [Sun, 25 Nov 2018 13:37:53 +0000 (14:37 +0100)]
st/nine: Fix volumetexture dtor on ctor failure

The dtor is called on allocation failure,
thus we must check the volumes are allocated
before trying to release them.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
3 years agost/nine: Switch to presentation buffer if resize is detected
Axel Davy [Sun, 16 Sep 2018 16:06:56 +0000 (18:06 +0200)]
st/nine: Switch to presentation buffer if resize is detected

This enables to match the window size
on resize on all cases, as it only works
currently with presentation buffers.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agost/nine: Use helper to release swapchain buffers later
Axel Davy [Wed, 21 Nov 2018 21:03:07 +0000 (22:03 +0100)]
st/nine: Use helper to release swapchain buffers later

This patch introduces a structure to release the
present_handles only when they are fully released
by the server, thus making
"DestroyD3DWindowBuffer" actually release the buffer
right away when called.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agofreedreno/a6xx: fix 3d texture layout
Rob Clark [Tue, 18 Dec 2018 15:34:23 +0000 (10:34 -0500)]
freedreno/a6xx: fix 3d texture layout

Maybe not 100% perfect, but seems to be a pretty good approximation of
that.

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: update generated headers
Rob Clark [Fri, 21 Dec 2018 18:22:37 +0000 (13:22 -0500)]
freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno/a6xx: improve setup_slices() debug msgs
Rob Clark [Tue, 18 Dec 2018 15:33:19 +0000 (10:33 -0500)]
freedreno/a6xx: improve setup_slices() debug msgs

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno/a6xx: simplify special case for 3d layout
Rob Clark [Tue, 18 Dec 2018 15:28:57 +0000 (10:28 -0500)]
freedreno/a6xx: simplify special case for 3d layout

This logic can be re-written as the two cases for 3d (ie. before/after
the miplevel sizes start reducing) vs everything else.  I think it is
easier to read this way.

Signed-off-by: Rob Clark <robdclark@gmail.com>