mesa.git
20 months agopost_version.py: fix branch name construction for release candidates
Eric Engestrom [Wed, 6 May 2020 22:16:24 +0000 (00:16 +0200)]
post_version.py: fix branch name construction for release candidates

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2870
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4929>

20 months agoglthread: stop using GLenum16 to get correct GL errors for out-of-bounds enums
Marek Olšák [Tue, 12 May 2020 20:22:29 +0000 (16:22 -0400)]
glthread: stop using GLenum16 to get correct GL errors for out-of-bounds enums

Reported by Ian Romanick.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5016>

20 months agoradeonsi: also enable tgsi_to_nir caching for compute shaders
Marek Olšák [Wed, 13 May 2020 17:33:00 +0000 (13:33 -0400)]
radeonsi: also enable tgsi_to_nir caching for compute shaders

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>

20 months agoradeonsi: Enable tgsi to nir disk cache
Axel Davy [Wed, 13 May 2020 16:48:48 +0000 (18:48 +0200)]
radeonsi: Enable tgsi to nir disk cache

Enable the tgsi to nir cache for radeonsi.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>

20 months agost/nine: Enable ttn cache
Axel Davy [Tue, 12 May 2020 20:26:46 +0000 (22:26 +0200)]
st/nine: Enable ttn cache

A trace of a Hat in Time, which builds thousands of shaders
takes 339 seconds to run the second time without this patch,
and 41 seconds with it (basically there is no more loading times).

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>

20 months agottn: Implement disk cache
Axel Davy [Tue, 12 May 2020 20:24:32 +0000 (22:24 +0200)]
ttn: Implement disk cache

ttn is slow, let's disk cache it.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>

20 months agottn: Add new allow_disk_cache parameter
Axel Davy [Tue, 12 May 2020 19:52:40 +0000 (21:52 +0200)]
ttn: Add new allow_disk_cache parameter

For now this parameter doesn't do anything.
It means the implementation is allowed to use
a cache on disk.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>

20 months agofreedreno/a6xx: Fix UBWC mipmapping height alignment.
Eric Anholt [Wed, 6 May 2020 21:50:34 +0000 (14:50 -0700)]
freedreno/a6xx: Fix UBWC mipmapping height alignment.

After fixing the power of two sizing, pitches worked, but 1-pixel high and
unaligned height miplevels were off.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agofreedreno/a6xx: Fix UBWC mipmap sizing.
Eric Anholt [Wed, 6 May 2020 19:21:01 +0000 (12:21 -0700)]
freedreno/a6xx: Fix UBWC mipmap sizing.

The HW requires a log2 width/height of the level 0 meta_* size in the
descriptors, making it pretty clear that UBWC mipmapping is all
power-of-two sized.  Fixes a bunch of failures in the upcoming unit UBWC
layout unit tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agofreedreno/a6xx: Fix UBWC blockheight for RG8.
Eric Anholt [Wed, 6 May 2020 22:38:46 +0000 (15:38 -0700)]
freedreno/a6xx: Fix UBWC blockheight for RG8.

Using texturator on a P3A at 1024x1024, RG8 has log2w/h of 6x7 instead of
R16I/UI's 6x8.  The other blockw/h I verified other than cpp=1
(R8/R8I/R8UI didn't use UBWC) and 32 (would need a bigger type).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agofreedreno: Pull the tile_alignment lookup for a layout to a helper.
Eric Anholt [Tue, 12 May 2020 20:49:37 +0000 (13:49 -0700)]
freedreno: Pull the tile_alignment lookup for a layout to a helper.

The r8g8 case UBWC alignment will be changing in the next commit, so
fdl6_get_ubwc_blockwidth needs to start paying attention to r8g8 too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agofreedreno/a6xx: Add a testcase for UBWC buffer sharing.
Eric Anholt [Thu, 7 May 2020 01:01:36 +0000 (18:01 -0700)]
freedreno/a6xx: Add a testcase for UBWC buffer sharing.

These offsets are hand-computed referencing msm_media_info.h, and match
our driver's current behavior.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agofreedreno/a6xx: Improve layout testcase logging for UBWC fails.
Eric Anholt [Wed, 6 May 2020 18:40:51 +0000 (11:40 -0700)]
freedreno/a6xx: Improve layout testcase logging for UBWC fails.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agofreedreno/a4xx+: Increase max texture size to 16384.
Eric Anholt [Wed, 6 May 2020 21:43:02 +0000 (14:43 -0700)]
freedreno/a4xx+: Increase max texture size to 16384.

Noticed when poking around with texture layouts and found that my big
texture layout from the blob buffer overflowed.  Values come from
http://vulkan.gpuinfo.org for Adreno 418, 512, 630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

20 months agonir: reset ssa-defs as non-divergent during divergence analysis instead of upfront
Daniel Schürmann [Tue, 21 Apr 2020 16:07:56 +0000 (17:07 +0100)]
nir: reset ssa-defs as non-divergent during divergence analysis instead of upfront

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4062>

20 months agonir: simplify phi handling in divergence analysis
Daniel Schürmann [Wed, 5 Feb 2020 17:36:34 +0000 (18:36 +0100)]
nir: simplify phi handling in divergence analysis

This patch adds some control flow information to the
state to keep track whether a loop contains divergent
continue or break statements to not having to
recalculate this property for every phi.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4062>

20 months agonir: rework phi handling in divergence analysis
Daniel Schürmann [Wed, 5 Feb 2020 12:08:27 +0000 (13:08 +0100)]
nir: rework phi handling in divergence analysis

This patch splits the visit_phi() function into
three different ones according to the kind of phi
(merge-node, loop-header or loop-exit) and calls
them when visiting the cf_nodes.
This allows to revisit loops if the loop header's
phis have changed, only.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4062>

20 months agonir: refactor divergence analysis state
Daniel Schürmann [Wed, 5 Feb 2020 10:53:04 +0000 (11:53 +0100)]
nir: refactor divergence analysis state

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4062>

20 months agonir: add nir_intrinsic_elect to divergence analysis
Daniel Schürmann [Thu, 6 Feb 2020 16:35:25 +0000 (17:35 +0100)]
nir: add nir_intrinsic_elect to divergence analysis

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4062>

20 months agonir: Make "divergent" a property of an SSA value
Jason Ekstrand [Tue, 15 Oct 2019 19:48:10 +0000 (14:48 -0500)]
nir: Make "divergent" a property of an SSA value

v2: fix usage in ACO (by Daniel Schürmann)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4062>

20 months agogallium: remove more "state tracker" occurences
Marek Olšák [Tue, 12 May 2020 20:19:10 +0000 (16:19 -0400)]
gallium: remove more "state tracker" occurences

Trivial.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4902>

20 months agogallium: rename PIPE_RESOURCE_FLAG_ST_PRIV to FRONTEND_PRIV
Marek Olšák [Wed, 4 Dec 2019 02:22:43 +0000 (21:22 -0500)]
gallium: rename PIPE_RESOURCE_FLAG_ST_PRIV to FRONTEND_PRIV

Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4902>

20 months agogallium: change comments to remove 'state tracker'
Marek Olšák [Wed, 4 Dec 2019 01:38:14 +0000 (20:38 -0500)]
gallium: change comments to remove 'state tracker'

Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4902>

20 months agogallium: rename 'state tracker' to 'frontend'
Marek Olšák [Tue, 3 Dec 2019 23:01:31 +0000 (18:01 -0500)]
gallium: rename 'state tracker' to 'frontend'

Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4902>

20 months agotu: Implement fallback linear staging blit for CopyImage
Connor Abbott [Tue, 12 May 2020 10:47:03 +0000 (12:47 +0200)]
tu: Implement fallback linear staging blit for CopyImage

Also, rewrite the format decision code so that we correctly decide when
the linear fallback is needed, even if UBWC is disabled. As part of
that, I also moved around some of the code to handle compressed formats
to make sure that copying compressed formats with a linear staging blit
works (this is now possible since we started allowing tiled compressed
textures).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5007>

20 months agotu: Add noubwc debug flag to disable UBWC
Connor Abbott [Tue, 12 May 2020 15:45:26 +0000 (17:45 +0200)]
tu: Add noubwc debug flag to disable UBWC

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5007>

20 months agotu: Add a "scratch bo" allocation mechanism
Connor Abbott [Mon, 11 May 2020 16:46:04 +0000 (18:46 +0200)]
tu: Add a "scratch bo" allocation mechanism

This is simpler than a full-blown memory reuse mechanism, but is good
enough to make sure that repeatedly doing a copy that requires the
linear staging buffer workaround won't use excessive memory or be slowed
down due to repeated allocations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5007>

20 months agoaco: improve phi affinities with p_split_vector
Rhys Perry [Fri, 8 May 2020 18:01:09 +0000 (19:01 +0100)]
aco: improve phi affinities with p_split_vector

Totals from 5860 (4.59% of 127638) affected shaders:
VGPRs: 460212 -> 460216 (+0.00%)
CodeSize: 65554356 -> 65464816 (-0.14%)
Instrs: 12655972 -> 12633578 (-0.18%)
Copies: 1309994 -> 1292163 (-1.36%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4990>

20 months agoaco: consider affinities when creating v_mac_f32
Rhys Perry [Fri, 8 May 2020 16:58:07 +0000 (17:58 +0100)]
aco: consider affinities when creating v_mac_f32

Totals from 8487 (6.65% of 127638) affected shaders:
CodeSize: 62061988 -> 62058020 (-0.01%); split: -0.01%, +0.01%
Instrs: 11910757 -> 11885409 (-0.21%); split: -0.21%, +0.00%
Copies: 1065244 -> 1040945 (-2.28%); split: -2.30%, +0.02%
Branches: 349665 -> 348914 (-0.21%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4990>

20 months agoaco: mark phi definitions as last-seen phi operands
Rhys Perry [Fri, 8 May 2020 10:45:57 +0000 (11:45 +0100)]
aco: mark phi definitions as last-seen phi operands

Totals from 14340 (11.23% of 127638) affected shaders:
SGPRs: 1251648 -> 1251512 (-0.01%)
VGPRs: 994556 -> 994104 (-0.05%); split: -0.06%, +0.01%
CodeSize: 122894528 -> 121099604 (-1.46%); split: -1.49%, +0.03%
MaxWaves: 106039 -> 106103 (+0.06%); split: +0.06%, -0.00%
Instrs: 23860066 -> 23414317 (-1.87%); split: -1.90%, +0.03%
Copies: 2448228 -> 2049305 (-16.29%); split: -16.37%, +0.07%
Branches: 789381 -> 757921 (-3.99%); split: -4.62%, +0.64%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4990>

20 months agoaco: fix consecutively written vgprs from vmem instructions
Rhys Perry [Thu, 7 May 2020 13:27:42 +0000 (14:27 +0100)]
aco: fix consecutively written vgprs from vmem instructions

If one VMEM instruction uses a sampler and the other doesn't, we can't do
this optimization.

Totals from 47 (0.04% of 127638) affected shaders:
CodeSize: 271744 -> 271656 (-0.03%); split: -0.04%, +0.01%
Instrs: 52783 -> 52761 (-0.04%); split: -0.05%, +0.01%
Cycles: 5547040 -> 5546952 (-0.00%); split: -0.00%, +0.00%
VMEM: 10022 -> 9887 (-1.35%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4949>

20 months agoaco: simplify consecutive ordered vmem/lds writes optimization
Rhys Perry [Thu, 7 May 2020 14:02:20 +0000 (15:02 +0100)]
aco: simplify consecutive ordered vmem/lds writes optimization

This was unnecessary and messed with statistics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4949>

20 months agogitlab-ci: correct tracie behavior with replay errors
Andres Gomez [Thu, 30 Apr 2020 21:05:07 +0000 (00:05 +0300)]
gitlab-ci: correct tracie behavior with replay errors

[dump_trace_images] Info: Dumping trace /tmp/tracie.test.ap5pshYcsg/traces-db/trace1/magenta.testtrace... ERROR
[dump_trace_images] Debug: === Failure log start ===
invalid literal for int() with base 16: 'in'
[dump_trace_images] Debug: === Failure log end ===
[check_image] Trace /tmp/tracie.test.ap5pshYcsg/traces-db/trace1/magenta.testtrace couldn't be replayed. See above logs for more information.
Traceback (most recent call last):
  File "/tmp/tracie.test.ap5pshYcsg/tracie.py", line 176, in <module>
    main()
  File "/tmp/tracie.test.ap5pshYcsg/tracie.py", line 164, in main
    ok, result = gitlab_check_trace(project_url, commit_id, args.device_name, trace, expectation)
TypeError: cannot unpack non-iterable bool object

Fixes: efbbf8bb81e ("tracie: Print results in a machine readable format")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4839>

20 months agogitlab-ci: create always the "results" directory with tracie
Andres Gomez [Thu, 30 Apr 2020 19:49:58 +0000 (22:49 +0300)]
gitlab-ci: create always the "results" directory with tracie

Otherwise, we will fail when the traces description file doesn't
contain any checksum for the specified device.

Fixes: efbbf8bb81e ("tracie: Print results in a machine readable format")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4839>

20 months agoradv: add a LLVM version string workaround for SotTR and ACO
Samuel Pitoiset [Mon, 11 May 2020 07:54:11 +0000 (09:54 +0200)]
radv: add a LLVM version string workaround for SotTR and ACO

When the LLVM version is too old or missing, SotTR applies shader
workarounds and that reduces performance by 2-5% with ACO.

SotTR workarounds are applied with LLVM 8 and older, so reporting
LLVM 9.0.1 should be fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4984>

20 months agoturnip: use the common code for generating extensions and dispatch tables
Samuel Pitoiset [Tue, 12 May 2020 14:17:31 +0000 (16:17 +0200)]
turnip: use the common code for generating extensions and dispatch tables

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4987>

20 months agoanv: use the common code for generating extensions and dispatch tables
Samuel Pitoiset [Mon, 11 May 2020 13:08:16 +0000 (15:08 +0200)]
anv: use the common code for generating extensions and dispatch tables

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4987>

20 months agoradv: use the common code for generating extensions and dispatch tables
Samuel Pitoiset [Mon, 11 May 2020 09:33:00 +0000 (11:33 +0200)]
radv: use the common code for generating extensions and dispatch tables

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4987>

20 months agovulkan: import common code for generating extensions
Samuel Pitoiset [Mon, 11 May 2020 12:36:02 +0000 (14:36 +0200)]
vulkan: import common code for generating extensions

ANV and RADV have similar Python code for generating extensions
and dispatch tables.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4987>

20 months agoradv: implement VK_EXT_private_data
Samuel Pitoiset [Wed, 29 Apr 2020 08:19:11 +0000 (10:19 +0200)]
radv: implement VK_EXT_private_data

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4886>

20 months agoradv: use the base object struct types
Samuel Pitoiset [Wed, 29 Apr 2020 12:57:20 +0000 (14:57 +0200)]
radv: use the base object struct types

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4886>

20 months agoradv: use the common base object type for VkDevice
Samuel Pitoiset [Wed, 29 Apr 2020 08:16:32 +0000 (10:16 +0200)]
radv: use the common base object type for VkDevice

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4886>

20 months agoetnaviv: Disable seamless cube map on GC880
Marek Vasut [Sat, 2 May 2020 20:24:25 +0000 (22:24 +0200)]
etnaviv: Disable seamless cube map on GC880

The GC880 on iMX6DL indicates in it's minorFeatures2 register that it
does support SEAMLESS_CUBE_MAP, however when the TE.SAMPLER_CONFIG1
VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP bit is set on GC880 on iMX6DL,
the result is corrupted image. In particular, the following ~112 dEQPs
are affected and fail:

  dEQP-GLES2.functional.texture.filtering.cube.*

This only happens on MX6DL GC880, MX6Q GC2000 and STM32MP1 GC400(GCnano)
do not report the minorFeatures2 SEAMLESS_CUBE_MAP bit and ignore the
TE_SAMPLER_CONFIG1 VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP bit (note
that ss->seamless_cube_map is unconditionally set by mesa at times even
PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE returns 0), so there is no visible
problem and there are no failing dEQP tests on the GC2000 and GCnano.

This might imply that the minorFeatures2 SEAMLESS_CUBE_MAP has some
different meaning on GC880 or the SEAMLESS_CUBE_MAP behaves differently
on the GC880.

This patch does not set the SEAMLESS_CUBE_MAP bit on hardware which does
not indicate support for seamless cube map and on GC880, which results
in reduction in failed dEQPs: 635 to 186 on GC880, 274 to 270 on GC2000
and no change on GC400(GCnano).

Fixes: 8dd26fa2f06 ("etnaviv: support GL_ARB_seamless_cubemap_per_texture")
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4865>

20 months agofreedreno/a6xx: fix max-scissor opt
Rob Clark [Tue, 12 May 2020 23:39:20 +0000 (16:39 -0700)]
freedreno/a6xx: fix max-scissor opt

On a6xx we need a 0,0 based scissor in the binning pass, but can use the
blit-scissor to avoid restore/resolve of untouched pixels, and use the
conditional execution if the IB to bin to skip bins with no geometry
(due to the scissor).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5021>

20 months agofreedreno/ir3/sched: try to avoid syncs
Rob Clark [Wed, 6 May 2020 17:29:01 +0000 (10:29 -0700)]
freedreno/ir3/sched: try to avoid syncs

Similar to what we do in postsched.  It is useful for pre-RA sched to be
a bit aware of things that would cause syncs.  In particular for the tex
fetches, since the vecN src/dst tends to limit postsched's ability to
re-order them.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4923>

20 months agofreedreno/ir3/sched: avoid scheduling outputs
Rob Clark [Wed, 6 May 2020 17:20:14 +0000 (10:20 -0700)]
freedreno/ir3/sched: avoid scheduling outputs

If an instruction's only use is as an output, and it increases register
pressure, then try to avoid scheduling it until there are no other
options.

A semi-common pattern is `fragcolN.a = 1.0`, this pushes all these
immed loads to the end of the shader.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4923>

20 months agofreedreno/ir3/postsched: try to avoid (sy) syncs
Rob Clark [Wed, 6 May 2020 17:06:17 +0000 (10:06 -0700)]
freedreno/ir3/postsched: try to avoid (sy) syncs

Similar to avoidance of `(ss)` syncs, it turns out to be helpful to
avoid `(sy)` syncs as well.  This helps us turn an tex, (sy)alu, tex,
(sy)alu sequence into tex, tex, (sy)alu, alu, which is a big win in
gfxbench gl_fill2.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4923>

20 months agofreedreno/ir3/postsched: reset sfu_delay on sync
Rob Clark [Wed, 6 May 2020 17:01:08 +0000 (10:01 -0700)]
freedreno/ir3/postsched: reset sfu_delay on sync

Once we schedule an instruction that will require an `(ss)` sync flag,
there is no need to delay any further instructions that consume an
SFU result (until the next SFU instruction is scheduled).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4923>

20 months agofreedreno/ir3: limit # of tex prefetch by shader size
Rob Clark [Mon, 4 May 2020 22:13:20 +0000 (15:13 -0700)]
freedreno/ir3: limit # of tex prefetch by shader size

It seems for short frag shaders, too much prefetch can be detrimental.
I think what we *really* want to do is decide after pre-RA sched, when
we also know about nop's and what the actual ir3 instruction count is.
But that will require re-working how prefetch lowering works.  For now
this is a super crude heuristic to attempt to approximate a good
solution.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4923>

20 months agofreedreno/ir3: fix indirect cb0 load_ubo lowering
Rob Clark [Thu, 7 May 2020 20:24:46 +0000 (13:24 -0700)]
freedreno/ir3: fix indirect cb0 load_ubo lowering

We can no longer assume that `state->ranges[0]` is block 0.  It *often*
is, but when we encounter a "real" ubo that we lower to `load_uniform`
before a block 0 `load_ubo`, it could end up another entry in the table.
Resulting in the second pass after gathering ubo ranges, not finding a
valid range.  Which results in a `load_ubo` for a thing that is not
actually a ubo making it's way into ir3 frontend.  Resulting in grabbing
what we think is a ubo address out of some unrelated const register, and
trying to dereference that.  Which as you can imagine, fails in amusing
ways.

Fixes: fc850080ee3 ("ir3: Rewrite UBO push analysis to support bindless")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4954>

20 months agofreedreno/ir3: don't allow negative const_offset
Rob Clark [Thu, 7 May 2020 18:09:17 +0000 (11:09 -0700)]
freedreno/ir3: don't allow negative const_offset

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4954>

20 months agopanfrost: Run dEQP-GLES3.functional.shaders.derivate.* on CI
Alyssa Rosenzweig [Tue, 12 May 2020 18:14:29 +0000 (14:14 -0400)]
panfrost: Run dEQP-GLES3.functional.shaders.derivate.* on CI

Should be stable now, and should pass except for MSAA tests
(multisampling is still a todo overall).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Fix derivative swizzle
Alyssa Rosenzweig [Mon, 11 May 2020 13:20:39 +0000 (09:20 -0400)]
pan/mdg: Fix derivative swizzle

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Set types for derivatives
Alyssa Rosenzweig [Wed, 6 May 2020 18:17:34 +0000 (14:17 -0400)]
pan/mdg: Set types for derivatives

Closes #2900

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Remove texture_op_count
Alyssa Rosenzweig [Tue, 12 May 2020 17:36:51 +0000 (13:36 -0400)]
pan/mdg: Remove texture_op_count

Was used as a crude approximation of the terminate flag, which we now
can do properly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Use analysis to set .cont/.last flags
Alyssa Rosenzweig [Tue, 12 May 2020 17:34:52 +0000 (13:34 -0400)]
pan/mdg: Use analysis to set .cont/.last flags

Corresponds roughly to what we analyze. Note that "terminate AND
execute" is a contradiction (rather: it's equivalent to just
terminating), hence why there are only three possibilities for the
states of the flags:

   .cont = continue, don't execute
   .last = don't continue, don't execute
   .cont.last = continue and execute

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Use the helper invo analyze passes
Alyssa Rosenzweig [Tue, 12 May 2020 17:26:32 +0000 (13:26 -0400)]
pan/mdg: Use the helper invo analyze passes

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Analyze helper execution requirements
Alyssa Rosenzweig [Tue, 12 May 2020 17:19:23 +0000 (13:19 -0400)]
pan/mdg: Analyze helper execution requirements

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Analyze helper invocation termination
Alyssa Rosenzweig [Tue, 12 May 2020 00:22:16 +0000 (20:22 -0400)]
pan/mdg: Analyze helper invocation termination

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agopan/mdg: Explain helper invocations dataflow theory
Alyssa Rosenzweig [Tue, 12 May 2020 00:05:24 +0000 (20:05 -0400)]
pan/mdg: Explain helper invocations dataflow theory

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5014>

20 months agointel/compiler: fix alignment assert in nir_emit_intrinsic
Arcady Goldmints-Orlov [Mon, 11 May 2020 23:31:49 +0000 (18:31 -0500)]
intel/compiler: fix alignment assert in nir_emit_intrinsic

Fixes: c643979228 (intel/fs: Choose memory message type based on bit size)
Fixes: dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i8vec2
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5000>

20 months agofreedreno: Skip taking the lock for resource usage if it's already flagged.
Eric Anholt [Tue, 12 May 2020 16:39:20 +0000 (09:39 -0700)]
freedreno: Skip taking the lock for resource usage if it's already flagged.

Improves nohw drawoverhead 8-ubos update throughput by 13.493% +/-
0.391444% (n=15).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5011>

20 months agofreedreno: Move the resource_read early out to an inline.
Eric Anholt [Mon, 11 May 2020 22:08:35 +0000 (15:08 -0700)]
freedreno: Move the resource_read early out to an inline.

Looking at perf, the drawoverhead test case was now spending 13% CPU (89%
in that function) on stack management.

nohw drawoverhead throughput 1.03902% +/- 0.380257% (n=13).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4996>

20 months agofreedreno: Add an early out for preparing to read a resource.
Eric Anholt [Mon, 11 May 2020 20:46:33 +0000 (13:46 -0700)]
freedreno: Add an early out for preparing to read a resource.

nohw drawoverhead 8 UBOs test throughput 1.06093% +/- 0.363376% (n=10).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4996>

20 months agofreedreno: Split the fd_batch_resource_used by read vs write.
Eric Anholt [Mon, 11 May 2020 20:28:58 +0000 (13:28 -0700)]
freedreno: Split the fd_batch_resource_used by read vs write.

This is for an optimization I plan in a following commit.  I found I had
to add likely()s to avoid a perf regression from branch prediction.

On the drawoverhead 8 UBOs test, the HW can't quite keep up with the CPU,
but if I set nohw then this change is 1.32023% +/- 0.373053% (n=10).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4996>

20 months agofreedreno: Add a nohw flag to skip submitting to the kernel.
Eric Anholt [Mon, 11 May 2020 20:53:48 +0000 (13:53 -0700)]
freedreno: Add a nohw flag to skip submitting to the kernel.

For some CPU-side-only optimizations, it can be nice to disable rendering
so that we can see what the impact is even on cases where the GPU can't
quite keep up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4996>

20 months agoturnip: Execute ir3_nir_lower_gs pass again
Brian Ho [Mon, 4 May 2020 20:55:06 +0000 (13:55 -0700)]
turnip: Execute ir3_nir_lower_gs pass again

This commit fixes a GS regression introduced in !4562 where
ir3's GS lowering pass was moved from common code (ir3_nir) to
freedreno-specific code (ir3_shader). For GS support in turnip, we
need to add the GS lowering pass back in, this time in tu_shader.

As for the nir_gather_info change, the GS lowering pass has always
introduced a discard_if intrinsic into the GS. Previously, we simply
ran nir_shader_gather_info before GS lowering, but now since we lower
the GS before we need to remove the assertion that only a FS can use
the discard_if intrinsic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4892>

20 months agofreedreno/gmem: rework gmem layout algo
Rob Clark [Fri, 8 May 2020 23:35:29 +0000 (16:35 -0700)]
freedreno/gmem: rework gmem layout algo

And try a bit harder to find an optimal layout.  Improves on a sub-
optimal layout we arrive at in the 4 MRT pass in manhattan, picking
up a bit more than 3%.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agofreedreno/gmem: relax alignment on a6xx
Rob Clark [Sat, 9 May 2020 16:42:14 +0000 (09:42 -0700)]
freedreno/gmem: relax alignment on a6xx

The blob only uses single page alignment, and empirically that appears
to work just fine.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agofreedreno: add gmemtool
Rob Clark [Sat, 9 May 2020 20:19:14 +0000 (13:19 -0700)]
freedreno: add gmemtool

A simple standalone thing to run through a bunch of GMEM layouts for a
given gpu.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agofreedreno/gmem: add helper to dump GMEM layout
Rob Clark [Sat, 9 May 2020 16:38:02 +0000 (09:38 -0700)]
freedreno/gmem: add helper to dump GMEM layout

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agofreedreno/gmem: add div_align() helper
Rob Clark [Fri, 8 May 2020 23:13:59 +0000 (16:13 -0700)]
freedreno/gmem: add div_align() helper

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agofreedreno: initialize max_scissor
Rob Clark [Sat, 9 May 2020 19:31:20 +0000 (12:31 -0700)]
freedreno: initialize max_scissor

Somehow the initialization of this got lost somewhere along the way,
resulting in assuming minx/miny are always zero.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agofreedreno/gmem: don't assume scissor opt when estimating # of bins
Rob Clark [Sat, 9 May 2020 19:29:43 +0000 (12:29 -0700)]
freedreno/gmem: don't assume scissor opt when estimating # of bins

We potentially don't know yet what the resulting scissor bounds are, so
we can't assume this when estimating number of bins per pipe for VSC
size calculations.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4976>

20 months agovulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains
Jason Ekstrand [Fri, 8 May 2020 07:06:26 +0000 (02:06 -0500)]
vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains

There is an annoying spec corner on Android.  Because VkSwapchain is
implemented in the Vulkan loader on Android which may not know about
this extension, we have to handle it as a special case inside the
driver.  We only have to do this on Android and only for VkSwapchainKHR.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4882>

20 months agoanv,vulkan: Implement VK_EXT_private_data
Jason Ekstrand [Tue, 21 Apr 2020 21:31:25 +0000 (16:31 -0500)]
anv,vulkan: Implement VK_EXT_private_data

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4882>

20 months agoturnip: enable tiling for compressed formats
Jonathan Marek [Tue, 12 May 2020 15:28:51 +0000 (11:28 -0400)]
turnip: enable tiling for compressed formats

Now that layout code supports this, we can enable it.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5009>

20 months agoturnip: update "fetchsize" value to match fdl6_layout changes
Jonathan Marek [Tue, 12 May 2020 15:26:05 +0000 (11:26 -0400)]
turnip: update "fetchsize" value to match fdl6_layout changes

It seems this is actually a "minimum pitch" value. For example
TFETCH6_2_BYTE means a minimum pitch of 128 bytes for mipmap levels.

This fixes breakage with compressed formats. For example this test:

dEQP-VK.pipeline.sampler.view_type.2d.format.eac_r11_snorm_block.mipmap.linear.lod.equal_min_3_max_3

Fixes: a34b3fa198a4f ("freedreno/fdl: Align after dividing by block size")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5009>

20 months agofreedreno: Fix non-constbuf-upload UBO block indices and count.
Eric Anholt [Mon, 11 May 2020 18:18:02 +0000 (11:18 -0700)]
freedreno: Fix non-constbuf-upload UBO block indices and count.

The nir_analyze_ubo_ranges pass removes all UBO block 0 loads to reverse
what nir_lower_uniforms_to_ubo() had done, and we only upload UBO pointers
to the HW for UBO block 1-N, so let's just fix up the shader state.

Fixes an off by one in const state layout setup, and some really dodgy
register addressing trying to deal with dynamic UBO indices when the UBO
pointers happen to be at the start of the constbuf.

There's no fixes tag, though this fixes a bug from September, because it
would require the num_ubos fix in nir_lower_uniforms_to_ubo.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4992>

20 months agonir: Fix count when we didn't lower load_uniforms but did shift load_ubos.
Eric Anholt [Mon, 11 May 2020 18:53:22 +0000 (11:53 -0700)]
nir: Fix count when we didn't lower load_uniforms but did shift load_ubos.

The fixed commit was really nice in mostly fixing num_ubos to reflect the
shader after lowering, but for
dEQP-GLES31.functional.compute.basic.ubo_to_ssbo_single_invocation there
are no default uniforms and so we skipped the increment, even though we
shifted the block index up.

Fixes: 4777ee1a62f0 ("nir: Always create UBO variable when lowering uniforms to ubo")
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4992>

20 months agofreedreno: Drop the "write" arg to emit_const_bo now relocs don't care.
Eric Anholt [Mon, 11 May 2020 16:46:03 +0000 (09:46 -0700)]
freedreno: Drop the "write" arg to emit_const_bo now relocs don't care.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>

20 months agofreedreno: Replace OUT_RELOCW with OUT_RELOC.
Eric Anholt [Fri, 8 May 2020 19:39:36 +0000 (12:39 -0700)]
freedreno: Replace OUT_RELOCW with OUT_RELOC.

Final cleanup commit now that they're the same.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>

20 months agofreedreno: Tell the kernel that all BOs are for writing.
Eric Anholt [Fri, 8 May 2020 19:28:08 +0000 (12:28 -0700)]
freedreno: Tell the kernel that all BOs are for writing.

Using non-write flags is pretty dubious -- it means the kernel tracking an
array of read-only consumers of the BO and having exclusive consumers wait
on each reader's fence.  It allows multiple readers through dma-bufs to do
work in parallel, but at the cost of kernel CPU time and memory management
of the shared array.  Other drivers have dropped this distinction since
dma-buf sharing is usually producer-consumer, not producer-two-consumers,
and the userspace and kernel space tracking is expensive.

For us, this lets us drop the flags passed in for relocs and tracked in
the ringbuffer reloc lists.  The end result of the flags reduction work is
drawoverhead uniforms test throughput 2.37195% +/- 0.365579% (n=15)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>

20 months agofreedreno: Mark all ringbuffer BOs as to be dumped on crash.
Eric Anholt [Fri, 8 May 2020 18:28:14 +0000 (11:28 -0700)]
freedreno: Mark all ringbuffer BOs as to be dumped on crash.

We can avoid passing these flags around in the DRM backends by just
marking ring BOs up front.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>

20 months agofreedreno: Replace OUT_RELOCD with permanently flagging shader BOs for it.
Eric Anholt [Fri, 8 May 2020 18:24:12 +0000 (11:24 -0700)]
freedreno: Replace OUT_RELOCD with permanently flagging shader BOs for it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>

20 months agofreedreno: Start moving relocs flags into the BOs.
Eric Anholt [Fri, 8 May 2020 18:20:07 +0000 (11:20 -0700)]
freedreno: Start moving relocs flags into the BOs.

It's silly to have all the reloc emitters passing around FD_RELOC_READ
when you have to have it set on all relocs (that don't include WRITE,
which implies read) for the kernel to actually track the fences on the BO.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>

20 months agoaco: optimize add/sub(a, cndmask(b, 0, 1, cond)) -> addc/subbrev_co(0, a, b)
Samuel Pitoiset [Thu, 2 Apr 2020 15:41:36 +0000 (17:41 +0200)]
aco: optimize add/sub(a, cndmask(b, 0, 1, cond)) -> addc/subbrev_co(0, a, b)

v2: outline into a separate function and also optimize additions (by Daniel Schürmann)

Totals from affected shaders: (VEGA)
SGPRS: 938888 -> 941496 (0.28 %)
VGPRS: 832068 -> 831532 (-0.06 %)
Spilled SGPRs: 618 -> 618 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 3696 -> 3696 (0.00 %) dwords per thread
Code Size: 72893900 -> 72558928 (-0.46 %) bytes
LDS: 18201 -> 18201 (0.00 %) blocks
Max Waves: 64256 -> 64268 (0.02 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4419>

20 months agoaco: coalesce parallelcopies during register allocation
Daniel Schürmann [Thu, 7 May 2020 17:19:54 +0000 (18:19 +0100)]
aco: coalesce parallelcopies during register allocation

These are the result of lowering to CSSA, and should be removed if possible

Totals from affected shaders: (VEGA)
SGPRS: 544544 -> 544544 (0.00 %)
VGPRS: 418224 -> 418224 (0.00 %)
Spilled SGPRs: 141826 -> 141826 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 65853740 -> 64703380 (-1.75 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 13669 -> 13669 (0.00 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4952>

20 months agoglthread: Fix use of alloca() without #include "c99_alloca.h"
Jon Turney [Wed, 6 May 2020 15:09:56 +0000 (16:09 +0100)]
glthread: Fix use of alloca() without #include "c99_alloca.h"

../src/mesa/main/glthread_draw.c: In function ‘_mesa_marshal_MultiDrawElementsBaseVertex’:
../src/mesa/main/glthread_draw.c:812:36: error: implicit declaration of function ‘alloca’; did you mean ‘malloc’? [-Werror=implicit-function-declaration]
  812 |       const GLvoid **out_indices = alloca(sizeof(indices[0]) * draw_count);
      |                                    ^~~~~~
      |                                    malloc
../src/mesa/main/glthread_draw.c:812:36: error: initialization of ‘const GLvoid **’ {aka ‘const void **’} from ‘int’ makes pointer from integer without a cast [-Werror=int-conversion]
cc1: some warnings being treated as errors

Include c99_alloca.h to portably make the alloca() prototype available.

Fixes: 2840bc30
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4920>

20 months agoetnaviv: generalize FE stall before loading shader and sampler states
Lucas Stach [Thu, 6 Feb 2020 16:11:03 +0000 (17:11 +0100)]
etnaviv: generalize FE stall before loading shader and sampler states

It seems that some of the new shader and sampler states added with
Halti0 are not self-synchronizing anymore. Make sure to stall the FE
before loading those new states to avoid corruption of the in-flight
draw state.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3963>

20 months agoCI: Re-enable Panfrost T7x0 jobs
Daniel Stone [Tue, 12 May 2020 10:33:06 +0000 (11:33 +0100)]
CI: Re-enable Panfrost T7x0 jobs

The hardware issue in the lab preventing jobs from being run on those
machines (and limiting T820 availability), leading to them being
disabled in !4965, has been fixed.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: 696bafac40f5 ("CI: Disable Panfrost T7x0 jobs")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5006>

20 months agoradv: update the list of allowed Android extensions
Samuel Pitoiset [Mon, 11 May 2020 10:04:51 +0000 (12:04 +0200)]
radv: update the list of allowed Android extensions

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4985>

20 months agoradv: handle different Vulkan API versions correctly
Samuel Pitoiset [Mon, 11 May 2020 09:58:26 +0000 (11:58 +0200)]
radv: handle different Vulkan API versions correctly

Loosely based on ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4985>

20 months agoradv: limit the Vulkan version to 1.1 for Android
Samuel Pitoiset [Mon, 11 May 2020 08:52:18 +0000 (10:52 +0200)]
radv: limit the Vulkan version to 1.1 for Android

Vulkan 1.2 seems rejected. This hardcodes the Android version to
1.1.107.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2936
Fixes: 7f5462e349a ("radv: enable Vulkan 1.2")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4985>

20 months agor600: Fix nir compiler options, i.e. don't lower IO to temps for TESS
Gert Wollny [Mon, 11 May 2020 07:03:41 +0000 (09:03 +0200)]
r600: Fix nir compiler options, i.e. don't lower IO to temps for TESS

Also fix alignments and add umad24 and umul24 options.

Fixes: 6747a984f59ea9a2dd74b98d59cb8fdb028969ae
    r600: Enable tesselation for NIR

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4982>

20 months agov3d/tex: use TMUSLOD register if possible
Alejandro Piñeiro [Thu, 7 May 2020 09:46:25 +0000 (11:46 +0200)]
v3d/tex: use TMUSLOD register if possible

TMUSLOD register is the same that TMUS but having the same effect that
setting disable_autolod on the TMU configuration parameter 2.

So using that register is potentially more efficient, as in several
cases we would be able to skip writing P2.

One case where we can't use it is for texture cube maps, as we need to
use TMUSCM.

v2: don't put a comment in the middle of the conditions (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4962>

20 months agov3d/tex: set up default values for Configuration Parameter 1 if possible
Alejandro Piñeiro [Wed, 29 Apr 2020 08:29:50 +0000 (10:29 +0200)]
v3d/tex: set up default values for Configuration Parameter 1 if possible

Texture access has three configuration parameters, P0 (texture), P1
(sampler) and P2(lookup). P1 and P2 are optional, but if P2 is needed
(like for example to set the offset for texelFetchOffset), then you
need to set P1.

But until now when setting up P1 we were asking the driver to fill up
the address with the shader state. But in that case we can just fill
that address with the default value NULL.

So let's avoid asking the driver to fill that default values, and do
it directly on the compiler. This is a good-to-have on OpenGL, and
likely would be needed on Vulkan.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4962>

20 months agov3d/tex: only look up the 2nd texture gather offset for 1d non-arrays
Alejandro Piñeiro [Tue, 28 Apr 2020 22:33:47 +0000 (00:33 +0200)]
v3d/tex: only look up the 2nd texture gather offset for 1d non-arrays

Commit 1bc71e8b655f2f02b3e3a0af34c7cad12b9cb83d already did that for
the 3rd offset, but it also needs to do it for the 2nd (to handle 1d
array).

Fixes assertion failures with Vulkan CTS tests using 1darray
targets. Seems that there isn't too many 1darray tests on OpenGL CTS,
and OpenGL-ES don't support 1d arrays, but the same problem could
arise eventually on OpenGL.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4962>

20 months agodrirc: Enable glthread for rpcs3
Ani [Mon, 11 May 2020 14:45:47 +0000 (14:45 +0000)]
drirc: Enable glthread for rpcs3

Closes: #2939
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4988>

20 months agopan/midgard: Fix old style shadows
Icecream95 [Mon, 11 May 2020 22:16:31 +0000 (10:16 +1200)]
pan/midgard: Fix old style shadows

This fixes the sky being red in OpenMW, as well as some of the Mesa
demos using shadows (shadowtex, shadow_sampler).

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4997>