mesa.git
5 years agoAndroid: enable building on arm64
Rob Herring [Tue, 2 Feb 2016 20:45:09 +0000 (14:45 -0600)]
Android: enable building on arm64

Use the LOCAL_CFLAGS_{32/64} instead of arch specific variants to define
the DEFAULT_DRIVER_DIR. This enables building for arm64.

Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoAndroid: Fix building secondary arch in mixed 32/64-bit builds
Rob Herring [Tue, 2 Feb 2016 20:45:08 +0000 (14:45 -0600)]
Android: Fix building secondary arch in mixed 32/64-bit builds

TARGET_CC is not defined for the secondary arch on combined 32/64-bit
builds. The build system uses 2ND_TARGET_CC instead and it is not meant
to be used in module makefiles. LOCAL_CC was used to provide C only
flags as -std=c99 is not valid for C++ files. Since Android 4.4,
LOCAL_CONLYFLAGS was added to set compiler flags on C files only, so it
can be used now instead of LOCAL_CC.

This will break on pre-4.4 versions of Android, but it unlikely anyone
is using current Mesa with such an old version of Android.

Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoegl: android: clean-up config attribute setting
Rob Herring [Tue, 2 Feb 2016 20:23:10 +0000 (14:23 -0600)]
egl: android: clean-up config attribute setting

Pass the additional config attributes to dri2_add_config to set them
instead of open coding them. This is in preparation to add more attributes.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoegl: android: fix visuals declaration
Varad Gautam [Tue, 2 Feb 2016 20:23:09 +0000 (14:23 -0600)]
egl: android: fix visuals declaration

Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoAndroid: fix build break in libmesa_program
Rob Herring [Mon, 15 Feb 2016 14:24:43 +0000 (08:24 -0600)]
Android: fix build break in libmesa_program

Commit 5fd848f6c9ee ("program: Use _mesa_geometric_samples to calculate
gl_NumSamples") broken Android builds. Add the missing include path "main"
to framebuffer.h like other includes in prog_statevars.c.

Cc: Neil Roberts <neil@linux.intel.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agomesa: gl_NumSamples should always be at least one
Ilia Mirkin [Tue, 16 Feb 2016 06:18:30 +0000 (01:18 -0500)]
mesa: gl_NumSamples should always be at least one

From ARB_sample_shading:

    "gl_NumSamples is the total number of samples in the framebuffer,
     or one if rendering to a non-multisample framebuffer"

So make sure to always pass in at least 1.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O`Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
5 years agocompiler/glsl: Fix uniform location counting.
Plamena Manolova [Thu, 11 Feb 2016 13:00:02 +0000 (15:00 +0200)]
compiler/glsl: Fix uniform location counting.

This patch moves the calculation of current uniforms to
link_uniforms, which makes use of UniformRemapTable which
stores all the reserved uniform locations.

Location assignment for implicit uniforms now tries to use
any gaps left in the table after the location assignment
for explicit uniforms. This gives us more space to store more
uniforms.

Patch is based on earlier patch with following changes/additions:

   1: Move the counting of explicit locations to
      check_explicit_uniform_locations and then pass
      the number to link_assign_uniform_locations.
   2: Count the number of empty slots in UniformRemapTable
      and store them in a list_head.
   3: Try to find an empty slot for implicit locations from
      the list, if that fails resize UniformRemapTable.

Fixes following CTS tests:
   ES31-CTS.explicit_uniform_location.uniform-loc-mix-with-implicit-max
   ES31-CTS.explicit_uniform_location.uniform-loc-mix-with-implicit-max-array

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93696

5 years agogallivm, tgsi: provide fake sample_i_ms implementations
Roland Scheidegger [Wed, 17 Feb 2016 19:42:11 +0000 (20:42 +0100)]
gallivm, tgsi: provide fake sample_i_ms implementations

Just like the rest of the msaa "implementation" it's just fake for now...

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: new st_DrawAtlasBitmaps() function for drawing bitmap text
Brian Paul [Wed, 3 Feb 2016 16:40:08 +0000 (09:40 -0700)]
st/mesa: new st_DrawAtlasBitmaps() function for drawing bitmap text

This basically saves the current pipeline state, sets up state for
rendering, constructs a set of textured quads, renders, then restores
the previous pipeline state.

It shouldn't be hard to implement a similar function for non-gallium
drives.  With some code refactoring, the vertex definition code could
probably be shared.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
5 years agomesa: implement a display list / glBitmap texture atlas
Brian Paul [Wed, 3 Feb 2016 16:35:42 +0000 (09:35 -0700)]
mesa: implement a display list / glBitmap texture atlas

This improves the performance of applications which use glXUseXFont()
or wglUseFontBitmaps() and glCallLists() to draw bitmap text.

Basically, we collect all the glBitmap images from the display lists
and put them into a texture atlas.  To render the bitmaps for a
glCallLists() command, we render a set of textured quads where each
quad is textured with one bitmap image.  Actually, the rendering part
has to be done by the Mesa driver or Mesa/gallium state tracker.

Note that GLUT demos that use glutBitmapCharacter() don't benefit
from this.

v2, per Nicolai Hähnle:
- check the max tex rect size is at least 1024.
- add comment in dd.h that texture_rectangle is required.
- in _mesa_DeleteLists(), try to delete the atlas before the list(s)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
5 years agost/mesa: apply DepthMode swizzle to stencil texturing as well
Ilia Mirkin [Tue, 16 Feb 2016 23:58:42 +0000 (18:58 -0500)]
st/mesa: apply DepthMode swizzle to stencil texturing as well

Gallium doesn't present these as GL_RED-style. A swizzle is necessary to
present the proper data in the unused components.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agoi965/skl: Update Skylake renderer strings
Ben Widawsky [Tue, 16 Feb 2016 23:08:40 +0000 (15:08 -0800)]
i965/skl: Update Skylake renderer strings

Also adds some of the Iris/Pro parts which we previously didn't have named.

v2: 0x192d is gt3, not gt4
Adding some 'e' tags for eDRAM parts

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Michał Winiarski <michal.winiarski@intel.com>
5 years agoi965/skl: Add two missing device IDs
Ben Widawsky [Tue, 16 Feb 2016 23:10:24 +0000 (15:10 -0800)]
i965/skl: Add two missing device IDs

The Iris part is left unbranded because we did not have these with original SKL.

v2: 0x192d is gt3, not gt4

v3: Forgot to update the temporary brand string when I did v2.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Michał Winiarski <michal.winiarski@intel.com>
5 years agomesa: allow multisampled format info to be returned on GLES 3.1
Ilia Mirkin [Thu, 11 Feb 2016 20:02:30 +0000 (15:02 -0500)]
mesa: allow multisampled format info to be returned on GLES 3.1

The restriction on multisampled integer texture formats only applies to
GLES 3.0, so don't apply it to GLES 3.1 contexts. This fixes a slew of

dEQP-GLES31.functional.state_query.internal_format.*

tests, which now all pass.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
5 years agoi965: Extract push constant state to a new file
Ben Widawsky [Thu, 30 Jul 2015 21:31:20 +0000 (14:31 -0700)]
i965: Extract push constant state to a new file

Every stage has a corresponding 3DSTATE_CONSTANT_XS packet, so having
the code to create and emit push constant buffers in genX_vs_state.c
is a little strange.  Moving it to a separate file seems more logical.

v2 [Ken]: Rebase on master, explain motivation in the commit message.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: Make emit_minmax return an instruction*.
Matt Turner [Thu, 11 Feb 2016 21:41:58 +0000 (13:41 -0800)]
i965: Make emit_minmax return an instruction*.

And use it in brw_fs_nir.cpp.

5 years agoi965: Lower min/max after optimization on Gen4/5.
Matt Turner [Thu, 11 Feb 2016 20:27:02 +0000 (12:27 -0800)]
i965: Lower min/max after optimization on Gen4/5.

Gen4/5's SEL instruction cannot use conditional modifiers, so min/max
are implemented as CMP + SEL. Handling that after optimization lets us
CSE more.

On Ironlake:

   total instructions in shared programs: 6426035 -> 6422753 (-0.05%)
   instructions in affected programs: 326604 -> 323322 (-1.00%)
   helped: 1411

   total cycles in shared programs: 129184700 -> 129101586 (-0.06%)
   cycles in affected programs: 18950290 -> 18867176 (-0.44%)
   helped: 2419
   HURT: 328

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
5 years agoi965/vec4: Initialize force_writemask_all in vec4_builder().
Matt Turner [Thu, 11 Feb 2016 20:23:53 +0000 (12:23 -0800)]
i965/vec4: Initialize force_writemask_all in vec4_builder().

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
5 years agoradeon/llvm: Add TargetLibraryInfo to the pass manager
Tom Stellard [Thu, 4 Feb 2016 19:37:31 +0000 (19:37 +0000)]
radeon/llvm: Add TargetLibraryInfo to the pass manager

This will prevent optimization passes from introducing unsupported
library calls.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeon/llvm: Set the target triple on the module
Tom Stellard [Thu, 4 Feb 2016 02:34:55 +0000 (02:34 +0000)]
radeon/llvm: Set the target triple on the module

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallivm: Add helpers for creating and destroying TargetLibraryInfo
Tom Stellard [Thu, 4 Feb 2016 19:36:50 +0000 (19:36 +0000)]
gallivm: Add helpers for creating and destroying TargetLibraryInfo

This functionality is not exposed via the LLVM C API.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agonvc0: invalidate all buffers when switching pipe contexts
Samuel Pitoiset [Wed, 17 Feb 2016 20:14:24 +0000 (21:14 +0100)]
nvc0: invalidate all buffers when switching pipe contexts

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agost/mesa: fix up result_src.type when doing i2u/u2i conversions
Ilia Mirkin [Tue, 16 Feb 2016 07:12:29 +0000 (02:12 -0500)]
st/mesa: fix up result_src.type when doing i2u/u2i conversions

Even though it's a no-op, it's important to keep track of the type so
that we can pick the properly-signed op later on.

This fixes dEQP-GLES3.functional.shaders.precision.uint.highp_div_fragment,
which ended up using IDIV instead of UDIV.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
5 years agost/mesa: use cso_set_viewport_dims() in try_pbo_upload_common()
Brian Paul [Tue, 16 Feb 2016 00:27:15 +0000 (17:27 -0700)]
st/mesa: use cso_set_viewport_dims() in try_pbo_upload_common()

Note that this results in a different transformation for the viewport's
Z axis (depth range), but that doesn't matter for this case.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agoi965/gen7: Use predicated rendering for indirect compute
Jordan Justen [Mon, 15 Feb 2016 23:17:15 +0000 (15:17 -0800)]
i965/gen7: Use predicated rendering for indirect compute

On gen7 (Ivy Bridge, Haswell), we will get a GPU hang if an indirect
dispatch is used, but one of the dimensions is 0.

Therefore we use predicated rendering on the GPGPU_WALKER command to
handle this case.

Fixes piglit test: spec/arb_compute_shader/zero-dispatch-size

From the ARB_compute_shader spec, under DispatchCompute:

"If the work group count in any dimension is zero, no work groups are
 dispatched."

And then for DispatchComputeIndirect:

... "is equivalent (assuming no errors are generated) to calling
DispatchCompute with <num_groups_x>, <num_groups_y> and
<num_groups_z>" ...

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94100
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agofreedreno: expose time-elapsed query
Rob Clark [Wed, 10 Feb 2016 19:40:24 +0000 (14:40 -0500)]
freedreno: expose time-elapsed query

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/a4xx: implement time-elapsed query
Rob Clark [Wed, 10 Feb 2016 19:40:01 +0000 (14:40 -0500)]
freedreno/a4xx: implement time-elapsed query

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/a4xx: better occlusion/sample counting
Rob Clark [Sun, 14 Feb 2016 14:59:41 +0000 (09:59 -0500)]
freedreno/a4xx: better occlusion/sample counting

This seems to give more reliable results.  More similar to what we do on
a3xx, although I think it breaks the a3xx theory that the four sets of
results map to each MRT (since we appear to still only have four sets on
a4xx).  The divide-by-two is a bit odd, but seems to be needed for some
reason.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/query: fix refcnt'ing issue
Rob Clark [Sat, 13 Feb 2016 18:46:05 +0000 (13:46 -0500)]
freedreno/query: fix refcnt'ing issue

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/query: some queries don't have ->begin_query()
Rob Clark [Sun, 14 Feb 2016 15:02:13 +0000 (10:02 -0500)]
freedreno/query: some queries don't have ->begin_query()

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/query: align counter snapshot locations
Rob Clark [Sat, 13 Feb 2016 23:29:28 +0000 (18:29 -0500)]
freedreno/query: align counter snapshot locations

Some hw queries need their sample memory locations to have certain
alignment.  At the moment that isn't an issue, since the only hw query
is occlusion, so all samples have the same size.  But when others are
added with different sample sizes, this starts to be a problem.

All current and immediately upcoming hw queries simply need their
sample address aligned to their size, so let's use that for now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/query: add optional enable hook
Rob Clark [Wed, 10 Feb 2016 19:31:59 +0000 (14:31 -0500)]
freedreno/query: add optional enable hook

Add enable hook for hw query providers.  Some will need to configure
perfctr selector registers, which we want to do at the start of the
submit.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno: query max gpu freq
Rob Clark [Wed, 10 Feb 2016 18:25:32 +0000 (13:25 -0500)]
freedreno: query max gpu freq

This will be needed to support converting from cycle counts to time for
performance related queries (initially time-elapsed, but there are some
additional performance counters that could be wired up).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno: update generated headers
Rob Clark [Wed, 10 Feb 2016 17:07:02 +0000 (12:07 -0500)]
freedreno: update generated headers

Mostly to pull in perf ctrs.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
5 years agofreedreno/ir3: fix new gcc6 errors
Rob Clark [Tue, 16 Feb 2016 18:11:25 +0000 (13:11 -0500)]
freedreno/ir3: fix new gcc6 errors

src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c: In function ‘emit_tex’:
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c:1368:26: warning: unused variable ‘const_off’ [-Wunused-variable]
  struct ir3_instruction *const_off[4];
                          ^~~~~~~~~
unused since:

commit 8750299a420af76cebd3067f6f603eacde06ae06
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date:   Tue Feb 9 14:51:28 2016 -0800

    nir: Remove the const_offset from nir_tex_instr

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agonv50/ir: we can't do the add to mad conversion when the mul saturates
Karol Herbst [Thu, 28 Jan 2016 15:45:58 +0000 (16:45 +0100)]
nv50/ir: we can't do the add to mad conversion when the mul saturates

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50/ir: optimize neg(and(set, 1)) to set
Karol Herbst [Sat, 23 Jan 2016 23:16:05 +0000 (00:16 +0100)]
nv50/ir: optimize neg(and(set, 1)) to set

helps shaders in saints row IV, bioshock infinite and shadow warrior

total instructions in shared programs : 1914931 -> 1903900 (-0.58%)
total gprs used in shared programs    : 247920 -> 247785 (-0.05%)
total local used in shared programs   : 5673 -> 5673 (0.00%)
total bytes used in shared programs   : 17558272 -> 17457320 (-0.57%)

                local        gpr       inst      bytes
    helped           0         137         719         719
      hurt           0          12           0           0

v2: remove this opt for OP_SLCT and check against float for OP_SET
v3: simplified the code

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50/ir: fix quadop emission in the presence of predication
Ilia Mirkin [Tue, 16 Feb 2016 07:26:54 +0000 (02:26 -0500)]
nv50/ir: fix quadop emission in the presence of predication

When there's a predicate, it just goes onto the sources list. If the
quadop only has a single regular source, we will end up thinking that
the predicate is the second source. Check explicitly for the predSrc so
that we don't accidentally emit the wrong thing.

This fixes a bunch of dEQP-GLES3.functional.shaders.derivate.* tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
5 years agonv50,nvc0: enable/disable seamless cubemap texturing as requested
Ilia Mirkin [Sun, 14 Feb 2016 03:14:02 +0000 (22:14 -0500)]
nv50,nvc0: enable/disable seamless cubemap texturing as requested

In a situation where the seamless setting isn't available on a
per-texture basis (G200+ Teslas, and all Fermis), assume that all
samplers will have it identically set, and enable accordingly.

This fixes arb_seamless_cubemap piglit test on Fermi and Tesla.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agost/mesa: add missing ETC2 entries to format_map
Rob Clark [Tue, 16 Feb 2016 16:43:38 +0000 (11:43 -0500)]
st/mesa: add missing ETC2 entries to format_map

Noticed by Ilia when I was trying to figure out why some app was failing
to use ETC2.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: enable compute support on GK110:GM200 with an envvar
Samuel Pitoiset [Sat, 13 Feb 2016 23:32:34 +0000 (00:32 +0100)]
nvc0: enable compute support on GK110:GM200 with an envvar

Without this NVF0_COMPUTE environment variable, compute support is
initialized by default and this is not what we want for now because
it might break 3D. It will be enabled by default once we are sure it
won't break anything.

Please note that compute support on GM200+ is not enabled yet because
it needs to be double-checked.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: add compute support for GM107
Samuel Pitoiset [Sat, 13 Feb 2016 23:19:13 +0000 (00:19 +0100)]
nvc0: add compute support for GM107

Fortunately, compute support on GM107 is very close to GK110, except
the GK110_COMPUTE.UNK02C4 which is invalid and should not be used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: fix compute state initialization on GK110+
Samuel Pitoiset [Sat, 13 Feb 2016 23:14:34 +0000 (00:14 +0100)]
nvc0: fix compute state initialization on GK110+

Because our firmware doesn't support the GK110_COMPUTE.FIRMWARE[0x6]
method the GPU hangs when it is used. Removing it fix the issue and
allow to launch compute shaders on GK110+.

Tested on GK208 and GM107.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agoglsl: remove duplicate interpolation_string() function
Timothy Arceri [Sat, 13 Feb 2016 22:51:31 +0000 (09:51 +1100)]
glsl: remove duplicate interpolation_string() function

We already have one in the IR code that can be used everywhere its
needed in the AST code so remove the one from the AST.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
5 years agoglsl: remove unused helper
Timothy Arceri [Mon, 15 Feb 2016 07:38:29 +0000 (18:38 +1100)]
glsl: remove unused helper

Seems to have become unused when i965 moved to NIR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
5 years agoglsl: set user defined varyings to smooth by default in ES
Timothy Arceri [Tue, 16 Feb 2016 00:03:56 +0000 (11:03 +1100)]
glsl: set user defined varyings to smooth by default in ES

This is usually handled by the backends in order to handle the
various interactions with the gl_*Color built-ins.

The problem is this means linking will fail if one side on the
interface adds the smooth qualifier to the varying and the other
side just uses the default even though they match.

This fixes various deqp tests. The spec is not clear what to for
desktop GL so leave it as is for now.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92743

5 years agogm107/ir: add ATOM CAS emission
Samuel Pitoiset [Tue, 16 Feb 2016 17:53:11 +0000 (18:53 +0100)]
gm107/ir: add ATOM CAS emission

This fixes the following dEQP test and the other compswap variants.

dEQP-GLES31.functional.ssbo.atomic.compswap.highp_int

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agost/mesa: do not init limits when compute shaders are not supported
Samuel Pitoiset [Mon, 15 Feb 2016 21:40:46 +0000 (22:40 +0100)]
st/mesa: do not init limits when compute shaders are not supported

When the number of uniform blocks is less than 12,
ARB_uniform_buffer_object can't be enabled and the maximum GL version
is not even 3.1...

This fixes a regression introduced in 7c79c1e (st/mesa: add compute
shader state) if the maximum number of uniform blocks allowed for
compute shaders is less than 12. This happens on Kepler but this might
also affect other Gallium drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reported-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
5 years agomesa: Don't call driver when there is no compute work
Jordan Justen [Tue, 16 Feb 2016 16:21:22 +0000 (08:21 -0800)]
mesa: Don't call driver when there is no compute work

The ARB_compute_shader spec says:

  "If the work group count in any dimension is zero, no work groups
   are dispatched."

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agoi965: Set compute shader shared memory max to 64k
Jordan Justen [Sat, 13 Feb 2016 22:25:33 +0000 (14:25 -0800)]
i965: Set compute shader shared memory max to 64k

See Ivy Bridge PRM, Volume 2, Part 2, 1.8.4 INTERFACE_DESCRIPTOR_DATA:

DWORD 5, bits 20:16: "This field indicates how much shared local
memory the thread group requires. The amount is specified in 4k
blocks, but only powers of 2 are allowed: 0, 4k, 8k, 16k, 32k and 64k
per half-slice."

For Haswell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA:

DWORD 5, bits 20:16: With text identical to the Ivy Bridge PRM.

For Broadwell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA:

DWORD 6, bits 20:16: With text identical to the Ivy Bridge PRM.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agost/mesa: use new CSO_BITS_ALL_SHADERS
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use new CSO_BITS_ALL_SHADERS

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agocso: add CSO_BITS_ALL_SHADERS
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
cso: add CSO_BITS_ALL_SHADERS

For saving/restoring all shader stages.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agost/mesa: simplify st->ctx, ctx->st usage in a various places
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: simplify st->ctx, ctx->st usage in a various places

5 years agost/mesa: use _mesa_geometric_width/height() in glDrawPixels code
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use _mesa_geometric_width/height() in glDrawPixels code

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agost/mesa: rename attr variable in st_DrawTex()
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: rename attr variable in st_DrawTex()

Rename to 'tex_attr' to be a bit more clear.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: use 'cso' instead of 'st->cso_context' in st_DrawTex()
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use 'cso' instead of 'st->cso_context' in st_DrawTex()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: fix whitespace and add comment in st_DrawTex()
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: fix whitespace and add comment in st_DrawTex()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: used _mesa_num_tex_faces() in st_finalize_texture()
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: used _mesa_num_tex_faces() in st_finalize_texture()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agocso: make most of the cso_save/restore_x() functions static
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
cso: make most of the cso_save/restore_x() functions static

Users of the CSO save/restore facility all use the new
cso_save/restore_state() functions instead.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agopostprocess: use new cso_save/restore_state() functions
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
postprocess: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agogallium/hud: use new cso_save/restore_state() functions
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
gallium/hud: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agogallium/util: use new cso_save/restore_state() functions
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
gallium/util: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: use cso_save/restore_state() in st_cb_texture.c
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use cso_save/restore_state() in st_cb_texture.c

This simplifies the error handling code too.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: use new cso_save/restore_state() functions
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agocso: add new cso_save/restore_state() functions
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
cso: add new cso_save/restore_state() functions

cso_save_state() takes a bitmask of state items to save.  Calling
cso_restore_state() restores those states.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agocso: remove comment
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
cso: remove comment

There's a similar comment just a few lines before.

5 years agost/mesa: use new cso_set_viewport_dims() helper
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use new cso_set_viewport_dims() helper

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agocso: add new cso_set_viewport_dims() helper
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
cso: add new cso_set_viewport_dims() helper

To simplify some viewport setting code in the state tracker.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: use 'cso' local var instead of st->cso_context
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: use 'cso' local var instead of st->cso_context

Just a little cleaner.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: consolidate quad drawing code
Brian Paul [Tue, 16 Feb 2016 17:22:32 +0000 (10:22 -0700)]
st/mesa: consolidate quad drawing code

The glClear, glBitmap and glDrawPixels code now use a new st_draw_quad()
helper function.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap
Brian Paul [Tue, 16 Feb 2016 17:22:31 +0000 (10:22 -0700)]
st/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap

Define a new st_util_vertex structure which is a bit smaller (9 floats
versus the previous 12 floats per vertex).  Clean up the glClear,
glDrawPixels and glBitmap code that sets up the vertex data and does the
drawing so it's all very similar.  This can lead to more consolidation.

v2: add assertion that vertex buffer slot == 0 to catch possible future
change in cso_get_aux_vertex_buffer_slot() behavior.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agost/mesa: include u_draw.h, not u_draw_quad.h in st_draw.c
Brian Paul [Tue, 16 Feb 2016 17:22:31 +0000 (10:22 -0700)]
st/mesa: include u_draw.h, not u_draw_quad.h in st_draw.c

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
5 years agoconfigure: Bail out on llvm-config component error
Jan Vesely [Fri, 12 Feb 2016 23:58:55 +0000 (18:58 -0500)]
configure: Bail out on llvm-config component error

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
5 years agoHandle removal of LLVMAddTargetData in SVN revision 260919
Matthew Dawson [Tue, 16 Feb 2016 06:25:20 +0000 (01:25 -0500)]
Handle removal of LLVMAddTargetData in SVN revision 260919

LLVM removed LLVMAddTargetData for the 3.9 release in r260919.  For the two
places in mesa where this is called, only enable the lines when compiling
for less then 3.9.

For the radeon driver, I'm not sure how to check if any other LLVM calls need
to be adjusted.  I think since the target data used is extracted from the
LLVMModule, it isn't necessary to pass it back to LLVM again.

The code does compile, and at least for radeonsi does run OpenGL games.

[ Michel Dänzer: Move #if closer to LLVMAddTargetData in lp_bld_init.c,
  and add HAVE_LLVM < 0x0309 guards around now unused occurrences of TD
  and data_layout ]

Signed-off-by: Matthew Dawson <matthew@mjdsystems.ca>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
5 years agoi965: Expose logic telling if non-msrt mcs is supported
Topi Pohjolainen [Fri, 1 Jan 2016 15:02:00 +0000 (17:02 +0200)]
i965: Expose logic telling if non-msrt mcs is supported

Alos use the opportunity to mark inputs constant. (Context has to be
given as read-write to intel_miptree_supports_non_msrt_fast_clear()
to support debug output).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoi965/gen9: Refactor msrt mcs initialization
Topi Pohjolainen [Thu, 10 Dec 2015 14:03:03 +0000 (16:03 +0200)]
i965/gen9: Refactor msrt mcs initialization

This will be re-used to initialize auxiliary buffers in lossless
compression case.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoi965: Add a few assertions on lossless compression
Topi Pohjolainen [Tue, 2 Feb 2016 08:04:34 +0000 (10:04 +0200)]
i965: Add a few assertions on lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoi965: Add a flag telling color resolve pass to ignore CCS_E
Topi Pohjolainen [Tue, 2 Feb 2016 08:00:41 +0000 (10:00 +0200)]
i965: Add a flag telling color resolve pass to ignore CCS_E

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoi965: Add resolve option for lossless compression
Topi Pohjolainen [Wed, 9 Dec 2015 13:48:57 +0000 (15:48 +0200)]
i965: Add resolve option for lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoi965: Allow fast clear to be used with lossless compression
Topi Pohjolainen [Mon, 7 Dec 2015 10:23:04 +0000 (12:23 +0200)]
i965: Allow fast clear to be used with lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression.
v3 (Ben): Squash with "i965: Resolve color buffer also in
          lossless compression case" and clarify simple
          non-compressed fast clear case.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoi965: Add helper for detecting lossless compression
Topi Pohjolainen [Thu, 11 Feb 2016 08:42:13 +0000 (10:42 +0200)]
i965: Add helper for detecting lossless compression

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
5 years agoRevert "i965: Restore vbo after color resolve during brw_try_draw_prims()"
Topi Pohjolainen [Mon, 15 Feb 2016 08:58:41 +0000 (10:58 +0200)]
Revert "i965: Restore vbo after color resolve during brw_try_draw_prims()"

This got pushed accidentally in the first place but wasn't reverted
as it didn't regress piglit but instead fixed one newly introduced
test exercising a corner in case in i965 driver. However, saving and
restoring vertex buffer context is complicated and requires more
thought.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94150

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Tapani Palli <tapani.palli@intel.com>
5 years agonvc0: initial support for GM20x GPUs
Ben Skeggs [Mon, 15 Feb 2016 21:56:44 +0000 (07:56 +1000)]
nvc0: initial support for GM20x GPUs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: implement support for maxwell texture headers
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nvc0: implement support for maxwell texture headers

Adds support for the new TIC layout that's present on Maxwell GPUs,
heavily based on the code for the existing layout.

This code is required for GM20x support.  While GM10x supports the older
layout still, this commit switches it to use the updated version instead.

Piglit testing shows zero regressions on GM107.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: import maxwell texture header definitions from rnndb
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nvc0: import maxwell texture header definitions from rnndb

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: split tic format specification
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: split tic format specification

We previously stored texture format information as it would appear in
the TIC.

We're about to support the new TIC layout that appeared with Maxwell,
so it makes more sense to store the data in a split-out format.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: remove nv50_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: remove nv50_texture.xml.h

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: switch nvc0_tex.c to updated g80_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nvc0: switch nvc0_tex.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: switch nvc0_surface.c to updated g80_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nvc0: switch nvc0_surface.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50: switch nv50_tex.c to updated g80_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50: switch nv50_tex.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50: switch nv50_surface.c to updated g80_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50: switch nv50_surface.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50: switch nv50_state.c to updated g80_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50: switch nv50_state.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: switch nv50_formats.c to updated g80_texture.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: switch nv50_formats.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50: import updated g80_texture.xml.h from rnndb
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50: import updated g80_texture.xml.h from rnndb

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: remove nv50_defs.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: remove nv50_defs.xml.h

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: switch nv50_formats.c to updated g80_defs.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: switch nv50_formats.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: improved macros to handle format specification
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: improved macros to handle format specification

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50-: separate vertex formats from surface format descriptions
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nv50-: separate vertex formats from surface format descriptions

We've previously had identical naming between vertex and texture
formats, so it mostly made sense to define these together.

However, upcoming patches are going to transition the driver over to
using updated texture header definitions using NVIDIA's naming, and this
will no longer be the case.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: remove unnecessary includes
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nvc0: remove unnecessary includes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonvc0: switch nvc0_tex.c to updated g80_defs.xml.h
Ben Skeggs [Mon, 15 Feb 2016 05:37:29 +0000 (15:37 +1000)]
nvc0: switch nvc0_tex.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>