mesa.git
4 years agogbm/dri: Fix sign-extension in modifier query
Daniel Stone [Tue, 2 May 2017 18:44:38 +0000 (19:44 +0100)]
gbm/dri: Fix sign-extension in modifier query

When we were assembling the unsigned 64-bit query return from its
two signed 32-bit component parts, the lower half was getting
sign-extended into the top half. Be more explicit about what we want to
do.

Fixes gbm_bo_get_modifier() returning ((1 << 64) - 1) rather than
((1 << 56) - 1), i.e. DRM_FORMAT_MOD_INVALID.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
4 years agonir: Pick just the channels we want for bitmap and drawpixels lowering.
Eric Anholt [Wed, 8 Mar 2017 23:20:31 +0000 (15:20 -0800)]
nir: Pick just the channels we want for bitmap and drawpixels lowering.

NIR now validates that SSA references use the same number of channels as
are in the SSA value.

v2: Reword commit message, since the commit didn't land before the
    validation change did.

Fixes: 370d68babcbb ("nir/validate: Validate that bit sizes and components always match")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Cc: <mesa-stable@lists.freedesktop.org>
4 years agoanv/tests: Create a dummy instance as well as device
Jason Ekstrand [Mon, 1 May 2017 23:48:12 +0000 (16:48 -0700)]
anv/tests: Create a dummy instance as well as device

This fixes crashes caused by 35e626bd0e59e7ce9fd97ccef66b2468c09206a4
which made us start referencing the instance in the allocators.  With
this commit, the tests now happily pass again.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100877
Tested-by: Vinson Lee <vlee@freedesktop.org>
4 years agoradv: Use correct stage for ready bit.
Bas Nieuwenhuizen [Sun, 30 Apr 2017 15:56:24 +0000 (17:56 +0200)]
radv: Use correct stage for ready bit.

Set the bit in the same stage as the timestamp, instead always at top of pipe.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
4 years agoradv: Add top of pipe timestamp queries.
Bas Nieuwenhuizen [Sun, 30 Apr 2017 15:49:15 +0000 (17:49 +0200)]
radv: Add top of pipe timestamp queries.

Does not fix brokenness with the ready bit.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agoradv: Add NIR loop unrolling.
Bas Nieuwenhuizen [Wed, 26 Apr 2017 20:29:01 +0000 (22:29 +0200)]
radv: Add NIR loop unrolling.

Not much effect on dota2/talos, but positive on deferred.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@itsqueeze.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agoi965: Solve Android native fence fd double close
Randy Xu [Tue, 18 Apr 2017 06:27:10 +0000 (14:27 +0800)]
i965: Solve Android native fence fd double close

The Android native fence in i965 has two fds: _EGLSync::SyncFd and
brw_fence::sync_fd.

The semantics of __DRI2fenceExtensionRec::create_fence_fd are unclear on
whether the DRI driver takes ownership of the incoming fd (which is the
same incoming fd from eglCreateSync).  i965 did take ownership, but all
other Mesa drivers do not; instead, they dup the incoming fd. As
a result, _EGLSync::SyncFd and brw_fence::sync_fd were the same fd, and
both egl_dri2 and i965 believed they owned it. On eglDestroySync, that
led to a double-close.

Fix the double-close by making brw_dri_create_fence_fd dup the incoming
fd, just like the other drivers do.

Signed-off-by: Randy Xu <randy.xu@intel.com>
Test: Run Vulkan and GLES stress test and no crash.
Fixes: 6403e376511 ("i965/sync: Implement fences based on Linux sync_file")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
[chadv: Polish the commit message]
Cc: mesa-stable@lists.freedesktop.org
4 years agovc4: Only build the NEON code on arm32.
Eric Anholt [Fri, 14 Apr 2017 17:41:51 +0000 (10:41 -0700)]
vc4: Only build the NEON code on arm32.

NEON is sufficiently different on arm64 that we can't just reuse this
code.  Disable it on arm64 for now.

v2: Use PIPE_ARCH_ARM instead, as __ARM_ARCH may be 8 for a 32-bit build
    for a v8 CPU.

Signed-off-by: Eric Anholt <eric@anholt.net>
Cc: <mesa-stable@lists.freedesktop.org>
4 years agogm107/ir: add a missing assertion in emitISCADD()
Samuel Pitoiset [Sat, 29 Apr 2017 15:40:26 +0000 (17:40 +0200)]
gm107/ir: add a missing assertion in emitISCADD()

For consistency, similar to the other emitters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
4 years agoi965: Don't allocate uniform space for samplers
Timothy Arceri [Sun, 30 Apr 2017 02:12:35 +0000 (12:12 +1000)]
i965: Don't allocate uniform space for samplers

Samplers are encoded into the instruction word, so there's no need to
make space in the uniform file.

Previously matrix_columns and vector_elements were set to 0, making this
else case a no-op. Commit 75a31a20af26 changed that, causing malloc
corruption in thousands of tests on i965.

Fixes: 75a31a20af26 ("glsl: set vector_elements to 1 for samplers")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100871

4 years agoegl: initialise dummy_thread via _eglInitThreadInfo
Emil Velikov [Tue, 25 Apr 2017 16:07:46 +0000 (17:07 +0100)]
egl: initialise dummy_thread via _eglInitThreadInfo

Considering we cannot make dummy_thread a constant we might as well,
initialise by the same function that handles the actual thread info.

This way we don't need to worry about mismatch between the initialiser
and initialising function.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agoegl: polish dri2_to_egl_attribute_map[]
Emil Velikov [Fri, 28 Apr 2017 16:01:03 +0000 (17:01 +0100)]
egl: polish dri2_to_egl_attribute_map[]

Annotate the array as static const and use C99 initialiser to populate
it.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agogallium/targets: fix bool setting on BE architectures
Ilia Mirkin [Tue, 18 Apr 2017 04:00:40 +0000 (00:00 -0400)]
gallium/targets: fix bool setting on BE architectures

val_bool and val_int are in a union. val_bool gets the first byte, which
happens to work on LE when setting via the int, but breaks on BE. By
setting the value properly, we are able to use DRI3 on BE architectures.
Tested by running glxgears with a NV34 in a G5 PPC.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
[Emil Velikov: squash the vmwgfx hunk]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4 years agodocs: add release calendar page and references to it
Emil Velikov [Mon, 24 Apr 2017 16:22:19 +0000 (17:22 +0100)]
docs: add release calendar page and references to it

Add a page that has information which release is expected when and
associated information.

Reference to it from the "Releasing process" and "Release notes" pages.

v2:
 - Add Andres for 17.0.5
 - Rework table format to include the branch (Eric)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agotravis: bump MAKEFLAGS to -j4
Emil Velikov [Thu, 27 Apr 2017 16:09:12 +0000 (17:09 +0100)]
travis: bump MAKEFLAGS to -j4

The instance should have 2 cores, yet bumping the jobs to 4 should give
us a minor speed improvement.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: enable wayland support
Emil Velikov [Tue, 18 Apr 2017 12:57:31 +0000 (13:57 +0100)]
travis: enable wayland support

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: add Gallium state-tracker targets
Emil Velikov [Fri, 7 Apr 2017 13:06:25 +0000 (14:06 +0100)]
travis: add Gallium state-tracker targets

Split into OpenCL and others, since the former is quite time consuming.

v2:
 - explicitly enable/disable components
 - build libvdpau 1.1 requirement
 - enable st/vdpau
 - build libva 1.6.2 (API 0.38) requirement

v3: Drop ubuntu-toolchain-r-test from sources (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: model scons check target like the make one
Emil Velikov [Fri, 28 Apr 2017 18:01:33 +0000 (19:01 +0100)]
travis: model scons check target like the make one

Should make things a bit more consistent across the board.

Cc: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: split the make target to three separate ones
Emil Velikov [Fri, 7 Apr 2017 11:13:56 +0000 (12:13 +0100)]
travis: split the make target to three separate ones

Split the target to allow faster builds for each run.

The overall build time will be more, yet Travis runs multiple builds in
parallel so we're limited by the slowest one.

Things are split roughly as:
 - DRI loaders, classic DRI drivers, classic OSMesa, make check
 - All Gallium drivers (minus the SWR) alongside st/dri (mesa)
 - The Vulkan drivers - ANV and RADV, make check (anv)

v2:
 - rework RUN_CHECK to MAKE_CHECK_COMMAND
 - explicitly disable DRI loaders
 - generate linux/memfd.h locally and enable ANV
 - add libedit-dev

v3: Use printf to create the header (Andres).
v4: Really add the libedit + printf hunks.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: add "make swr" to the build matrix
Emil Velikov [Thu, 6 Apr 2017 17:01:19 +0000 (18:01 +0100)]
travis: add "make swr" to the build matrix

v2: Quote OVERRIDE variables.
v3: Add missplaced libedit-dev hunk (Andres).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: add "scons swr" to the build matrix
Emil Velikov [Thu, 6 Apr 2017 15:23:21 +0000 (16:23 +0100)]
travis: add "scons swr" to the build matrix

Requires GCC 5.0 (due to the C++14 requirement) and LLVM 3.9.

v2: Enable the target, add libedit-dev, rework check target.
v3: Comment the current check target, add -j4 SCONSFLAGS, quote OVERRIDE
variables.
v4: Keep check target as-is (Andres)

Cc: Tim Rowley <timothy.o.rowley@intel.com>
Cc: George Kyriazis <george.kyriazis@intel.com>
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: add separate "scons" and "scons llvm" targets
Emil Velikov [Thu, 6 Apr 2017 13:41:44 +0000 (14:41 +0100)]
travis: add separate "scons" and "scons llvm" targets

The former does not require any LLVM, while the latter uses LLVM 3.3.

This way we'll quickly catch any LLVM 3.3+ functionality that gets
introduced where it shouldn't.

Add the full list of addons for each build permutation.

v2: Keep libedit-dev, rework check target.
v3: Comment the current check target, add -j4 SCONSFLAGS
v4:
 - Remove llvm-toolchain-trusty-3.3 source (Andres)
 - Keep check target as-is (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: split out matrix from env
Emil Velikov [Thu, 6 Apr 2017 13:38:40 +0000 (14:38 +0100)]
travis: split out matrix from env

With next commits we'll add a couple of more options.

v2: Rework check target.
v3: Comment the current check target, add -j4 SCONSFLAGS
v4: Keep check target as-is, will rework with later patch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: rework "if test" blocks in the script section
Emil Velikov [Thu, 6 Apr 2017 13:23:36 +0000 (14:23 +0100)]
travis: rework "if test" blocks in the script section

Split the "if test" blocks so that we get more sensible output in case
of a failure.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: remove unused -dev packages
Emil Velikov [Thu, 6 Apr 2017 13:09:58 +0000 (14:09 +0100)]
travis: remove unused -dev packages

We effectively override libdrm-dev and libxcb-dri2-0-dev since we build
and install the package locally.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: automatically manage ccache caching
Emil Velikov [Thu, 6 Apr 2017 13:02:38 +0000 (14:02 +0100)]
travis: automatically manage ccache caching

According to the manual

"If you are using ccache, use:

  language: c # or other C/C++ variants

  cache: ccache

to cache $HOME/.ccache and automatically add /usr/lib/ccache to your
$PATH."

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: enable apt cache
Emil Velikov [Thu, 6 Apr 2017 15:36:59 +0000 (16:36 +0100)]
travis: enable apt cache

Provides a small, but consistent improvement.
Example numbers of the jobs added later in the series.

"make loaders/classic DRI" - 1s
"scons SWR" - 6s

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agotravis: add the possibility of using the txc-dxtn library
Andres Gomez [Fri, 7 Apr 2017 12:16:21 +0000 (15:16 +0300)]
travis: add the possibility of using the txc-dxtn library

The txc-dxtn library implements the patented S3 Texture Compression
algorithm.

By default it won't be used but we add the possibility of setting the
USE_TXC_DXTN variable to yes in the travis web UI so it will be
installed and used for the scons tests.

Cc: Eric Anholt <eric@anholt.net>
Cc: Rhys Kidd <rhyskidd@gmail.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
[Emil Velikov: keep the LIB prefix, drop the LD_LIBRARY_PATH, fold URL]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
4 years agotravis: replace Trusty-based LLVM toolchain apt-get with apt addon
Andres Gomez [Wed, 5 Apr 2017 17:27:30 +0000 (20:27 +0300)]
travis: replace Trusty-based LLVM toolchain apt-get with apt addon

Trusty's LLVM toochain repository was whitelisted some time ago. See:
https://github.com/travis-ci/apt-source-whitelist/commit/479067c5e74cb0c1e2419209179b1afe2edce274

Signed-off-by: Andres Gomez <agomez@igalia.com>
[Emil Velikov]
 - set sudo to false
 - reference the Trusty change (Rhys)
 - keep libedit-dev
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
4 years agotravis: explicitly LD_LIBRARY_PATH the local libraries
Emil Velikov [Thu, 6 Apr 2017 12:32:36 +0000 (13:32 +0100)]
travis: explicitly LD_LIBRARY_PATH the local libraries

Some of the libraries may be dlopened, which may not always work due to
the non-standard prefix that we're using.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
4 years agost/wgl: whitespace, formatting fixes in stw_pixelformat.c
Brian Paul [Sat, 29 Apr 2017 03:48:47 +0000 (21:48 -0600)]
st/wgl: whitespace, formatting fixes in stw_pixelformat.c

Trivial.

4 years agost/wgl: allow WGL_BIND_TO_TEXTURE_RGB_ARB for RGBA visuals
Charmaine Lee [Wed, 18 May 2016 17:11:25 +0000 (10:11 -0700)]
st/wgl: allow WGL_BIND_TO_TEXTURE_RGB_ARB for RGBA visuals

We do not need to restrict WGL_BIND_TO_TEXTURE_RGB_ARB to
RGB visuals only. It can be supported with RGBA visuals as well.

This fixes the early exit of cinebench-r15-test trace.

Tested with cinebench-r15, piglit, glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>
4 years agost/wgl: use ARRAY_SIZE() macro in wglChoosePixelFormatARB()
Brian Paul [Sat, 29 Apr 2017 03:32:05 +0000 (21:32 -0600)]
st/wgl: use ARRAY_SIZE() macro in wglChoosePixelFormatARB()

Trivial.

4 years agost/wgl: whitespace/formatting fixes in stw_ext_pixelformat.c
Brian Paul [Sat, 29 Apr 2017 03:32:05 +0000 (21:32 -0600)]
st/wgl: whitespace/formatting fixes in stw_ext_pixelformat.c

Trivial.

4 years agosvga: implement sRGB rendering for imported surfaces
Neha Bhende [Thu, 27 Apr 2017 17:05:35 +0000 (10:05 -0700)]
svga: implement sRGB rendering for imported surfaces

If texture is imported and templ format is sRGB, use compatible sRGB format
to the imported texture format while creating surface view.

tested with MTT piglit, glretrace, viewperf and conform

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agosvga: add function svga_linear_to_srgb()
Neha Bhende [Thu, 27 Apr 2017 17:37:02 +0000 (10:37 -0700)]
svga: add function svga_linear_to_srgb()

This function will return compatible svga srgb format for corresponding
linear format

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agoglx: add missing sRGB attribute check in fbconfigs_compatible()
Neha Bhende [Wed, 26 Apr 2017 23:21:32 +0000 (16:21 -0700)]
glx: add missing sRGB attribute check in fbconfigs_compatible()

This patch will allow driver to choose srgb capable FBconfig
if GLX_FRAMEBUFFER_SRGB_CAPABLE_ARB attribute is 1

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agosvga: Add a more elaborate format compatibility determination v2
Thomas Hellstrom [Fri, 7 Apr 2017 12:54:56 +0000 (14:54 +0200)]
svga: Add a more elaborate format compatibility determination v2

dri3 is a bit sloppy about its format compatibility requirements, so add
a possibility to import xrgb surfaces as argb textures and vice versa.

At the same time, make the svga_texture_from_handle() function a bit more
readable and fix the error path where we leaked a winsys surface.

v2: Addressed review comments by Brian.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agoswr/rast: add memory api to SwrGetInterface()
Tim Rowley [Sat, 22 Apr 2017 03:14:16 +0000 (22:14 -0500)]
swr/rast: add memory api to SwrGetInterface()

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: use gather instruction for odd format fetch
Tim Rowley [Fri, 21 Apr 2017 18:35:55 +0000 (13:35 -0500)]
swr/rast: use gather instruction for odd format fetch

Small fetch performance optimization - use gather instruction
for odd format fetch instead of slow emulated code.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: enable SIMD16 8x2 tile backend
Tim Rowley [Fri, 21 Apr 2017 18:18:55 +0000 (13:18 -0500)]
swr/rast: enable SIMD16 8x2 tile backend

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: add SwrInit() to init backend/memory tables
Tim Rowley [Fri, 21 Apr 2017 15:21:19 +0000 (10:21 -0500)]
swr/rast: add SwrInit() to init backend/memory tables

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: increment depth/stencil tile pointer in SIMD16 BE
Tim Rowley [Thu, 20 Apr 2017 23:34:29 +0000 (18:34 -0500)]
swr/rast: increment depth/stencil tile pointer in SIMD16 BE

Misplaced #endif preventing depth and stencil hot tile pointers
from incrementing in SIMD16 8x2 configuration of BackendPixelRate.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: add SwrGetInterface() function to return api
Tim Rowley [Thu, 20 Apr 2017 00:00:21 +0000 (19:00 -0500)]
swr/rast: add SwrGetInterface() function to return api

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: enable per-warp scratch space for CS
Tim Rowley [Wed, 19 Apr 2017 22:03:32 +0000 (17:03 -0500)]
swr/rast: enable per-warp scratch space for CS

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: reduce simd{16}vertex stack for VS output
Tim Rowley [Wed, 19 Apr 2017 17:21:05 +0000 (12:21 -0500)]
swr/rast: reduce simd{16}vertex stack for VS output

Frontend - reduce simdvertex/simd16vertex stack usage for VS output in
ProcessDraw, fixes stack overflow in some of the deeper call stacks under
SIMD16.

1. Move the vertex store out of PA_FACTORY, and off the stack
2. Allocate the vertex store out of the aligned heap (pointer is
   temporarily stored in TLS, but will be migrated to thread pool
   along with other frontend temporary buffers).
3. Grow the vertex store as necessary for the number of verts per
   primitive, in chunks of 8/4 simdvertex/simd16vertex

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: remove default argument from SwrSync()
Tim Rowley [Wed, 19 Apr 2017 15:58:59 +0000 (10:58 -0500)]
swr/rast: remove default argument from SwrSync()

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: remove unused variables in the SIMD16 FE
Tim Rowley [Thu, 13 Apr 2017 21:26:08 +0000 (16:26 -0500)]
swr/rast: remove unused variables in the SIMD16 FE

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: move construction of const above goto
Tim Rowley [Thu, 13 Apr 2017 21:11:09 +0000 (16:11 -0500)]
swr/rast: move construction of const above goto

Fixes gcc error for SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: name threads to aid debugging
Tim Rowley [Thu, 13 Apr 2017 21:01:12 +0000 (16:01 -0500)]
swr/rast: name threads to aid debugging

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: disable buffer overrun warning for Assemble()
Tim Rowley [Wed, 26 Apr 2017 18:11:00 +0000 (13:11 -0500)]
swr/rast: disable buffer overrun warning for Assemble()

Disabling buffer overrun warning for Assemble(uint32_t slot,
simdvector *verts) due to what looks like a MSVC compiler bug
when compiling the SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: clean up clipper comments
Tim Rowley [Wed, 26 Apr 2017 18:10:23 +0000 (13:10 -0500)]
swr/rast: clean up clipper comments

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: add SIMDAPI decorators in binner/clipper
Tim Rowley [Wed, 26 Apr 2017 18:09:00 +0000 (13:09 -0500)]
swr/rast: add SIMDAPI decorators in binner/clipper

Fixes MSVC errors with SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: add additional jit utility functions
Tim Rowley [Tue, 11 Apr 2017 22:25:11 +0000 (17:25 -0500)]
swr/rast: add additional jit utility functions

Not used yet.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: more flexible max attribute slots
Tim Rowley [Mon, 10 Apr 2017 16:29:45 +0000 (11:29 -0500)]
swr/rast: more flexible max attribute slots

Ability to allocate space for an arbitrary number (at compile time)
of positions in the vertex layout.

Removes KNOB_NUM_ATTRIBUTES from knobs.h, replaces the VTX slot
number #defines with the SWR_VTX_SLOTS enum (which contains
replacement for NUM_ATTRIBUTES: SWR_VTX_NUM_SLOTS)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoi965: Drop BRW_NEW_CONTEXT from 3DSTATE_DS/GS on Gen7-7.5.
Kenneth Graunke [Thu, 27 Apr 2017 06:49:49 +0000 (23:49 -0700)]
i965: Drop BRW_NEW_CONTEXT from 3DSTATE_DS/GS on Gen7-7.5.

We already have BRW_NEW_BATCH, which completely covers all the cases
that BRW_NEW_CONTEXT would handle.  Drop it.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
4 years agoi965: Drop _NEW_TRANSFORM from 3DSTATE_DS/GS on Gen7-7.5.
Kenneth Graunke [Thu, 27 Apr 2017 06:48:49 +0000 (23:48 -0700)]
i965: Drop _NEW_TRANSFORM from 3DSTATE_DS/GS on Gen7-7.5.

There's no reason for this as far as I can tell.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
4 years agoi965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.
Kenneth Graunke [Thu, 27 Apr 2017 05:34:50 +0000 (22:34 -0700)]
i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.

Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not.  We ought to
be consistent - the answer depends on the API, not the hardware generation.

The Sandybridge PRM says about RASTRULE_UPPER_RIGHT:

   "To match OpenGL point rasterization rules (round to +infinity, where
    this is the upper right direction wrt OpenGL screen origin of lower
    left).

So this is likely the one we should use.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
4 years agoi965: Always set AALINEDISTANCE_TRUE on Sandybridge.
Kenneth Graunke [Wed, 26 Apr 2017 21:27:15 +0000 (14:27 -0700)]
i965: Always set AALINEDISTANCE_TRUE on Sandybridge.

We set this unconditionally on every other platform.  Zero (Manhattan)
isn't even listed as an option in the Sandybridge docs - only "true".

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: Use true AA line distance on G45/Ironlake.
Kenneth Graunke [Wed, 26 Apr 2017 21:28:49 +0000 (14:28 -0700)]
i965: Use true AA line distance on G45/Ironlake.

The original Broadwater and Crestline platforms computed antialiased
line distances using "manhattan" distance, aka a + b = c.  Eaglelake
and Cantiga added "true" distance, which apparently does something
like max(a, b) + min(a, b) / 4.  Not exactly "true", but at least
more accurate.

The G45 documentation indicates that the old manhattan distance setting
is "only for debug purposes" and should never be used.  The Ironlake
documentation no longer mentions AALINEDISTANCE_MANHATTAN, though it
does still contain the narrative about the feature.

At any rate, we should use the more accurate mode.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agodocs: add news item and link release notes for 17.0.5
Andres Gomez [Fri, 28 Apr 2017 17:45:32 +0000 (20:45 +0300)]
docs: add news item and link release notes for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
4 years agodocs: add sha256 checksums for 17.0.5
Andres Gomez [Fri, 28 Apr 2017 22:17:40 +0000 (01:17 +0300)]
docs: add sha256 checksums for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6cb65ce2d3689ae7f692f8cf08559109037dd74e)

4 years agodocs: add release notes for 17.0.5
Andres Gomez [Fri, 28 Apr 2017 17:41:38 +0000 (20:41 +0300)]
docs: add release notes for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 61b134a862ecc1877bbe2f2c14e493b5fb607e04)

4 years agoradeonsi: don't load unused compute shader input SGPRs and VGPRs
Marek Olšák [Mon, 24 Apr 2017 15:27:37 +0000 (17:27 +0200)]
radeonsi: don't load unused compute shader input SGPRs and VGPRs

Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine
whether to load BLOCK_ID for each component separately, and set the number
of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave
rate in most cases.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agotgsi/scan: record compute shader system value usage
Marek Olšák [Mon, 24 Apr 2017 14:29:22 +0000 (16:29 +0200)]
tgsi/scan: record compute shader system value usage

v2: just do indexing with swizzle[i]

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: add a HUD query for draw calls with primitive restart
Marek Olšák [Mon, 24 Apr 2017 10:10:24 +0000 (12:10 +0200)]
radeonsi: add a HUD query for draw calls with primitive restart

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoradeonsi: tell LLVM not to remove s_barrier instructions
Marek Olšák [Sat, 22 Apr 2017 22:46:55 +0000 (00:46 +0200)]
radeonsi: tell LLVM not to remove s_barrier instructions

LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: fix tess offchip offset for per-patch attributes
Marek Olšák [Sat, 22 Apr 2017 19:12:08 +0000 (21:12 +0200)]
radeonsi: fix tess offchip offset for per-patch attributes

We need 4 more bits there. I don't know what is fixed by this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: pass tessellation ring addresses via user SGPRs
Marek Olšák [Sat, 22 Apr 2017 17:34:26 +0000 (19:34 +0200)]
radeonsi: pass tessellation ring addresses via user SGPRs

This removes s_load_dword latency for tess rings.

We need just 1 SGPR for the address if we use 64K alignment. The final asm
for recreating the descriptor is:

    // s2 is (address >> 16)
    s_mov_b32 s3, 0
    s_lshl_b64 s[4:5], s[2:3], 16
    s_mov_b32 s6, -1
    s_mov_b32 s7, 0x27fac

v2: bitcast the descriptor type from v2i64 to v4i32

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue
Marek Olšák [Sat, 22 Apr 2017 16:56:12 +0000 (18:56 +0200)]
radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: remove VS epilog code, compile VS with PrimID export on demand
Marek Olšák [Sat, 22 Apr 2017 16:04:00 +0000 (18:04 +0200)]
radeonsi: remove VS epilog code, compile VS with PrimID export on demand

The use of PrimID in the pixel shader is too rare to deserve such
a sizable support code.

The initial idea of the VS epilog was to move the clipping code there and
remove it based on states, but optimized variants are now used to do that
and are easier to support, so the VS epilog has turned out to be not so
useful.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3
Marek Olšák [Sat, 22 Apr 2017 15:27:10 +0000 (17:27 +0200)]
radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3

VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: don't load PrimID in TES if it's not used
Marek Olšák [Sat, 22 Apr 2017 12:12:52 +0000 (14:12 +0200)]
radeonsi: don't load PrimID in TES if it's not used

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: explain (non-)monolithic shaders
Marek Olšák [Wed, 19 Apr 2017 23:07:19 +0000 (01:07 +0200)]
radeonsi: explain (non-)monolithic shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: enable OpenGL 4.5
Marek Olšák [Wed, 15 Feb 2017 02:04:01 +0000 (03:04 +0100)]
radeonsi/gfx9: enable OpenGL 4.5

Tentatively enable it, expecting the scratch buffer support to be done before
the next Mesa release.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st
Marek Olšák [Thu, 20 Apr 2017 11:06:31 +0000 (13:06 +0200)]
radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: add reference counting for shader selectors
Marek Olšák [Thu, 20 Apr 2017 11:04:02 +0000 (13:04 +0200)]
radeonsi: add reference counting for shader selectors

The 2nd shader of merged shaders should take a reference of the 1st shader.
The next commit will do that.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS
Marek Olšák [Sun, 23 Apr 2017 00:53:19 +0000 (02:53 +0200)]
radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: set TES registers for merged ES-GS
Marek Olšák [Sun, 23 Apr 2017 00:48:02 +0000 (02:48 +0200)]
radeonsi/gfx9: set TES registers for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS
Marek Olšák [Wed, 19 Apr 2017 01:24:05 +0000 (03:24 +0200)]
radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS

not implemented yet

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: always compile monolithic ES-GS (asynchronously)
Marek Olšák [Tue, 18 Apr 2017 23:53:35 +0000 (01:53 +0200)]
radeonsi/gfx9: always compile monolithic ES-GS (asynchronously)

In addition to the non-monolithic variant.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: add support for monolithic ES-GS
Marek Olšák [Tue, 18 Apr 2017 23:24:43 +0000 (01:24 +0200)]
radeonsi/gfx9: add support for monolithic ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders
Marek Olšák [Tue, 18 Apr 2017 21:49:07 +0000 (23:49 +0200)]
radeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: select shader parts for non-monolithic ES-GS
Marek Olšák [Wed, 19 Apr 2017 01:37:14 +0000 (03:37 +0200)]
radeonsi/gfx9: select shader parts for non-monolithic ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: add GS prolog support for merged ES-GS
Marek Olšák [Wed, 19 Apr 2017 01:37:04 +0000 (03:37 +0200)]
radeonsi/gfx9: add GS prolog support for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: add VS prolog support for merged ES-GS
Marek Olšák [Wed, 19 Apr 2017 01:36:33 +0000 (03:36 +0200)]
radeonsi/gfx9: add VS prolog support for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS
Marek Olšák [Wed, 19 Apr 2017 01:34:56 +0000 (03:34 +0200)]
radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: store ES outputs to LDS
Marek Olšák [Wed, 19 Apr 2017 01:34:03 +0000 (03:34 +0200)]
radeonsi/gfx9: store ES outputs to LDS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: load GS inputs from LDS
Marek Olšák [Wed, 19 Apr 2017 01:33:03 +0000 (03:33 +0200)]
radeonsi/gfx9: load GS inputs from LDS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: get GS wave ID from the correct input
Marek Olšák [Wed, 19 Apr 2017 01:31:12 +0000 (03:31 +0200)]
radeonsi/gfx9: get GS wave ID from the correct input

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: add the function signature of merged ES-GS
Marek Olšák [Wed, 19 Apr 2017 01:29:44 +0000 (03:29 +0200)]
radeonsi/gfx9: add the function signature of merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: set registers and shader key for merged ES-GS
Marek Olšák [Wed, 19 Apr 2017 01:21:16 +0000 (03:21 +0200)]
radeonsi/gfx9: set registers and shader key for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: add GS user SGPRs
Marek Olšák [Wed, 19 Apr 2017 01:12:55 +0000 (03:12 +0200)]
radeonsi/gfx9: add GS user SGPRs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: rename declare_tess_lds -> declare_lds_as_pointer
Marek Olšák [Wed, 19 Apr 2017 01:17:24 +0000 (03:17 +0200)]
radeonsi: rename declare_tess_lds -> declare_lds_as_pointer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: simplify some shader type conditions
Marek Olšák [Wed, 19 Apr 2017 01:15:52 +0000 (03:15 +0200)]
radeonsi: simplify some shader type conditions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: rename the swizzle parameter of lds_store
Marek Olšák [Wed, 19 Apr 2017 01:13:58 +0000 (03:13 +0200)]
radeonsi: rename the swizzle parameter of lds_store

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: add si_shader::prolog2
Marek Olšák [Fri, 7 Apr 2017 19:38:09 +0000 (21:38 +0200)]
radeonsi: add si_shader::prolog2

For a GS prolog in merged ES-GS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders
Marek Olšák [Sat, 22 Apr 2017 18:07:20 +0000 (20:07 +0200)]
radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: add support for monolithic merged LS-HS
Marek Olšák [Wed, 5 Apr 2017 22:33:45 +0000 (00:33 +0200)]
radeonsi/gfx9: add support for monolithic merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them
Marek Olšák [Tue, 14 Mar 2017 18:35:28 +0000 (19:35 +0100)]
radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>