mesa.git
2 years agov3d: Introduce a DRM shim for calling out to the simulator.
Eric Anholt [Wed, 26 Sep 2018 02:15:45 +0000 (19:15 -0700)]
v3d: Introduce a DRM shim for calling out to the simulator.

The goal is to enable testing of parts of drivers without depending on any
particular kernel version or hardware being present.

Simply set LD_PRELOAD=$PREFIX/lib/libv3d_drm_shim.so in your environment,
and we'll fake a /dev/dri/renderD128 (or whatever the next available node
is) using v3dv3.  That node can then be used with the surfaceless or gbm
EGL platforms.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
2 years agoglsl: report no function instead of empty candidate list
Erik Faye-Lund [Thu, 13 Jun 2019 10:03:27 +0000 (12:03 +0200)]
glsl: report no function instead of empty candidate list

When generating the error message for a missing function error where
all available overloads were missing due to a too low GLSL version, we
used to report something like this:

---8<---
0:224(14): error: no matching function for call to
           `textureCubeLod(samplerCube, vec3, float)'; candidates are:
0:224(14): error: type mismatch
---8<---

This is a pretty confusing error message, and can throw people off when
debugging. So let's instead check if any overload is available before we
decide what to print. This allow us to report something like this
instead:

---8<---
0:224(14): error: no function with name 'textureCubeLod'
0:224(14): error: type mismatch
---8<---

This is arguably easier to understand for programmers, and doesn't send
you on a wild goose chase to figure out what argument is wrong just
because you stopped reading the message prematurely. I'm of course
referring to a friend, not me. For sure. I would never do that.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoradv: Set correct metadata size for GFX9+.
Bas Nieuwenhuizen [Thu, 25 Jul 2019 14:53:34 +0000 (16:53 +0200)]
radv: Set correct metadata size for GFX9+.

Without correct size, radeonsi assumes the metadata is incorrect,
which can and will cause issues.

Since the metadata is really incorrect without the size, let us
fix that.

Fixes: e43cc3e3afc "radv/gfx9: handle GFX9 opaque metadata"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoanv: report HOST_ALLOCATION as supported for images
Arcady Goldmints-Orlov [Tue, 23 Jul 2019 19:36:48 +0000 (14:36 -0500)]
anv: report HOST_ALLOCATION as supported for images

Report VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT as
supported for images. It was being shown supported for buffers, but not
images.

Fixes: 69cc6272fbc1 ("anv: Implement VK_EXT_external_memory_host")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoradv/gfx10: fix intensity formats by setting ALPHA_IS_ON_MSB
Samuel Pitoiset [Wed, 24 Jul 2019 14:50:38 +0000 (16:50 +0200)]
radv/gfx10: fix intensity formats by setting ALPHA_IS_ON_MSB

This fixes
dEQP-VK.rasterization.primitive_size.points.point_size_*

This also fixes some black squares with the Sascha SSAO demo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: use L2 for DMA copy/fill operations
Samuel Pitoiset [Thu, 25 Jul 2019 13:38:51 +0000 (15:38 +0200)]
radv/gfx10: use L2 for DMA copy/fill operations

It's coherent and faster. GFX7-GFX9 should also support this but
for now only uses L2 for GFX10 because it's untested on previous gens.

This fixes dEQP-VK.memory.pipeline_barrier.transfer_*

This also fixes some missing geometry in Dawn Of War III because
VBOs weren't updated correctly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agopan/midgard: Optimize varying projection
Alyssa Rosenzweig [Wed, 24 Jul 2019 22:37:24 +0000 (15:37 -0700)]
pan/midgard: Optimize varying projection

We add a new opt pass fusing perspective projection with varyings. Minor
win..? We don't combine non-varying projections, since if we're too
agressive, the extra load/store traffic will hurt us so it's not really
a win in practice.

total instructions in shared programs: 3915 -> 3913 (-0.05%)
instructions in affected programs: 76 -> 74 (-2.63%)
helped: 1
HURT: 0

total bundles in shared programs: 2520 -> 2519 (-0.04%)
bundles in affected programs: 46 -> 45 (-2.17%)
helped: 1
HURT: 0

total quadwords in shared programs: 4027 -> 4025 (-0.05%)
quadwords in affected programs: 80 -> 78 (-2.50%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add perspective projection recombine pass
Alyssa Rosenzweig [Wed, 24 Jul 2019 03:02:56 +0000 (20:02 -0700)]
pan/midgard: Add perspective projection recombine pass

We don't use it yet, since it's actually a shader-db regression. This is
primarily helpful as an intermediate step for attaching projection to
varyings.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Force perspective ops to use vec4
Alyssa Rosenzweig [Wed, 24 Jul 2019 22:36:46 +0000 (15:36 -0700)]
pan/midgard: Force perspective ops to use vec4

It doesn't make sense to use them with anything less.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add R27-only op handling
Alyssa Rosenzweig [Wed, 24 Jul 2019 21:58:46 +0000 (14:58 -0700)]
pan/midgard: Add R27-only op handling

We use a special conflicting register class.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add OP_R27_ONLY helper
Alyssa Rosenzweig [Wed, 24 Jul 2019 21:52:57 +0000 (14:52 -0700)]
pan/midgard: Add OP_R27_ONLY helper

While load/store ops like st_vary can take an argument in either
r26/r27, ops like those for perspective projection must specifically
take their argument in r27.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Enable RA for st_vary
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:54:59 +0000 (12:54 -0700)]
pan/midgard: Enable RA for st_vary

Now that all the piping is in place to do so without regressions, we
flip on automatic register allocation for varyings. Hooray!

total instructions in shared programs: 4025 -> 3915 (-2.73%)
instructions in affected programs: 1667 -> 1557 (-6.60%)
helped: 62
HURT: 0
helped stats (abs) min: 1 max: 3 x̄: 1.77 x̃: 2
helped stats (rel) min: 0.93% max: 20.00% x̄: 10.80% x̃: 10.64%
95% mean confidence interval for instructions value: -1.89 -1.66
95% mean confidence interval for instructions %-change: -12.50% -9.11%
Instructions are helped.

total bundles in shared programs: 2683 -> 2520 (-6.08%)
bundles in affected programs: 1066 -> 903 (-15.29%)
helped: 62
HURT: 0
helped stats (abs) min: 1 max: 3 x̄: 2.63 x̃: 3
helped stats (rel) min: 2.94% max: 42.86% x̄: 23.85% x̃: 22.50%
95% mean confidence interval for bundles value: -2.83 -2.43
95% mean confidence interval for bundles %-change: -27.73% -19.97%
Bundles are helped.

total quadwords in shared programs: 4192 -> 4027 (-3.94%)
quadwords in affected programs: 1584 -> 1419 (-10.42%)
helped: 62
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 2.66 x̃: 3
helped stats (rel) min: 1.85% max: 30.00% x̄: 16.49% x̃: 16.52%
95% mean confidence interval for quadwords value: -2.87 -2.46
95% mean confidence interval for quadwords %-change: -19.14% -13.84%
Quadwords are helped.

total registers in shared programs: 433 -> 411 (-5.08%)
registers in affected programs: 67 -> 45 (-32.84%)
helped: 23
HURT: 1
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 25.00% max: 50.00% x̄: 41.30% x̃: 50.00%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 14.29% max: 14.29% x̄: 14.29% x̃: 14.29%
95% mean confidence interval for registers value: -1.09 -0.74
95% mean confidence interval for registers %-change: -45.45% -32.52%
Registers are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Remove check for `class`
Alyssa Rosenzweig [Wed, 24 Jul 2019 21:10:12 +0000 (14:10 -0700)]
pan/midgard: Remove check for `class`

Fixes classes defaulting to vec4 in some cases.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Move uniforms to special registers
Alyssa Rosenzweig [Wed, 24 Jul 2019 20:29:36 +0000 (13:29 -0700)]
pan/midgard: Move uniforms to special registers

The load/store pipes can't take a uniform register in, so an explicit
move is necessary here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Emit st_vary registers in install_registers
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:53:58 +0000 (12:53 -0700)]
pan/midgard: Emit st_vary registers in install_registers

Now that we have its registers handled normally like the rest of the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_lower_special_reads helper
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:53:08 +0000 (12:53 -0700)]
pan/midgard: Add mir_lower_special_reads helper

Given the constraints on special registers, we add a helper for lowering
these by inserting moves (copies) where needed to satsify the ISA
constraints.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add emit_explicit_constant helper
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:52:27 +0000 (12:52 -0700)]
pan/midgard: Add emit_explicit_constant helper

We generalize the constant emission helper used in fragment writeout as
we'll also need it for vertex outputs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_rewrite_index_src_tag
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:51:51 +0000 (12:51 -0700)]
pan/midgard: Add mir_rewrite_index_src_tag

Specialized version of a rewrite that only rewrites a certain type of
instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add class check
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:33:26 +0000 (11:33 -0700)]
pan/midgard: Add class check

This ensures the rules for accessing special register classes are
satisfied. This is asserted as a prepass should have lowered offending
uses to something satisfying these rules. Special register classes are
*not* work registers and cannot be used for RMW operations; they are
essentially 1-way pipes straight into/from fixed-function logic in the
shader cores.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Implement class spilling
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:16:48 +0000 (11:16 -0700)]
pan/midgard: Implement class spilling

We reuse the same register spilling mechanism as for work->memory to
spill special->work registers, e.g. to allow writing out more than 2
vec4 varyings (without better scheduling anyway).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Extend liveness analysis to st_vary
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:16:15 +0000 (11:16 -0700)]
pan/midgard: Extend liveness analysis to st_vary

These can consume sources now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Implement load/store register classing
Alyssa Rosenzweig [Wed, 24 Jul 2019 17:03:24 +0000 (10:03 -0700)]
pan/midgard: Implement load/store register classing

This does not yet support special->work spilling, nor does it support
multiclass breakup. These corner cases will be handled in succeeding
commits.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Allocate special register classes
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:31:46 +0000 (08:31 -0700)]
pan/midgard: Allocate special register classes

We'll want to also handle load/store and texture registers in our RA
loop.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Move copy propagation into its own file
Alyssa Rosenzweig [Wed, 24 Jul 2019 14:23:19 +0000 (07:23 -0700)]
pan/midgard: Move copy propagation into its own file

We also expose some utilities it uses as general MIR helpers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_simple_swizzle helper
Alyssa Rosenzweig [Wed, 24 Jul 2019 03:02:06 +0000 (20:02 -0700)]
pan/midgard: Add mir_simple_swizzle helper

Checks for x/xy/xyz/xyzw style swizzles (slightly more general but you
get the idea).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_single_use helper
Alyssa Rosenzweig [Wed, 24 Jul 2019 03:01:44 +0000 (20:01 -0700)]
pan/midgard: Add mir_single_use helper

Helps as an optimization heuristic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Compute I/O counts from shader_info
Alyssa Rosenzweig [Wed, 24 Jul 2019 00:02:38 +0000 (17:02 -0700)]
panfrost: Compute I/O counts from shader_info

...rather than exposing it in the vendored compiler region.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Don't DIY point size/coord fields
Alyssa Rosenzweig [Tue, 23 Jul 2019 23:55:38 +0000 (16:55 -0700)]
panfrost: Don't DIY point size/coord fields

Again, it's in shader_info for us!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Use nir_gather_info information about discards
Alyssa Rosenzweig [Tue, 23 Jul 2019 23:52:40 +0000 (16:52 -0700)]
panfrost: Use nir_gather_info information about discards

No need to track this ourselves!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Use NIR helper invocations info
Alyssa Rosenzweig [Tue, 23 Jul 2019 23:49:37 +0000 (16:49 -0700)]
panfrost: Use NIR helper invocations info

We don't need to guesstimate this ourselves. This will help when we
bringup derivatives.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost/sfbd: Flesh out fragment job
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:39:39 +0000 (08:39 -0700)]
panfrost/sfbd: Flesh out fragment job

We include a zsbuf attachment function based on how the corresponding
MFBD code works, as well as extending cbufs to mipmapped rendering while
we're at it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Disable tiled formats on SFBD systems
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:41:04 +0000 (08:41 -0700)]
panfrost: Disable tiled formats on SFBD systems

Just because we don't have the format codes to render to them yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Move require_sfbd to screen
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:46:15 +0000 (08:46 -0700)]
panfrost: Move require_sfbd to screen

We'll need it to specialize resource creation by chip.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Reserve, but do not upload, shader padding
Alyssa Rosenzweig [Tue, 23 Jul 2019 17:14:46 +0000 (10:14 -0700)]
panfrost: Reserve, but do not upload, shader padding

Fixes invalid read errors reported by valgrind.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agoutil/ra: Add a getter for a node class
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:19:21 +0000 (11:19 -0700)]
util/ra: Add a getter for a node class

Complements the existing getters and the setter for node class. To be
used in the Panfrost RA refactor.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agopanfrost/ci: Update kernel to 5.2
Tomeu Vizoso [Thu, 25 Jul 2019 09:58:08 +0000 (11:58 +0200)]
panfrost/ci: Update kernel to 5.2

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agoegl: Also query modifiers when exporting DMABuf
Nicolas Dufresne [Sun, 14 Jul 2019 18:48:11 +0000 (14:48 -0400)]
egl: Also query modifiers when exporting DMABuf

This fixes eglExportDMABUFImageQueryMESA() so it will report the
modififers of the underlying image. Without this information,
re-importing will likely be broken as it is rare these days that no
modifiers are used.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Fixes: 8f7338f284cdb1fef64c ("egl: add initial EGL_MESA_image_dma_buf_export v2.4")
2 years agomesa: Enable GL_MESA_framebuffer_flip_y for GL 4.3
Heinrich Fink [Tue, 4 Jun 2019 15:19:47 +0000 (17:19 +0200)]
mesa: Enable GL_MESA_framebuffer_flip_y for GL 4.3

Extend MESA_framebuffer_flip_y to be used with OpenGL versions 4.3 and
higher. OpenGL 4.3 adds FramebufferParameteri needed by this extension.

Reviewed-by: Fritz Koenig <frkoenig@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agopanfrost: Don't expose some atomic stuff even with dEQP
Alyssa Rosenzweig [Wed, 24 Jul 2019 02:18:44 +0000 (19:18 -0700)]
panfrost: Don't expose some atomic stuff even with dEQP

Fixes dEQP crashes.

Fixes: 2f93ecd654e ("panfrost: Fake CAPs for dEQP-GLES31")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agogallium: fix windows build from params change.
Dave Airlie [Wed, 24 Jul 2019 23:33:36 +0000 (09:33 +1000)]
gallium: fix windows build from params change.

This is why we can't have nice things. I'm sure there's someway
to do this with {0} but I really don't have time for that.

Fixes: 2631fd3b0bf ("gallivm: rework lp_build_tgsi_soa to take a struct")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2 years agonir/algebraic: add scmp algebraic optimizations
Jonathan Marek [Wed, 24 Jul 2019 17:33:17 +0000 (13:33 -0400)]
nir/algebraic: add scmp algebraic optimizations

When 'x' is the result of a scmp op:

x != 0.0 or x == 1.0: passthrough
x == 0.0 or x != 1.0: invert

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agonir/algebraic: add option to lower fall_equalN/fany_nequalN
Jonathan Marek [Sun, 2 Jun 2019 22:44:49 +0000 (18:44 -0400)]
nir/algebraic: add option to lower fall_equalN/fany_nequalN

Add generic lowerings for fall_equalN/fany_nequalN. These should be optimal
for vec4 backends that doesn't have any special instructions for it, as
long as they support saturate.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agonir/algebraic: add fdot2 optimizations
Jonathan Marek [Fri, 21 Jun 2019 01:56:29 +0000 (21:56 -0400)]
nir/algebraic: add fdot2 optimizations

Add simple fdot2 optimizations that are missing.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agonir/algebraic: add option to lower fdph
Jonathan Marek [Fri, 21 Jun 2019 01:47:16 +0000 (21:47 -0400)]
nir/algebraic: add option to lower fdph

For backends that don't have a 'fdph' instructions

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agonir: replace lower_sincos with algebraic opt
Jonathan Marek [Wed, 8 May 2019 14:26:49 +0000 (10:26 -0400)]
nir: replace lower_sincos with algebraic opt

This version has less ops for the same precision.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2 years agonir/algebraic: allow swizzle in nir_algebraic replace expression
Jonathan Marek [Fri, 21 Jun 2019 01:23:53 +0000 (21:23 -0400)]
nir/algebraic: allow swizzle in nir_algebraic replace expression

This is to allow optimizations in nir_opt_algebraic not otherwise possible

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2 years agogallium/u_transfer_helper: fix assert in RGTC case
Rob Clark [Mon, 22 Jul 2019 21:23:52 +0000 (14:23 -0700)]
gallium/u_transfer_helper: fix assert in RGTC case

Previously we'd hit the unreachable() for uploading RGTC.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agomain: Free memory allocated for gl_bitmap_atlas structure
Yevhenii Kolesnikov [Tue, 23 Jul 2019 15:35:29 +0000 (18:35 +0300)]
main: Free memory allocated for gl_bitmap_atlas structure

Structure itself wasn't freed during context tear-down, causing a
memory leak on iris.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2 years agonir,intel: lower if (cond) demote() to new intrinsic demote_if(cond)
Daniel Schürmann [Thu, 18 Jul 2019 11:39:49 +0000 (13:39 +0200)]
nir,intel: lower if (cond) demote() to new intrinsic demote_if(cond)

This will effectively enable the optimization in anv.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoi965: Use NIR to lower legacy userclipping.
Kenneth Graunke [Sun, 21 May 2017 08:36:14 +0000 (01:36 -0700)]
i965: Use NIR to lower legacy userclipping.

This allows us to drop legacy userclip plane handling in both the vec4
and FS backends, and simplifies a few interfaces.

v2 (Jason Ekstrand):
 - Move brw_nir_lower_legacy_clipping to brw_nir_uniforms.cpp because
   it's i965-specific.
 - Handle adding the params in brw_nir_lower_legacy_clipping
 - Call brw_nir_lower_legacy_clipping from brw_codegen_vs_prog

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoanv: Implement VK_EXT_subgroup_size_control
Jason Ekstrand [Thu, 21 Feb 2019 20:50:10 +0000 (14:50 -0600)]
anv: Implement VK_EXT_subgroup_size_control

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agoanv/pipeline: Plumb pipeline shader stage create flags
Jason Ekstrand [Fri, 22 Feb 2019 21:21:13 +0000 (15:21 -0600)]
anv/pipeline: Plumb pipeline shader stage create flags

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/compiler: Allow for required subgroup sizes
Jason Ekstrand [Tue, 9 Jul 2019 19:28:18 +0000 (14:28 -0500)]
intel/compiler: Allow for required subgroup sizes

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/compiler: Allow for varying subgroup sizes
Jason Ekstrand [Fri, 22 Feb 2019 21:28:24 +0000 (15:28 -0600)]
intel/compiler: Allow for varying subgroup sizes

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir/lower_subgroups: Properly lower masks when subgroup_size == 0
Jason Ekstrand [Thu, 11 Jul 2019 03:20:00 +0000 (22:20 -0500)]
nir/lower_subgroups: Properly lower masks when subgroup_size == 0

Instead of building a constant mask (which depends on knowing the
subgroup size), we build an expression.  Because the pass uses the
nir_shader_lower_instructions helper, subgroup lowering will be run on
any newly emitted instructions as well as the previously existing
instructions.  In particular, if the subgroup size is known, the newly
emitted subgroup_size intrinsic will get turned into a constant and a
later constant folding pass will clean it up.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agovulkan: Update the XML and headers to 1.1.116
Jason Ekstrand [Thu, 4 Jul 2019 20:10:23 +0000 (15:10 -0500)]
vulkan: Update the XML and headers to 1.1.116

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/compiler: Be more conservative about subgroup sizes in GL
Jason Ekstrand [Fri, 22 Feb 2019 16:48:39 +0000 (10:48 -0600)]
intel/compiler: Be more conservative about subgroup sizes in GL

The rules for gl_SubgroupSize in Vulkan require that it be a constant
that can be queried through the API.  However, all GL requires is that
it's a uniform.  Instead of always claiming that the subgroup size in
the shader is 32 in GL like we have to do for Vulkan, claim 8 for
geometry stages, the maximum for fragment shaders, and the actual size
for compute.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/compiler: Lower gl_SubgroupSize in postprocess_nir
Jason Ekstrand [Thu, 21 Feb 2019 21:29:12 +0000 (15:29 -0600)]
intel/compiler: Lower gl_SubgroupSize in postprocess_nir

Instead of lowering the subgroup size so early, wait until we have more
information.  In particular, we're going to want different subgroup
sizes from different stages depending on the API.  We also defer
lowering of subgroup masks because the ge/gt masks require the subgroup
size to generate a subgroup mask.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/nir: Make brw_nir_apply_sampler_key more generic
Jason Ekstrand [Fri, 22 Feb 2019 17:15:21 +0000 (11:15 -0600)]
intel/nir: Make brw_nir_apply_sampler_key more generic

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Add lowering for nir_op_irem and nir_op_imod
Sagar Ghuge [Tue, 16 Apr 2019 06:06:23 +0000 (23:06 -0700)]
nir: Add lowering for nir_op_irem and nir_op_imod

Tested on Gen > 9.

v2: 1) Fix lowering
    2) Keep a consistent i/u order (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agomain: Fix memleaks in mesa_use_program
Yevhenii Kolesnikov [Thu, 11 Jul 2019 10:00:46 +0000 (13:00 +0300)]
main: Fix memleaks in mesa_use_program

Add freeing of SubroutineIndexes to the _mesa_free_shader_state.

Fixes: 4566aaaa5b1 ("mesa/subroutines: start adding per-context
subroutine index support (v1.1)")
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agointel/compiler: don't use a keyword struct for a class fs_reg
Andrii Simiklit [Tue, 23 Jul 2019 11:48:58 +0000 (14:48 +0300)]
intel/compiler: don't use a keyword struct for a class fs_reg

warning: struct 'fs_reg' was previously declared as a class
Fixes: e64be391 ("intel/compiler: generalize the combine constants pass")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
2 years agolima/ppir: fix disassembler temp read/write print
Qiang Yu [Sat, 20 Jul 2019 10:11:07 +0000 (18:11 +0800)]
lima/ppir: fix disassembler temp read/write print

temp read/write use negtive offset, and handle
alignment==1 case.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2 years agogallium+mesa: fix tgsi_semantic array type
Eric Engestrom [Tue, 23 Jul 2019 09:01:44 +0000 (10:01 +0100)]
gallium+mesa: fix tgsi_semantic array type

Fixes: ed23335a313dfc9cec26 ("gallium: use enums in p_shader_tokens.h (v2)")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoutil: fix no-op macro (bad number of arguments)
Eric Engestrom [Tue, 23 Jul 2019 09:03:26 +0000 (10:03 +0100)]
util: fix no-op macro (bad number of arguments)

Fixes: b8e077daee4d6369d774 ("util: no-op __builtin_types_compatible_p() for non-GCC compilers")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoradv/gfx10: enable VK_EXT_transform_feedback
Samuel Pitoiset [Tue, 23 Jul 2019 12:53:34 +0000 (14:53 +0200)]
radv/gfx10: enable VK_EXT_transform_feedback

When a pipeline uses transform feedback, the driver fallbacks to
the legacy path because NGG support for streamout is a non-trivial
amount of work.

AMDVLK also uses the legacy path for streamout, while RadeonSI
uses the new NGG path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: do not enable NGG if a pipeline uses XFB
Samuel Pitoiset [Tue, 23 Jul 2019 13:12:42 +0000 (15:12 +0200)]
radv/gfx10: do not enable NGG if a pipeline uses XFB

NGG GS for streamout requires a bunch of work, so enable it with
the legacy path only for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: emit streamout shader config
Samuel Pitoiset [Tue, 23 Jul 2019 12:55:16 +0000 (14:55 +0200)]
radv/gfx10: emit streamout shader config

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: declare streamout user SGPRs
Samuel Pitoiset [Tue, 23 Jul 2019 12:53:45 +0000 (14:53 +0200)]
radv/gfx10: declare streamout user SGPRs

Required for legacy streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: update streamout descriptors
Samuel Pitoiset [Tue, 23 Jul 2019 08:12:13 +0000 (10:12 +0200)]
radv/gfx10: update streamout descriptors

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: fix VS input VGPRs with the legacy path
Samuel Pitoiset [Tue, 23 Jul 2019 09:52:36 +0000 (11:52 +0200)]
radv/gfx10: fix VS input VGPRs with the legacy path

For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agogallivm: rework lp_build_tgsi_soa to take a struct
Dave Airlie [Mon, 22 Jul 2019 02:04:27 +0000 (12:04 +1000)]
gallivm: rework lp_build_tgsi_soa to take a struct

The parameters were getting messy and I have to add a few more
for compute shaders, so clean it up before proceeding.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2 years agonir/lower_io: Return SSA defs from helpers
Jason Ekstrand [Fri, 19 Jul 2019 20:30:27 +0000 (15:30 -0500)]
nir/lower_io: Return SSA defs from helpers

I can't find a single place where nir_lower_io is called after going out
of SSA which is the only real reason why you wouldn't do this. Returning
SSA defs is more idiomatic and is required for the next commit.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agomeson: allow building all glx without any drivers
Dylan Baker [Mon, 1 Jul 2019 17:04:03 +0000 (10:04 -0700)]
meson: allow building all glx without any drivers

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111016
Fixes: a47c525f3281a2753180e076c7e9b7772aff8f06
       ("meson: build glx")
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoswr/rasterizer: Fix 3D resource copies.
Jan Zielinski [Tue, 23 Jul 2019 10:47:28 +0000 (12:47 +0200)]
swr/rasterizer: Fix 3D resource copies.

Ensure constant attributes stay constant with barycentric interpolation.

Reviewed-by: Alok Hota <alok.hota@intel.com>
2 years agoswr/rasterizer: Fix return type on SIMD8 version of Clamp and Normalize utility functions
Jan Zielinski [Tue, 23 Jul 2019 10:31:35 +0000 (12:31 +0200)]
swr/rasterizer: Fix return type on SIMD8 version of Clamp and Normalize utility functions

Reviewed-by: Alok Hota <alok.hota@intel.com>
2 years agoswr/rasterizer: small formatting changes
Jan Zielinski [Tue, 23 Jul 2019 10:18:03 +0000 (12:18 +0200)]
swr/rasterizer: small formatting changes

Reviewed-by: Alok Hota <alok.hota@intel.com>
2 years agoswr/rasterizer: Adding support for unhandled clipEnable state
Jan Zielinski [Tue, 23 Jul 2019 08:30:47 +0000 (10:30 +0200)]
swr/rasterizer: Adding support for unhandled clipEnable state

Clipping is not correctly handled by the rasterizer - fixing this.

Reviewed-by: Alok Hota <alok.hota@intel.com>
2 years agoradv/gfx10: Enable binning.
Bas Nieuwenhuizen [Sun, 21 Jul 2019 01:40:00 +0000 (03:40 +0200)]
radv/gfx10: Enable binning.

Numbers for Talos:

gfx10 without binning: 77.0 77.7 77.2 77.6
gfx10 with binning: 82.3 82.0 82.7 82.4

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv/gfx10: Implement bin size calculation.
Bas Nieuwenhuizen [Sat, 20 Jul 2019 23:38:13 +0000 (01:38 +0200)]
radv/gfx10: Implement bin size calculation.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv/gfx9: Select between depth/color bins based on area.
Bas Nieuwenhuizen [Fri, 19 Jul 2019 22:58:12 +0000 (00:58 +0200)]
radv/gfx9: Select between depth/color bins based on area.

Mirrors radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv: Generalize binning settings.
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:54:24 +0000 (01:54 +0200)]
radv: Generalize binning settings.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradv/gfx10: Use new scan converter.
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:18:28 +0000 (01:18 +0200)]
radv/gfx10: Use new scan converter.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv: Set FLUSH_ON_BINNING_TRANSITION.
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:48:47 +0000 (01:48 +0200)]
radv: Set FLUSH_ON_BINNING_TRANSITION.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv: Use pbb_allow for framebuffer BREAK_BATCH.
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:10:36 +0000 (01:10 +0200)]
radv: Use pbb_allow for framebuffer BREAK_BATCH.

Ported from radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2 years agoradeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.
Marek Olšák [Tue, 23 Jul 2019 01:20:29 +0000 (21:20 -0400)]
radeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.

This doesn't implement the color buffer load.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agotgsi/scan: add uses_fbfetch
Marek Olšák [Tue, 23 Jul 2019 01:08:48 +0000 (21:08 -0400)]
tgsi/scan: add uses_fbfetch

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: fail if importing a texture with incorrect last_level or samples
Marek Olšák [Mon, 22 Jul 2019 22:07:06 +0000 (18:07 -0400)]
radeonsi: fail if importing a texture with incorrect last_level or samples

v2: don't fail if the texture comes from an incompatible driver.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
2 years agoradeonsi: rewrite si_get_opaque_metadata, also for gfx10 support
Marek Olšák [Mon, 22 Jul 2019 22:03:13 +0000 (18:03 -0400)]
radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: simplify si_get_input_prim and remove incorrect TODO comment
Marek Olšák [Sat, 20 Jul 2019 01:12:43 +0000 (21:12 -0400)]
radeonsi: simplify si_get_input_prim and remove incorrect TODO comment

u_vertices_per_prim(QUADS) is the same as TRIANGLES.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi/gfx10: fix and enable CLEAR_STATE
Marek Olšák [Thu, 18 Jul 2019 03:29:22 +0000 (23:29 -0400)]
radeonsi/gfx10: fix and enable CLEAR_STATE

it was a driver bug.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: stop using info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]
Marek Olšák [Wed, 17 Jul 2019 23:32:12 +0000 (19:32 -0400)]
radeonsi: stop using info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoac/nir: implement nir_op_pack_{us}norm_2x16
Marek Olšák [Wed, 17 Jul 2019 22:54:42 +0000 (18:54 -0400)]
ac/nir: implement nir_op_pack_{us}norm_2x16

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agomesa/st: rewrite src var when lowering tex_src_plane
Pierre-Eric Pelloux-Prayer [Thu, 18 Jul 2019 13:04:05 +0000 (15:04 +0200)]
mesa/st: rewrite src var when lowering tex_src_plane

The assign_extra_samplers() adds the needed extra samplers but they need
to be used in the nir_tex_instr.
Otherwise the plane information is simply lost and all nir_tex_instr use the
same sampler.
Here's an example of the bug:

NIR before st_nir_lower_tex_src_plane:
vec1 32 ssa_8 = load_const (0x00000000 /* 0.000000 */)
vec4 32 ssa_9 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord), ssa_8 (plane)
vec1 32 ssa_10 = load_const (0x00000001 /* 0.000000 */)
vec4 32 ssa_11 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord), ssa_10 (plane)

After:

vec4 32 ssa_9 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord)
vec4 32 ssa_11 = tex ssa_0 (texture_deref), ssa_0 (sampler_deref), ssa_5 (coord)

This fixes the following piglit test for radeonsi + NIR:
  - ext_image_dma_buf_import-sample_nv12
  - ext_image_dma_buf_import-sample_yuv420
  - ext_image_dma_buf_import-sample_yvu420

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2 years agou_blitter: add a msaa parameter to util_blitter_clear
Pierre-Eric Pelloux-Prayer [Mon, 22 Jul 2019 14:14:20 +0000 (16:14 +0200)]
u_blitter: add a msaa parameter to util_blitter_clear

Fixes: ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agou_blitter: enable msaa when dst num samples is > 1
Pierre-Eric Pelloux-Prayer [Mon, 22 Jul 2019 12:02:14 +0000 (14:02 +0200)]
u_blitter: enable msaa when dst num samples is > 1

Commit ea5b7de138b broke some piglit tests on radeonsi (Bonaire hardware).
This commit fixes half of the regression by enabling msaa if the dest surface has
more than 1 sample (instead of hardcoding it to false).

Fixes: ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agonir/gather_info: Look for uses of helper invocations
Jason Ekstrand [Fri, 7 Jun 2019 23:07:46 +0000 (18:07 -0500)]
nir/gather_info: Look for uses of helper invocations

The one obvious omission here is gl_HelperInvocation itself.  However,
the spec doesn't require that we generate then when gl_HelperInvocation
is used, it merely mandates that we report them if they are there.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agonir/gather_info: Move setting uses_64bit out of the switch
Jason Ekstrand [Fri, 7 Jun 2019 23:03:10 +0000 (18:03 -0500)]
nir/gather_info: Move setting uses_64bit out of the switch

Otherwise, as we add things to the switch, we're going to forget and add
some 64-bit op at some point in the future and it'll stop getting
flagged.  There's no reason why we can't do the check for derivatives.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agonir: Add a nir_tex_instr_has_implicit_derivatives helper
Jason Ekstrand [Fri, 7 Jun 2019 22:58:15 +0000 (17:58 -0500)]
nir: Add a nir_tex_instr_has_implicit_derivatives helper

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agonir: Move nir_alu_instr_is_comparison to the ALU section
Jason Ekstrand [Fri, 7 Jun 2019 22:57:35 +0000 (17:57 -0500)]
nir: Move nir_alu_instr_is_comparison to the ALU section

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>