mesa.git
2 years agomeson: add a zlib subproject
Dylan Baker [Thu, 5 Apr 2018 23:14:07 +0000 (16:14 -0700)]
meson: add a zlib subproject

To help windows build

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agoadd a git ignore for subprojects
Dylan Baker [Fri, 6 Apr 2018 21:10:00 +0000 (14:10 -0700)]
add a git ignore for subprojects

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agomeson: don't build glapi_static_check_table on windows
Dylan Baker [Fri, 31 May 2019 23:20:35 +0000 (16:20 -0700)]
meson: don't build glapi_static_check_table on windows

It doesn't compile due to undefined symbols, which are in
libglapi_static, so I don't understand the problem.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agomeson: Make shared-glapi a combo
Dylan Baker [Fri, 31 May 2019 23:16:22 +0000 (16:16 -0700)]
meson: Make shared-glapi a combo

So it can auto off for windows, but on elsewhere.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agomeson: don't try to generate i18n translations on windows
Dylan Baker [Fri, 31 May 2019 23:13:11 +0000 (16:13 -0700)]
meson: don't try to generate i18n translations on windows

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agoglsl/tests: Handle windows \r\n new lines
Dylan Baker [Fri, 31 May 2019 17:13:55 +0000 (10:13 -0700)]
glsl/tests: Handle windows \r\n new lines

Currently the praser for s expressions assumes that newlines will be \n,
resulting in incorrect parsing on windows, where the newline is \r\n.
This patch just adds \r? to the regular expression used to parse the s
expressions, which fixes at 1 test on windows.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agoiris: Fix constant buffer sizes for non-UBOs
Kenneth Graunke [Tue, 10 Sep 2019 16:04:20 +0000 (09:04 -0700)]
iris: Fix constant buffer sizes for non-UBOs

Since the system value refactor, we've accidentally only been setting
cbuf->buffer_size in the UBO case, and not in the uploaded-constants
case.  We use cbuf->buffer_size to fill out the SURFACE_STATE entry,
so it needs to be initialized in both cases.

Fixes: 3b6d787e404 ("iris: move sysvals to their own constant buffer")
2 years agointel: update product names for WHL
Lionel Landwerlin [Tue, 10 Sep 2019 09:45:50 +0000 (12:45 +0300)]
intel: update product names for WHL

Documentation list all of those as "UHD".

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111629
BSpec: 33266
Acked-by: Tapani Pälli <tapani.palli@intel.com>
2 years agoradv/gfx10: declare a LDS symbol for the NGG emit space
Samuel Pitoiset [Tue, 3 Sep 2019 11:01:54 +0000 (13:01 +0200)]
radv/gfx10: declare a LDS symbol for the NGG emit space

This fixes some interactions when NGG GS is enabled. It fixes:

- dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom*
- dEQP-VK.tessellation.geometry_interaction.passthrough.*

For some reasons, using the computed ESGS ring size randomly hangs
with CTS. For now, just use the maximum LDS size for ESGS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: calculate GFX9 GS and GFX10 NGG states before compiling shader variants
Samuel Pitoiset [Tue, 3 Sep 2019 10:46:55 +0000 (12:46 +0200)]
radv: calculate GFX9 GS and GFX10 NGG states before compiling shader variants

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: store the ESGS ring size as part of gfx10_ngg_info
Samuel Pitoiset [Tue, 3 Sep 2019 09:34:42 +0000 (11:34 +0200)]
radv: store the ESGS ring size as part of gfx10_ngg_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: store GFX10 NGG state as part of the shader info
Samuel Pitoiset [Tue, 3 Sep 2019 09:20:54 +0000 (11:20 +0200)]
radv: store GFX10 NGG state as part of the shader info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: store GFX9 GS state as part of the shader info
Samuel Pitoiset [Tue, 3 Sep 2019 09:14:18 +0000 (11:14 +0200)]
radv: store GFX9 GS state as part of the shader info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: fill shader info for all stages in the pipeline
Samuel Pitoiset [Tue, 3 Sep 2019 08:29:19 +0000 (10:29 +0200)]
radv: fill shader info for all stages in the pipeline

This shouldn't be in NIR->LLVM because ACO also needs the shader
info. This will also help for computing some NGG values that are
necessary for declaring LDS symbols.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: do not pass all compiler options to the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 07:49:14 +0000 (09:49 +0200)]
radv: do not pass all compiler options to the shader info pass

Only the pipeline layout and the shader keys are needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeonsi: remove redundant si_texture offset and size fields
Marek Olšák [Thu, 29 Aug 2019 01:27:05 +0000 (21:27 -0400)]
radeonsi: remove redundant si_texture offset and size fields

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: move texture storage allocation outside of radeonsi
Marek Olšák [Wed, 28 Aug 2019 01:18:20 +0000 (21:18 -0400)]
radeonsi: move texture storage allocation outside of radeonsi

possible code sharing with radv

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: move HTILE allocation outside of radeonsi
Marek Olšák [Wed, 28 Aug 2019 01:07:41 +0000 (21:07 -0400)]
radeonsi: move HTILE allocation outside of radeonsi

ac_surface computes it for amdgpu.
radeon_drm_surface computes it for radeon.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: handle NO_DCC early
Marek Olšák [Wed, 28 Aug 2019 00:32:46 +0000 (20:32 -0400)]
radeonsi: handle NO_DCC early

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoac/surface: add RADEON_SURF_NO_FMASK
Marek Olšák [Wed, 28 Aug 2019 00:29:11 +0000 (20:29 -0400)]
ac/surface: add RADEON_SURF_NO_FMASK

This controls FMASK and CMASK computation for MSAA.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agor300,r600,radeonsi: set winsys_handle::stride,offset in drivers, not winsyses
Marek Olšák [Tue, 27 Aug 2019 23:35:25 +0000 (19:35 -0400)]
r300,r600,radeonsi: set winsys_handle::stride,offset in drivers, not winsyses

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agor300,r600,radeonsi: read winsys_handle::stride,offset in drivers, not winsyses
Marek Olšák [Tue, 27 Aug 2019 23:35:25 +0000 (19:35 -0400)]
r300,r600,radeonsi: read winsys_handle::stride,offset in drivers, not winsyses

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi/gfx10: fix wave occupancy computations
Marek Olšák [Wed, 28 Aug 2019 21:38:50 +0000 (17:38 -0400)]
radeonsi/gfx10: fix wave occupancy computations

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: only support at most 1024 threads per block
Marek Olšák [Tue, 27 Aug 2019 21:39:02 +0000 (17:39 -0400)]
radeonsi: only support at most 1024 threads per block

LLVM 10 won't support 2048.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: disable DCC when importing a texture from an incompatible driver
Marek Olšák [Tue, 27 Aug 2019 18:37:24 +0000 (14:37 -0400)]
radeonsi: disable DCC when importing a texture from an incompatible driver

and unify the code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi/gfx10: don't call gfx10_destroy_query with compute-only contexts
Marek Olšák [Fri, 23 Aug 2019 23:17:05 +0000 (19:17 -0400)]
radeonsi/gfx10: don't call gfx10_destroy_query with compute-only contexts

This fixes a crash.

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi/gfx10: use fma for TGSI_OPCODE_FMA
Marek Olšák [Mon, 26 Aug 2019 20:20:44 +0000 (16:20 -0400)]
radeonsi/gfx10: use fma for TGSI_OPCODE_FMA

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoac: use fma on gfx10
Marek Olšák [Mon, 26 Aug 2019 20:19:31 +0000 (16:19 -0400)]
ac: use fma on gfx10

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoac: enable LLVM atomic optimizations
Marek Olšák [Thu, 15 Aug 2019 20:53:34 +0000 (16:53 -0400)]
ac: enable LLVM atomic optimizations

2 years agovirgl: Fix pipe_resource leaks under multi-sample.
Lepton Wu [Tue, 10 Sep 2019 03:42:55 +0000 (03:42 +0000)]
virgl: Fix pipe_resource leaks under multi-sample.

Fixes: 900a80f9e4f ("virgl: virgl_transfer should own its virgl_resource")
Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2 years agoiris: Avoid flushing for cache history on transfer range flushes
Kenneth Graunke [Sun, 8 Sep 2019 05:51:15 +0000 (22:51 -0700)]
iris: Avoid flushing for cache history on transfer range flushes

The VBO module maps a buffer with GL_MAP_FLUSH_EXPLICIT, and keeps
appending data, and calling glFlushMappedBufferRange().  We were
invalidating the VF cache each time it flushed a new range, which
results in a ton of VF flushes.

If the contents of the destination in the target range are undefined
(never even possibly written), this patch makes us assume that it's
likely not in the cache and so cache invalidations are required.  If
the destination range is defined, we continue cache flushing as we may
need to expunge stale data.

This eliminates 88% of the VF cache invalidates on Manhattan 3.0.
Improves performance in Manhattan 3.0 on my Icelake 8x8 with the GPU
frequency locked to 700Mhz by 0.376724% +/- 0.0989183% (n=10).

2 years agoiris: Optimize out redundant sampler state binds
Kenneth Graunke [Sun, 8 Sep 2019 05:30:02 +0000 (22:30 -0700)]
iris: Optimize out redundant sampler state binds

This cuts roughly 85% of the 3DSTATE_SAMPLER_STATE_POINTERS_PS calls in
the J2DBench images test.  For some reason, the state tracker is calling
bind_sampler_state with the same sampler state in a bunch of cases.

2 years agoiris: Add support for the always_flush_cache=true debug option.
Kenneth Graunke [Sun, 8 Sep 2019 04:18:51 +0000 (21:18 -0700)]
iris: Add support for the always_flush_cache=true debug option.

This can be useful for debugging missing flushes.

2 years agomesa: Eliminate gl_config::rgbMode
Adam Jackson [Fri, 6 Sep 2019 16:30:19 +0000 (12:30 -0400)]
mesa: Eliminate gl_config::rgbMode

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: Eliminate gl_config::have{Accum,Depth,Stencil}Buffer
Adam Jackson [Fri, 6 Sep 2019 15:51:23 +0000 (11:51 -0400)]
mesa: Eliminate gl_config::have{Accum,Depth,Stencil}Buffer

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: Remove unused gl_config::indexBits
Adam Jackson [Fri, 6 Sep 2019 15:43:19 +0000 (11:43 -0400)]
mesa: Remove unused gl_config::indexBits

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agogallium/xlib: Fix an obvious thinko
Adam Jackson [Mon, 9 Sep 2019 17:59:34 +0000 (13:59 -0400)]
gallium/xlib: Fix an obvious thinko

x == !GLX_DIRECT_COLOR is a fancy way of writing x == 0, which is
clearly not what was meant.

2 years agoiris: Ignore line stipple information if it's disabled
Kenneth Graunke [Sun, 8 Sep 2019 06:43:05 +0000 (23:43 -0700)]
iris: Ignore line stipple information if it's disabled

The line stipple pattern and factor only matter if line stippling is
actually enabled.  Otherwise, we can safely ignore it.

PBO upload may give us zero for line stipple information, while normal
drawing tends to give us an actual stipple pattern such as 0xffff.  This
was causing us to flag IRIS_DIRTY_LINE_STIPPLE way too often, leading to
useless 3DSTATE_LINE_STIPPLE commands, which are non-pipelined and thus
very expensive.

Improves performance in Manhattan 3.0 on Skylake GT4e by
0.149261% +/- 0.0380796% (n=210).  On an Icelake 8x8 with the GPU
frequency locked at 700Mhz, improves by 0.423756% +/- 0.222843% (n=3).

2 years agolima/ppir: drop fge/flt/feq/fne options
Vasily Khoruzhick [Wed, 4 Sep 2019 05:58:05 +0000 (22:58 -0700)]
lima/ppir: drop fge/flt/feq/fne options

These are supposed to be lowered into sge/slt/seq/sne equivalents.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima: run opt_algebraic between int_to_float and boot_to_float for vs
Vasily Khoruzhick [Wed, 4 Sep 2019 05:55:48 +0000 (22:55 -0700)]
lima: run opt_algebraic between int_to_float and boot_to_float for vs

int_to_float emits ftrunc and ftrunc lowering generates bool ops.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: fix warning in gpir disassembler
Vasily Khoruzhick [Sun, 1 Sep 2019 21:38:08 +0000 (14:38 -0700)]
lima/gpir: fix warning in gpir disassembler

Fixes following warning:

../src/gallium/drivers/lima/ir/gp/disasm.c: In function ‘print_src’:
../src/gallium/drivers/lima/ir/gp/disasm.c:241:20: warning: array subscript 28 is above array bounds of ‘char[5]’ [-Warray-bounds]
  241 |              "xyzw"[src - gpir_codegen_src_attrib_x]);

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: lower fceil
Vasily Khoruzhick [Sun, 1 Sep 2019 21:37:23 +0000 (14:37 -0700)]
lima/gpir: lower fceil

GP doesn't support fceil so we need to lower it.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: Disallow moves for schedule_first nodes
Connor Abbott [Sun, 8 Sep 2019 16:48:35 +0000 (18:48 +0200)]
lima/gpir: Disallow moves for schedule_first nodes

The entire point of schedule_first is that the node has to be scheduled
as soon as possible without any moves because it doesn't produce a
proper floating-point value, or its value changes depending on where you
read it. We were still introducing a move for preexp2 in some cases
though, even if it got scheduled as soon as possible, which broke some
exp() tests. Fix that.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: Fix fake dep handling for schedule_first nodes
Connor Abbott [Sat, 7 Sep 2019 14:40:14 +0000 (16:40 +0200)]
lima/gpir: Fix fake dep handling for schedule_first nodes

The whole point of schedule_first nodes is that they need to be
scheduled as soon as possible, so if a schedule_first node is the
successor in a fake dependency that prevents it from being scheduled
after its parent, that can cause problems. We need to add these fake
dependencies to the parent as well, and we need to guarantee that the
pre-RA scheduler puts schedule_first nodes right before their parents in
order to prevent this from adding cycles to the dependency graph.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: Fix schedule_first insertion logic
Connor Abbott [Mon, 2 Sep 2019 20:31:00 +0000 (22:31 +0200)]
lima/gpir: Fix schedule_first insertion logic

The idea was to make sure schedule_first nodes were always first in the
ready list. I made sure they were inserted first, but not that other
nodes wouldn't later be scheduled ahead of them. Fixes
spec@glsl-1.10@execution@built-in-functions@vs-exp-float and probably
others.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: Ignore unscheduled successors in can_use_complex()
Connor Abbott [Mon, 2 Sep 2019 07:48:54 +0000 (09:48 +0200)]
lima/gpir: Ignore unscheduled successors in can_use_complex()

The point of the function is to avoid creating a complex move which is
used by certain slots in the next instruction, but unscheduled
successors will never be in the next instruction. Found while debugging
a crash that the previous commit fixed.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/gpir: Do all lowerings before rsched
Connor Abbott [Sun, 1 Sep 2019 17:33:06 +0000 (19:33 +0200)]
lima/gpir: Do all lowerings before rsched

The scheduler assumes that load nodes are always duplicated so that they
can always be scheduled eventually and therefore they never need to be
spilled. But some lowerings were running after the pre-RA scheduler,
whereas duplication has to happen before then since it's needed for the
scheduler to do a better job reducing register pressure. This meant
that lowerings were introducing multiple uses of a load instruction,
which broke the scheduler's expectation and resulted in infinite loops
in situations where the only nodes available to spill were load nodes.
Spilling load nodes would be silly, so we want to fix the lowerings
rather than the scheduler. Just do all lowerings before the pre-RA
scheduler, which also helps with reducing pressure since the scheduler
can more accurately compute the pressure.

Fixes lima/mesa#104.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agoandroid: anv: libmesa_vulkan_common: add libmesa_util static dependency
Mauro Rossi [Sun, 8 Sep 2019 15:35:22 +0000 (17:35 +0200)]
android: anv: libmesa_vulkan_common: add libmesa_util static dependency

Change needed to fix the following building error:

In file included from external/mesa/src/intel/vulkan/anv_device.c:43:
external/mesa/src/util/xmlpool.h:115:10: fatal error: 'xmlpool/options.h' file not found
         ^~~~~~~~~~~~~~~~~~~
1 error generated.

Fixes: 4dcb1ff ("anv: add support for driconf")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2 years agopanfrost: Rename pan_bo_cache.c into pan_bo.c
Boris Brezillon [Thu, 5 Sep 2019 19:41:33 +0000 (21:41 +0200)]
panfrost: Rename pan_bo_cache.c into pan_bo.c

So we can move all the BO logic into this file instead of having it
spread over pan_resource.c, pan_drm.c and pan_bo_cache.c.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: Get rid of the now unused SLAB allocator
Boris Brezillon [Thu, 5 Sep 2019 19:41:32 +0000 (21:41 +0200)]
panfrost: Get rid of the now unused SLAB allocator

The last users have been converted to use plain BOs. Let's get rid of
this abstraction. We can always consider adding it back if we need it
at some point.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: Get rid of unused panfrost_context fields
Boris Brezillon [Thu, 5 Sep 2019 19:41:31 +0000 (21:41 +0200)]
panfrost: Get rid of unused panfrost_context fields

Some fields in panfrost_context are unused (probably leftovers from
previous refactor). Let's get rid of them.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: Convert ctx->{scratchpad, tiler_heap, tiler_dummy} to plain BOs
Boris Brezillon [Thu, 5 Sep 2019 19:41:30 +0000 (21:41 +0200)]
panfrost: Convert ctx->{scratchpad, tiler_heap, tiler_dummy} to plain BOs

ctx->{scratchpad,tiler_heap,tiler_dummy} are allocated using
panfrost_drm_allocate_slab() but they never any of the SLAB-based
allocation logic. Let's convert those fields to plain BOs.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: Make transient allocation rely on the BO cache
Boris Brezillon [Thu, 5 Sep 2019 19:41:29 +0000 (21:41 +0200)]
panfrost: Make transient allocation rely on the BO cache

Right now, the transient memory allocator implements its own BO caching
mechanism, which is not really needed since we already have a generic
BO cache. Let's simplify things a bit.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: Stop passing a ctx to functions being passed a batch
Boris Brezillon [Thu, 5 Sep 2019 19:41:28 +0000 (21:41 +0200)]
panfrost: Stop passing a ctx to functions being passed a batch

The context can be retrieved from batch->ctx.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: Pass a batch to panfrost_drm_submit_vs_fs_batch()
Boris Brezillon [Thu, 5 Sep 2019 19:41:27 +0000 (21:41 +0200)]
panfrost: Pass a batch to panfrost_drm_submit_vs_fs_batch()

Given the function name it makes more sense to pass it a job batch
directly.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agopanfrost: s/job/batch/
Boris Brezillon [Thu, 5 Sep 2019 19:41:26 +0000 (21:41 +0200)]
panfrost: s/job/batch/

What we currently call a job is actually a batch containing several jobs
all attached to a rendering operation targeting a specific FBO.

Let's rename structs, functions, variables and fields to reflect this
fact.

Suggested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2 years agoegl: Add GL_MESA_EGL_sync support
Heinrich Fink [Tue, 30 Jul 2019 13:58:20 +0000 (15:58 +0200)]
egl: Add GL_MESA_EGL_sync support

This commit follow OES_EGL_sync to universially enable use of EGL sync
objects with desktop OpenGL contexts.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoheaders: Add GL_MESA_EGL_sync token to GL
Heinrich Fink [Tue, 30 Jul 2019 14:14:07 +0000 (16:14 +0200)]
headers: Add GL_MESA_EGL_sync token to GL

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoregistry: update gl.xml with GL_MESA_EGL_sync token
Heinrich Fink [Tue, 30 Jul 2019 14:12:20 +0000 (16:12 +0200)]
registry: update gl.xml with GL_MESA_EGL_sync token

As added by upstream GL registry changes

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agospecs: Add GL_MESA_EGL_sync
Heinrich Fink [Mon, 29 Jul 2019 14:47:20 +0000 (16:47 +0200)]
specs: Add GL_MESA_EGL_sync

Adds GL_MESA_EGL_sync as defined in upstream OpenGL registry

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoandroid: fix linking issues with liblog
Tapani Pälli [Fri, 6 Sep 2019 05:05:02 +0000 (08:05 +0300)]
android: fix linking issues with liblog

Fixes Android build errors observed in Intel CI.

Fixes: f9f7cbc1aa3 "util: android logging support"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agoiris: Support the disable_throttling=true driconf option.
Kenneth Graunke [Thu, 5 Sep 2019 08:52:17 +0000 (01:52 -0700)]
iris: Support the disable_throttling=true driconf option.

2 years agonir/dead_cf: Repair SSA if the pass makes progress
Jason Ekstrand [Fri, 30 Aug 2019 16:35:26 +0000 (11:35 -0500)]
nir/dead_cf: Repair SSA if the pass makes progress

The dead_cf pass calls into the CF manipulation helpers which attempt to
keep NIR's SSA form sane.  However, when the only break is removed from
a loop, dominance gets messed up anyway because the CF SSA clean-up code
only looks at phis and doesn't consider the case of code becoming
unreachable.  One solution to this would be to put the loop into LCSSA
form before we modify any of its contents.  Another (and the approach
taken by this pass) is to just run the repair_ssa pass afterwards
because the CF manipulation helpers are smart enough to keep all the
use/def stuff sane; they just don't always preserve dominance
properties.

While we're here, we clean up some bogus indentation.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111405
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111069
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir/repair_ssa: Insert deref casts when needed
Jason Ekstrand [Fri, 30 Aug 2019 19:16:07 +0000 (14:16 -0500)]
nir/repair_ssa: Insert deref casts when needed

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir/repair_ssa: Repair dominance for unreachable blocks
Jason Ekstrand [Mon, 2 Sep 2019 17:54:31 +0000 (12:54 -0500)]
nir/repair_ssa: Repair dominance for unreachable blocks

NIR currently assumes that unreachable blocks are trivially dominated by
everything.  However, when considering well-formed SSA, there is no path
from any block to an unreachable block.  Therefore, we can break any
use-def chains where the use is in an unreachable block.  This removes
any dependencies on code created by uses in unreachable blocks and lets
DCE do a better job of cleaning it up.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Add a block_is_unreachable helper
Jason Ekstrand [Mon, 2 Sep 2019 17:53:16 +0000 (12:53 -0500)]
nir: Add a block_is_unreachable helper

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Don't infinitely recurse in lower_ssa_defs_to_regs_block
Jason Ekstrand [Fri, 30 Aug 2019 18:55:02 +0000 (13:55 -0500)]
nir: Don't infinitely recurse in lower_ssa_defs_to_regs_block

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Handle complex derefs in nir_split_array_vars
Jason Ekstrand [Fri, 30 Aug 2019 18:21:00 +0000 (13:21 -0500)]
nir: Handle complex derefs in nir_split_array_vars

We already bail and don't split the vars but we were passing a NULL to
_mesa_hash_table_search which is not allowed.

Fixes: f1cb3348f1 "nir/split_vars: Properly bail in the presence of ..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/blorp: Use wide formats for nicely aligned stencil clears
Jason Ekstrand [Sat, 3 Feb 2018 17:12:15 +0000 (09:12 -0800)]
intel/blorp: Use wide formats for nicely aligned stencil clears

In the case where the stencil clear is nicely aligned, we can clear
stencil much more efficiently by mapping it as a wide format (say
RGBA32_UINT) and blasting out the stencil clear value with a repclear.
On Unigine Heaven, this makes one stencil clear go from non-trivial to
unnoticeable when looking at per-draw timings.

In order for this change to work properly, ANV needs to do a bit more
flushing around depth and stencil clears.  i965 and iris already have
the cache tracking logic to handle this so no changes are required
there.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/blorp: Expose surf_fake_interleaved_msaa internally
Jason Ekstrand [Sun, 1 Sep 2019 14:07:38 +0000 (09:07 -0500)]
intel/blorp: Expose surf_fake_interleaved_msaa internally

2 years agointel/blorp: Expose surf_retile_w_to_y internally
Jason Ekstrand [Sat, 3 Feb 2018 19:46:04 +0000 (11:46 -0800)]
intel/blorp: Expose surf_retile_w_to_y internally

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoblorp: Memset surface info to zero when initializing it
Jason Ekstrand [Sat, 31 Aug 2019 04:57:52 +0000 (23:57 -0500)]
blorp: Memset surface info to zero when initializing it

This isn't known to fix any current bugs but it does prevent a
regression in a subsequent commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/tools: Decode PS kernels on SNB
Jason Ekstrand [Sat, 31 Aug 2019 19:11:49 +0000 (14:11 -0500)]
intel/tools: Decode PS kernels on SNB

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNB
Jason Ekstrand [Sat, 31 Aug 2019 19:02:15 +0000 (14:02 -0500)]
intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNB

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agonir/lower_io_to_vector: don't merge compact varyings
Rhys Perry [Fri, 6 Sep 2019 20:38:57 +0000 (21:38 +0100)]
nir/lower_io_to_vector: don't merge compact varyings

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 02bc4aabb48 ('nir/lower_io_to_vector: allow FS outputs to be vectorized')
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agodrirc: override minImageCount=2 for gfxbench
Eric Engestrom [Thu, 29 Aug 2019 23:23:01 +0000 (00:23 +0100)]
drirc: override minImageCount=2 for gfxbench

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110765
Fixes: 4689e98fe884d9412b72 ("vulkan/wsi: Set X11 minImageCount to 3.")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoradv: add support for vk_x11_override_min_image_count
Eric Engestrom [Thu, 29 Aug 2019 22:52:52 +0000 (23:52 +0100)]
radv: add support for vk_x11_override_min_image_count

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoamd: move adaptive sync to performance section, as it is defined in xmlpool
Eric Engestrom [Fri, 30 Aug 2019 16:03:12 +0000 (17:03 +0100)]
amd: move adaptive sync to performance section, as it is defined in xmlpool

Fixes: 3844ed8d44677588bc29 ("radv: Add adaptive_sync driconfig option and enable it by default.")
Fixes: e260493f2ab2483e5a55 ("radeonsi: Enable adaptive_sync by default for radeon")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: add support for vk_x11_override_min_image_count
Eric Engestrom [Thu, 29 Aug 2019 22:55:29 +0000 (23:55 +0100)]
anv: add support for vk_x11_override_min_image_count

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agowsi: add minImageCount override
Eric Engestrom [Thu, 29 Aug 2019 22:49:29 +0000 (23:49 +0100)]
wsi: add minImageCount override

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: add support for driconf
Eric Engestrom [Wed, 24 Apr 2019 15:42:25 +0000 (16:42 +0100)]
anv: add support for driconf

No option is supported yet, this is just the boilerplate.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agogallivm: drop LLVM<3.3 code paths as no build system allows that
Eric Engestrom [Tue, 3 Sep 2019 21:40:32 +0000 (22:40 +0100)]
gallivm: drop LLVM<3.3 code paths as no build system allows that

Suggested-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agomeson/scons/android: drop now-unused HAVE_LLVM
Eric Engestrom [Tue, 27 Aug 2019 23:58:18 +0000 (00:58 +0100)]
meson/scons/android: drop now-unused HAVE_LLVM

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agollvmpipe: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR
Eric Engestrom [Tue, 27 Aug 2019 23:36:37 +0000 (00:36 +0100)]
llvmpipe: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoclover: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR
Eric Engestrom [Tue, 27 Aug 2019 23:36:45 +0000 (00:36 +0100)]
clover: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agogallivm: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR
Eric Engestrom [Tue, 27 Aug 2019 23:36:25 +0000 (00:36 +0100)]
gallivm: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoclover: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:07:00 +0000 (00:07 +0100)]
clover: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agogallivm: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:06:21 +0000 (00:06 +0100)]
gallivm: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoswr: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:06:45 +0000 (00:06 +0100)]
swr: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoamd: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:06:03 +0000 (00:06 +0100)]
amd: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agosvga: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
Eric Engestrom [Tue, 27 Aug 2019 22:59:14 +0000 (23:59 +0100)]
svga: replace binary HAVE_LLVM checks with LLVM_AVAILABLE

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agor600: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
Eric Engestrom [Tue, 27 Aug 2019 22:58:57 +0000 (23:58 +0100)]
r600: replace binary HAVE_LLVM checks with LLVM_AVAILABLE

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoaux/draw: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
Eric Engestrom [Tue, 27 Aug 2019 22:56:55 +0000 (23:56 +0100)]
aux/draw: replace binary HAVE_LLVM checks with LLVM_AVAILABLE

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agomeson/scons/android: add LLVM_AVAILABLE binary flag
Eric Engestrom [Tue, 27 Aug 2019 23:56:24 +0000 (00:56 +0100)]
meson/scons/android: add LLVM_AVAILABLE binary flag

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agogallivm: replace `0x` version print with actual version string
Eric Engestrom [Tue, 27 Aug 2019 22:54:52 +0000 (23:54 +0100)]
gallivm: replace `0x` version print with actual version string

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoanv,iris: L3ALLOC register replaces L3CNTLREG for gen12
Jordan Justen [Wed, 13 Dec 2017 04:24:57 +0000 (20:24 -0800)]
anv,iris: L3ALLOC register replaces L3CNTLREG for gen12

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agointel/gen12: Add L3 configurations
Anuj Phogat [Sat, 5 Jan 2019 00:04:07 +0000 (16:04 -0800)]
intel/gen12: Add L3 configurations

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoutil: include u_endian.h in u_math.h
Rhys Perry [Thu, 5 Sep 2019 19:51:30 +0000 (20:51 +0100)]
util: include u_endian.h in u_math.h

u_endian.h needs to be included, otherwise PIPE_ARCH_BIG_ENDIAN might not
be defined on big-endian architectures and the endian conversion macros
will be incorrect.

I don't think anything is broken because of this, I just noticed this when
looking at the file.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoanv: Bump maxComputeWorkgroupSize
Jason Ekstrand [Tue, 3 Sep 2019 15:00:23 +0000 (10:00 -0500)]
anv: Bump maxComputeWorkgroupSize

Fixes: 9a129510f56f "anv: Bump maxComputeWorkgroupInvocations"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111552
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel: Stop redirecting state cache to command streamer cache section
Kenneth Graunke [Sat, 31 Aug 2019 00:00:22 +0000 (17:00 -0700)]
intel: Stop redirecting state cache to command streamer cache section

This bit redirects the state cache from the unified/RO sections of the
L3 cache to the "CS command buffer" section of the cache, which would
be set up via TCCNTLREG.  The documentation says:

   "Additionaly, this redirection should be enabled only if there is a
    non-zero allocation for the CS command buffer section."

We don't allocate any cache to the CS command buffer section, so
enabling this redirection effectively disabled the state cache.
The Windows driver only sets up that section when using POSH, which
we do not currently use.  So, leave it unallocated and disable the
redirection to get a functional state cache again.

Improves performance in Civilization VI by 18%, Manhattan 3.0 by 6%,
and Car Chase by 2%.