mesa.git
4 years agoandroid: amd/addrlib: trivial fix for gfx9 support
Mauro Rossi [Sat, 1 Apr 2017 10:48:44 +0000 (12:48 +0200)]
android: amd/addrlib: trivial fix for gfx9 support

Fixes the following build error:

external/mesa/src/amd/addrlib/gfx9/gfx9addrlib.cpp:36:10: fatal error: 'gfx9_gb_reg.h' file not found
         ^
1 error generated.

Fixes: 7f160ef "amd/addrlib: import gfx9 support"
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agonir: Add GLSL_TYPE_[U]INT64 to some switch statements
Jason Ekstrand [Fri, 14 Apr 2017 21:41:43 +0000 (14:41 -0700)]
nir: Add GLSL_TYPE_[U]INT64 to some switch statements

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agogallium/radeon: always flush asynchronously and wait after begin_new_cs
Marek Olšák [Thu, 13 Apr 2017 21:46:59 +0000 (23:46 +0200)]
gallium/radeon: always flush asynchronously and wait after begin_new_cs

This hides the overhead of everything in the driver after the CS flush and
before returning from pipe_context::flush.
Only microbenchmarks will benefit.

+2% FPS for glxgears.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: remove local variable 'mod' from si_compile_tgsi_shader
Marek Olšák [Wed, 15 Mar 2017 19:50:35 +0000 (20:50 +0100)]
radeonsi: remove local variable 'mod' from si_compile_tgsi_shader

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: add si_shader_selector::vs_needs_prolog
Marek Olšák [Tue, 21 Feb 2017 19:32:51 +0000 (20:32 +0100)]
radeonsi: add si_shader_selector::vs_needs_prolog

cleanup

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: don't set VGT_GS_MODE as part of the GS state
Marek Olšák [Wed, 12 Apr 2017 15:48:16 +0000 (17:48 +0200)]
radeonsi: don't set VGT_GS_MODE as part of the GS state

The VS state sets it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: don't allow user indices with indirect draws
Marek Olšák [Sun, 2 Apr 2017 14:22:54 +0000 (16:22 +0200)]
radeonsi: don't allow user indices with indirect draws

Not possible with GL and it will make future gallium rework easier.
(also it's something I wouldn't like to support)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: merge two if (indirect) statements
Marek Olšák [Sun, 2 Apr 2017 13:27:02 +0000 (15:27 +0200)]
radeonsi: merge two if (indirect) statements

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: don't mark non-dirty textures with CMASK as compressed
Marek Olšák [Fri, 7 Apr 2017 10:36:59 +0000 (12:36 +0200)]
radeonsi: don't mark non-dirty textures with CMASK as compressed

because the compression is skipped with non-dirty textures.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agodocs: Document interaction Fixes tag and stable branches.
Bas Nieuwenhuizen [Fri, 14 Apr 2017 21:39:15 +0000 (23:39 +0200)]
docs: Document interaction Fixes tag and stable branches.

For the next time I forget.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoglsl: don't run the GLSL pre-processor when we are skipping compilation
Timothy Arceri [Mon, 10 Apr 2017 01:48:49 +0000 (11:48 +1000)]
glsl: don't run the GLSL pre-processor when we are skipping compilation

This moves the hashing of shader source for the cache lookup to before
the preprocessor.  In our experience, shaders are unlikely to hash the
same after preprocessing if they didn't hash the same before, so we can
skip preprocessing for cache hits.

Improves Deus Ex start-up times with a warm cache from ~30 seconds to
~22 seconds.

Also fixes the leaking of state.

V2: fix indentation

v3: add the value of MESA_EXTENSION_OVERRIDE to the hash of the shader.

Tested-by (v2): Grazvydas Ignotas <notasas@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agoglsl: delay optimisations on individual shaders when cache is available
Timothy Arceri [Mon, 10 Apr 2017 01:48:48 +0000 (11:48 +1000)]
glsl: delay optimisations on individual shaders when cache is available

Due to a max limit of 65,536 entries on the index table that we use to
decide if we can skip compiling individual shaders, it is very likely
we will have collisions.

To avoid doing too much work when the linked program may be in the
cache this patch delays calling the optimisations until link time.

Improves cold cache start-up times on Deus Ex by ~20 seconds.

When deleting the cache index to simulate a worst case scenario
of collisions in the index, warm cache start-up time improves by
~45 seconds.

V2: fix indentation, make sure to call optimisations on cache
fallback, make sure optimisations get called for XFB.

Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoanv: Add the pci_id into the shader cache UUID
Jason Ekstrand [Sat, 25 Feb 2017 00:36:00 +0000 (16:36 -0800)]
anv: Add the pci_id into the shader cache UUID

This prevents a user from using a cache created on one hardware
generation on a different one.  Of course, with Intel hardware, this
requires moving their drive from one machine to another but it's still
possible and we should prevent it.

Reviewed-by: Chad Versace <chadversary@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
4 years agoetnaviv: native fence fd support
Philipp Zabel [Wed, 12 Apr 2017 10:31:01 +0000 (12:31 +0200)]
etnaviv: native fence fd support

This adds native fence fd support to etnaviv, similarly to commit
0b98e84e9ba0 ("freedreno: native fence fd"), enabled for kernel
driver version 1.1 or later.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agodocs: mark GL_ARB_vertex_attrib_64bit and OpenGL 4.2 as supported by i965/gen7+
Francisco Jerez [Fri, 14 Apr 2017 22:59:52 +0000 (15:59 -0700)]
docs: mark GL_ARB_vertex_attrib_64bit and OpenGL 4.2 as supported by i965/gen7+

v2 (Andreas Boll):
- Mark GL 4.1 as supported by i965/gen7+
- Mark GL_ARB_shader_precision as supported by i965/gen7+
- Update release notes

Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: enable OpenGL 4.2 in Ivybridge
Juan A. Suarez Romero [Wed, 29 Mar 2017 09:41:35 +0000 (11:41 +0200)]
i965: enable OpenGL 4.2 in Ivybridge

Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: enable ARB_shader_precision in gen7+
Samuel Iglesias Gonsálvez [Mon, 17 Oct 2016 14:40:06 +0000 (14:40 +0000)]
i965: enable ARB_shader_precision in gen7+

Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: enable ARB_vertex_attrib_64bit for gen7+
Juan A. Suarez Romero [Fri, 21 Oct 2016 14:57:25 +0000 (16:57 +0200)]
i965: enable ARB_vertex_attrib_64bit for gen7+

Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoswr: Fix swr osmesa build
George Kyriazis [Fri, 14 Apr 2017 18:56:09 +0000 (13:56 -0500)]
swr: Fix swr osmesa build

Use GALLIUM_SWR to standardize

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoetnaviv: SINGLE_BUFFER support on GC3000
Wladimir J. van der Laan [Fri, 14 Apr 2017 07:44:27 +0000 (09:44 +0200)]
etnaviv: SINGLE_BUFFER support on GC3000

This patch adds support for the SINGLE_BUFFER feature on GC3000
GPUs, which allows rendering to a single buffer using multiple pixel
pipes.

This feature is always used when it is available, which means that
multi-tiled formats are no longer being used in that case, and all
buffers will be normal (super)tiled. This mimics the behavior of the
blob on GC3000.

- Because the same format can be used to render to and texture from,
  this avoids an extra resolve pass when rendering to texture.

- i.MX6qp includes a PRE which can scan-out directly from tiled formats,
  avoiding untiling overhead.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoetnaviv: Update includes from rnndb
Wladimir J. van der Laan [Fri, 14 Apr 2017 07:41:03 +0000 (09:41 +0200)]
etnaviv: Update includes from rnndb

Update to etna_viv commit 8486a97.

austriancoder: changed patch to include isa redefinition fix.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoetnaviv: Add chipMinorFeatures4 and 5
Wladimir J. van der Laan [Fri, 14 Apr 2017 07:39:52 +0000 (09:39 +0200)]
etnaviv: Add chipMinorFeatures4 and 5

Request chipMinorFeatures bitfields 4 and 5 from the
drm driver.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoetnaviv: resolve tile status when flushing resource
Philipp Zabel [Wed, 12 Apr 2017 14:13:37 +0000 (16:13 +0200)]
etnaviv: resolve tile status when flushing resource

When passing render buffers from EGL clients to a wayland compositor,
the resource tile status must be resolved because otherwise the tile
status is lost in the transfer and cleared parts of the buffer will
contain old contents.

The same applies when sampling directly from a renderable resource.

lst: Add seqno tracking, to skip flush when not needed.

Fixes: aadcb5e94b35 ("etnaviv: enable TS, but disable autodisable")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoetnaviv: stop repeatedly resolving an unchanged resource into its scanout prime buffer
Philipp Zabel [Wed, 12 Apr 2017 14:13:36 +0000 (16:13 +0200)]
etnaviv: stop repeatedly resolving an unchanged resource into its scanout prime buffer

Before resolving a resource into its scanout prime buffer, check that
the prime resource is actually older. If it is not, the resolve is an
expensive no-op, and we better skip it.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoswr: Add polygon stipple support
George Kyriazis [Sat, 1 Apr 2017 01:09:57 +0000 (20:09 -0500)]
swr: Add polygon stipple support

Add polygon stipple functionality to the fragment shader.

Explicitly turn off polygon stipple for lines and points, since we
do them using tris.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agodocs/relnotes: add GL_ARB_gpu_shader_fp64 support on i965/ivybridge
Samuel Iglesias Gonsálvez [Wed, 5 Apr 2017 04:23:43 +0000 (06:23 +0200)]
docs/relnotes: add GL_ARB_gpu_shader_fp64 support on i965/ivybridge

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
4 years agodocs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+
Samuel Iglesias Gonsálvez [Tue, 11 Oct 2016 08:59:52 +0000 (10:59 +0200)]
docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: enable OpenGL 4.0 to Ivybridge/Baytrail
Samuel Iglesias Gonsálvez [Fri, 26 Aug 2016 05:39:04 +0000 (07:39 +0200)]
i965: enable OpenGL 4.0 to Ivybridge/Baytrail

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail
Samuel Iglesias Gonsálvez [Fri, 26 Aug 2016 05:37:42 +0000 (07:37 +0200)]
i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: Use correct VertStride on align16 instructions.
Matt Turner [Fri, 20 Jan 2017 21:35:33 +0000 (13:35 -0800)]
i965: Use correct VertStride on align16 instructions.

In commit c35fa7a, we changed the "width" of DF source registers to 2,
which is conceptually fine. Unfortunately a VertStride of 2 is not
allowed by align16 instructions on IVB/BYT, and the regular VertStride
of 4 works fine in any case.

See generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-round-double.shader_test
for example:

cmp.ge.f0(8)    g18<1>DF        g1<0>.xyxyDF    -g8<2>DF        { align16 1Q };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed
cmp.ge.f0(8)    g19<1>DF        g1<0>.xyxyDF    -g9<2>DF        { align16 2N };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed

v2:
- Add spec quote (Curro).
- Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro)

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4/dce: improve track of partial flag register writes
Samuel Iglesias Gonsálvez [Fri, 17 Mar 2017 10:57:25 +0000 (11:57 +0100)]
i965/vec4/dce: improve track of partial flag register writes

This is required for correctness in presence of multiple 4-wide flag
writes (e.g. 4-wide instructions with a conditional mod set) which
update a different portion of the same 8-bit flag subregister.

Right now we keep track of flag dataflow with 8-bit granularity and
consider flag writes to have killed any previous definition of the
same subregister even if the write was less than 8 channels wide,
which can cause live flag register updates to be dead
code-eliminated incorrectly.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: don't do horizontal stride on some register file types
Samuel Iglesias Gonsálvez [Fri, 17 Mar 2017 10:55:49 +0000 (11:55 +0100)]
i965/vec4: don't do horizontal stride on some register file types

horiz_offset() shouldn't be doing anything for scalar registers,
because all channels of any SIMD instructions will end up reading or
writing the same component of the register, so shifting the register
offset would be wrong.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Re-implement in terms of is_uniform() for
  simplicity.  Pass argument by const reference.  Clarify commit
  message. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.
Matt Turner [Fri, 20 Jan 2017 21:35:32 +0000 (13:35 -0800)]
i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.

Otherwise for a pack_double_2x32_split opcode, we emit:

   vec1 64 ssa_135 = pack_double_2x32_split ssa_133, ssa_134
mov(8)          g5<1>UD         g5<4>.xUD                       { align16 1Q compacted };
mov(8)          g7<2>UD         g5<4,4,1>UD                     { align1 1Q };
        ERROR: When the destination spans two registers, the source must span two registers
               (exceptions for scalar source and packed-word to packed-dword expansion)
mov(8)          g8<2>UD         g5.4<4,4,1>UD                   { align1 2N };
        ERROR: The offset from the two source registers must be the same
mov(8)          g5<1>UD         g6<4>.xUD                       { align16 1Q compacted };
mov(8)          g7.1<2>UD       g5<4,4,1>UD                     { align1 1Q };
        ERROR: When the destination spans two registers, the source must span two registers
               (exceptions for scalar source and packed-word to packed-dword expansion)
mov(8)          g8.1<2>UD       g5.4<4,4,1>UD                   { align1 2N };
        ERROR: The offset from the two source registers must be the same

The intention was to emit mov(4)s for the instructions that have ERROR
annotations.

See tests/spec/arb_gpu_shader_fp64/execution/vs-isinf-dvec.shader_test
for example.

v2 (Samuel):
- Instead of setting the exec size to a fixed value, don't double it
(Curro).
- Add PICK_{HIGH,LOW}_32BIT to the condition.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Trivial rebase changes. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: use vec4_builder to emit instructions in setup_imm_df()
Samuel Iglesias Gonsálvez [Tue, 7 Mar 2017 09:29:53 +0000 (10:29 +0100)]
i965/vec4: use vec4_builder to emit instructions in setup_imm_df()

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Drop useless vec4_visitor dependencies.  Demote to
  static stand-alone function.  Don't write unused components in the
  result.  Use vec4_builder interface for register allocation. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: consider subregister offset in live variables
Juan A. Suarez Romero [Fri, 23 Sep 2016 15:57:39 +0000 (15:57 +0000)]
i965/vec4: consider subregister offset in live variables

Take into account offset values less than a full register (32 bytes)
when getting the var from register.

This is required when dealing with an operation that writes half of the
register (like one d2x in IVB/BYT, which uses exec_size == 4).

v2:
- Take in account this offset < 32 in liveness analysis too (Curro)

v3:
- Change formula in var_from_reg() (Curro)
- Remove useless changes (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: fix assert to detect SIMD lowered DF instructions in IVB
Francisco Jerez [Wed, 12 Apr 2017 23:54:49 +0000 (16:54 -0700)]
i965/vec4: fix assert to detect SIMD lowered DF instructions in IVB

On IVB, DF instructions have lowered the SIMD width to 4 but the
exec_size will be later doubled. Fix the assert to avoid crashing in
this case.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Simplify assert.  Except for the 'inst->group % 4
  == 0' part the assertion was redundant with the previous assertion. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type
Samuel Iglesias Gonsálvez [Fri, 24 Mar 2017 07:46:13 +0000 (08:46 +0100)]
i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type

This way we can set the destination type as double to all these new opcodes,
avoiding any optimizer's confusion that was happening before.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Drop no_spill workaround originally needed due to
  the bogus destination type of VEC4_OPCODE_FROM_DOUBLE. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: split d2x conversion and data gathering from one opcode to two explicit...
Samuel Iglesias Gonsálvez [Wed, 8 Mar 2017 08:27:49 +0000 (09:27 +0100)]
i965/vec4: split d2x conversion and data gathering from one opcode to two explicit ones

When doing a 64-bit to a smaller data type size conversion, the destination should
be aligned to 64-bits. Because of that, we need to gather the data after the
actual conversion.

Until now, these two operations were done by VEC4_OPCODE_FROM_DOUBLE but
now we split them explicitely in two different instructions:
VEC4_OPCODE_FROM_DOUBLE just do the conversion and
VEC4_OPCODE_PICK_LOW_32BIT will gather the data.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT
Juan A. Suarez Romero [Fri, 23 Sep 2016 09:57:43 +0000 (09:57 +0000)]
i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT

In the generator we must generate slightly different code for
Ivybridge/Baytrail, because of the way the stride works in
this hardware.

v2:
- Use stride and don't need to fix dst (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: keep original type when dealing with null registers
Juan A. Suarez Romero [Mon, 12 Sep 2016 16:06:22 +0000 (16:06 +0000)]
i965/vec4: keep original type when dealing with null registers

Keep the original type when dealing with null registers. Especially
because we do no want to introduce an implicit conversion between
types that could affect the conditional flags.

This affects especially when the original type is DF, and we are working
on Ivybridge/Baytrail.

v2 (Curro)
- Fix typo.
- Use retype() instead of applying the type directly.
- Remove unneeded retype.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/vec4: split DF instructions and later double its execsize in IVB/BYT
Samuel Iglesias Gonsálvez [Mon, 29 Aug 2016 08:10:30 +0000 (10:10 +0200)]
i965/vec4: split DF instructions and later double its execsize in IVB/BYT

We need to split DF instructions in two on IVB/BYT as it needs an
execsize 8 to process 4 DF values (one GRF in total).

v2:
- Rename helper and make it static inline function (Matt).
- Fix indention and add braces (Matt).

v3:
- Don't edit IR instruction when doubling exec_size (Curro)
- Add comment into the code (Curro).
- Manage ARF registers like the others (Curro)

v4:
- Add get_exec_type() function and use it to calculate the execution
  size.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Fix bogus 'type != BAD_FILE' check.  Take
  destination type as execution type where there is no valid source.
  Assert-fail if the deduced execution type is byte.  Clarify comment
  in get_lowered_simd_width().  Move SIMD width workaround outside of
  'if (...inst->size_written > REG_SIZE)' conditional block, since the
  problem should be independent of whether the amount of data written
  by the instruction is greater or lower than a GRF.  Drop redundant
  is_ivb_df definition.  Drop bogus inst->exec_size < 8 check.
  Simplify channel group assertion. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
Samuel Iglesias Gonsálvez [Thu, 25 Aug 2016 14:05:24 +0000 (16:05 +0200)]
i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT

The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: Get 64-bit indirect moves working on IVB.
Francisco Jerez [Thu, 9 Feb 2017 18:16:58 +0000 (10:16 -0800)]
i965/fs: Get 64-bit indirect moves working on IVB.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
4 years agoi965: Use source region <1,2,0> when converting to DF.
Matt Turner [Fri, 13 Jan 2017 02:05:58 +0000 (18:05 -0800)]
i965: Use source region <1,2,0> when converting to DF.

Doing so allows us to use a single MOV in VEC4_OPCODE_TO_DOUBLE instead
of two.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
4 years agoi965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT
Juan A. Suarez Romero [Wed, 3 Aug 2016 11:51:44 +0000 (11:51 +0000)]
i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT

According to the IVB and HSW PRMs:

"2.When the destination requires two registers and the sources are
 indirect, the sources must use 1x1 regioning mode."

So for DF instructions the execution size is not limited by the number
of address registers that are available, but by the EU decompression
logic not handling VxH indirect addressing correctly.

This patch limits the SIMD width to 4 in this case.

v2:
- Fix typo (Matt).
- Fix condition (Curro)

v3:
- Add spec quote (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: fix dst stride in IVB/BYT type conversions
Juan A. Suarez Romero [Fri, 20 Jan 2017 07:50:50 +0000 (08:50 +0100)]
i965/fs: fix dst stride in IVB/BYT type conversions

When converting a DF to 32-bit conversions, we set dst stride to 2,
to fulfill alignment restrictions because the upper Dword of every
Qword will be written with undefined value.

But in IVB/BYT, this is not necessary, as each DF conversion already
writes 2, the first one the real value, and the second one a 0.
That is, IVB/BYT already set stride = 2 implicitly, so we must set it to
1 explicitly to avoid ending up with stride = 4.

v2:
- Fix typo (Matt)

v3:
- Fix stride in the destination's brw_reg, don't modity IR (Curro)

v4:
- Remove 'is_dst' argument of brw_reg_from_fs_reg() (Curro)
- Fix comment (Curro).
- Relax hstride assert (Curro)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Minor spelling fixes. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: rename lower_d2x to lower_conversions
Samuel Iglesias Gonsálvez [Tue, 14 Mar 2017 07:17:36 +0000 (08:17 +0100)]
i965/fs: rename lower_d2x to lower_conversions

v2:
- Change the name to lower_conversions.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoRevert "i965/fs: Don't emit SEL instructions for type-converting MOVs."
Samuel Iglesias Gonsálvez [Tue, 28 Mar 2017 04:25:13 +0000 (06:25 +0200)]
Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs."

This reverts commit 7dccd38b400d3a65da20ddefe282a7bb0b7ccb58.

d2x pass fixes SEL instructions when there is a type conversion
by doing a SEL without type conversion and then convert the result.
This pass also takes into account the non-uniform control flow.

Then, 7dccd38b400d3a65da20ddefe282a7bb0b7ccb58 is not needed anymore.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965/fs: generalize the legalization d2x pass
Samuel Iglesias Gonsálvez [Fri, 20 Jan 2017 07:47:05 +0000 (08:47 +0100)]
i965/fs: generalize the legalization d2x pass

Generalize it to lower any unsupported narrower conversion.

v2 (Curro):
- Add supports_type_conversion()
- Reuse existing intruction instead of cloning it.
- Generalize d2x to narrower and equal size conversions.

v3 (Curro):
- Make supports_type_conversion() const and improve it.
- Use foreach_block_and_inst to process added instructions.
- Simplify code.
- Add assert and improve comments.
- Remove redundant mov.
- Remove useless comment.
- Remove saturate == false assert and add support for saturation
  when fixing the conversion.
- Add get_exec_type() function.

v4 (Curro):
- Use get_exec_type() function to get sources' type.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: Use <0,2,1> region for scalar DF sources on IVB/BYT.
Matt Turner [Wed, 11 Jan 2017 03:33:22 +0000 (19:33 -0800)]
i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.

On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
region, but on IVB and BYT DF regions must be programmed in terms of
floats. A <0,2,1> region accomplishes this.

v2:
- Apply region <0,2,1> in brw_reg_from_fs_reg() (Curro).

v3:
- Added comment explaining the reason (Curro).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: clamp exec_size when an instruction has a scalar DF source
Samuel Iglesias Gonsálvez [Wed, 11 Jan 2017 07:17:57 +0000 (08:17 +0100)]
i965/fs: clamp exec_size when an instruction has a scalar DF source

Then the SIMD lowering pass will get rid of any compressed instructions with scalar
source (whether force_writemask_all or not) and we avoid hitting the Gen7 region
decompression bug.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: double regioning parameters and execsize for DF in IVB/BYT
Juan A. Suarez Romero [Mon, 18 Jul 2016 07:27:56 +0000 (07:27 +0000)]
i965/fs: double regioning parameters and execsize for DF in IVB/BYT

In IVB and BYT, both regioning parameters and execution sizes are measured as
32-bits element size.

So when we have something like:

mov(8) g2<1>DF g3<4,4,1>DF

We are not actually moving 8 doubles (our intention), but 4 doubles.

We need to double the parameters to cope with this issue. However,
horizontal strides don't behave as they're supposed to on IVB
for DF regions, they will cause each 32-bit half of DF sources to be
strided individually, and doubling the value won't make any difference.

v2:
- Use devinfo directly (Matt).
- Use Baytrail instead of Valleview (Matt).
- Use IvyBridge instead of Ivy (Matt)
- Double the exec_size in code emission (Curro)

v3:
- Change hstride doubling by an assert and fix commit log (Curro).
- Substitute remaining compiler->devinfo by devinfo (Curro).

v4:
- Fix comment (Curro).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965/fs: add helper to retrieve instruction execution type
Juan A. Suarez Romero [Mon, 18 Jul 2016 07:17:39 +0000 (07:17 +0000)]
i965/fs: add helper to retrieve instruction execution type

The execution data size is the biggest type size of any instruction
operand.

We will use it to know if the instruction deals with DF, because in Ivy
we need to double the execution size and regioning parameters.

v2:
- Fix typo in commit log (Matt)
- Use static inline function instead of fs_inst's method (Curro).
- Define the result as a constant (Curro).
- Fix indentation (Matt).
- Add braces to nested control flow (Matt).

v3 (Curro):
- Add get_exec_type() and other auxiliary functions and use them to
  calculate its size.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Fix bogus 'type != BAD_FILE' check.  Fix deduced
  execution type for integer vector types.  Take destination type as
  execution type where there is no valid source.  Assert-fail if the
  deduced execution type is byte.  Move into brw_ir_fs.h header for
  consistency with the VEC4 back-end. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agoi965: Handle IVB DF differences in the validator.
Matt Turner [Fri, 20 Jan 2017 21:35:31 +0000 (13:35 -0800)]
i965: Handle IVB DF differences in the validator.

On IVB/BYT, region parameters and execution size for DF are in terms of
32-bit elements, so they are doubled. For evaluating the validity of an
instruction, we halve them.

v2 (Sam):
- Add comments.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
4 years agoi965/disasm: also print nibctrl in IVB for execsize=8
Iago Toral Quiroga [Fri, 22 Jul 2016 11:36:25 +0000 (13:36 +0200)]
i965/disasm: also print nibctrl in IVB for execsize=8

4-wide DF operations where NibCtrl applies require and execsize of 8
in IvyBridge/BayTrail.

v2:
- Refactor NibCtrl printing (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agonir: Destination component count of shader_clock intrinsic is 2
Boyan Ding [Wed, 12 Apr 2017 13:14:22 +0000 (21:14 +0800)]
nir: Destination component count of shader_clock intrinsic is 2

This fixes the following error when using ARB_shader_clock on i965:
vec1 32 ssa_0 = intrinsic shader_clock () () ()
intrinsic store_var (ssa_0) (clock_retval) (3) /* wrmask=xy */
error: src->ssa->num_components == num_components (nir/nir_validate.c:204)

Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
4 years agoradeonsi: add missing initialization for userptr buffers
Nicolai Hähnle [Wed, 12 Apr 2017 15:05:56 +0000 (17:05 +0200)]
radeonsi: add missing initialization for userptr buffers

Fix the accounting for memory usage of userptr buffers, which has been wrong
forever (or at least for a long time).

Also initialize flags. Without this initialization, the sparse buffer flag
might end up being set, which leads to staging buffers being used unnecessarily
(and incorrectly) in transfers to or from userptr buffers.

This works around VM faults that occur with the radeon kernel module when
running piglit ./bin/amd_pinned_memory decrement-offset map-buffer -auto

Fixes: e077c5fe6579 ("gallium/radeon: transfers and invalidation for sparse buffers")
Reported-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradv: remove the temp descriptor set infrastructure
Fredrik Höglund [Thu, 13 Apr 2017 22:27:00 +0000 (00:27 +0200)]
radv: remove the temp descriptor set infrastructure

It is no longer used.

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: use push descriptors in meta
Fredrik Höglund [Thu, 13 Apr 2017 22:26:59 +0000 (00:26 +0200)]
radv: use push descriptors in meta

Use push descriptors instead of temp descriptor sets.

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: add private push descriptors for meta
Fredrik Höglund [Thu, 13 Apr 2017 22:26:58 +0000 (00:26 +0200)]
radv: add private push descriptors for meta

This allows meta to use push descriptors without disturbing user
push descriptors.

radv_meta_push_descriptor_set differs from vkCmdPushDescriptorSetKHR
in that partial updates are not supported; all descriptors used in
subsequent draw commands must be pushed at the same time.

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoanv/blorp: Properly handle VK_ATTACHMENT_UNUSED
Jason Ekstrand [Thu, 6 Apr 2017 21:15:55 +0000 (14:15 -0700)]
anv/blorp: Properly handle VK_ATTACHMENT_UNUSED

The Vulkan driver was originally written under the assumption that
VK_ATTACHMENT_UNUSED was basically just for depth-stencil attachments.
However, the way things fell together, VK_ATTACHMENT_UNUSED can be used
anywhere in the subpass description.  The blorp-based clear and resolve
code has a bunch of places where we walk lists of attachments and we
weren't handling VK_ATTACHMENT_UNUSED everywhere.  This commit should
fix all of them.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
4 years agoanv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSED
Jason Ekstrand [Fri, 7 Apr 2017 17:33:25 +0000 (10:33 -0700)]
anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSED

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
4 years agoanv/cmd_buffer: Always set up a null surface state
Jason Ekstrand [Fri, 7 Apr 2017 17:31:01 +0000 (10:31 -0700)]
anv/cmd_buffer: Always set up a null surface state

We're about to start requiring it in yet another case and calculating
exactly when one is needed is starting to get prohibitively expensive.
A single surface state doesn't take up that much space so we may as well
create one all the time.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
4 years agoradeonsi: cope with missing disassembly
Nicolai Hähnle [Fri, 31 Mar 2017 11:03:03 +0000 (13:03 +0200)]
radeonsi: cope with missing disassembly

For robustness and testing purposes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agogallium/ddebug: dump missing members of pipe_draw_info
Nicolai Hähnle [Fri, 7 Apr 2017 14:14:52 +0000 (16:14 +0200)]
gallium/ddebug: dump missing members of pipe_draw_info

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: enable ARB_shader_viewport_layer_array
Nicolai Hähnle [Thu, 13 Apr 2017 20:16:26 +0000 (22:16 +0200)]
radeonsi: enable ARB_shader_viewport_layer_array

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agoradeonsi: handle ignored LAYER and VIEWPORT_INDEX writes
Nicolai Hähnle [Thu, 13 Apr 2017 20:14:20 +0000 (22:14 +0200)]
radeonsi: handle ignored LAYER and VIEWPORT_INDEX writes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agost/mesa: enable ARB_shader_viewport_layer_array
Nicolai Hähnle [Thu, 13 Apr 2017 19:47:00 +0000 (21:47 +0200)]
st/mesa: enable ARB_shader_viewport_layer_array

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agotgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}
Nicolai Hähnle [Thu, 13 Apr 2017 20:13:55 +0000 (22:13 +0200)]
tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}

Depending on pipe caps they can be writable in all vertex processing
stages, but only the output of the last stage counts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agogallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
Nicolai Hähnle [Thu, 13 Apr 2017 19:54:54 +0000 (21:54 +0200)]
gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agoconfigure.ac: add --enable-sanitize option
Nicolai Hähnle [Mon, 3 Apr 2017 09:17:48 +0000 (11:17 +0200)]
configure.ac: add --enable-sanitize option

Enable code sanitizers by adding -fsanitize=$foo flags for the compiler
and linker.

In addition, this also disables checking for undefined symbols: running
the address sanitizer requires additional symbols which should be provided
by a preloaded libasan.so (preloaded for hooking into malloc & friends
globally), and the undefined symbols check gets tripped up by that.

Running the tests works normally via `make check`, but shows additional
failures with the address sanitizer due to memory leaks that seem to be
mostly leaks in the tests themselves. I believe those failures should
really be fixed. In the mean-time, you can set

export ASAN_OPTIONS=detect_leaks=0

to only check for more serious error types.

v2:
- fail reasonably when an unsupported sanitize flag is given (Eric Engestrom)

Reviewed-by: Bartosz Tomczyk <bartosz.tomczyk86@gmail.com> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoanv/cmd_buffer: Flush the VF cache at the top of all primaries
Jason Ekstrand [Fri, 31 Mar 2017 22:33:39 +0000 (15:33 -0700)]
anv/cmd_buffer: Flush the VF cache at the top of all primaries

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
4 years agoanv/blorp: Flush the texture cache in UpdateBuffer
Jason Ekstrand [Fri, 31 Mar 2017 22:33:51 +0000 (15:33 -0700)]
anv/blorp: Flush the texture cache in UpdateBuffer

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
4 years agoanv: Limit VkDeviceMemory objects to 2GB
Jason Ekstrand [Tue, 11 Apr 2017 15:33:19 +0000 (08:33 -0700)]
anv: Limit VkDeviceMemory objects to 2GB

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
4 years agointel/blorp: Add a blorp_emit_dynamic macro
Jason Ekstrand [Sat, 10 Sep 2016 21:15:51 +0000 (14:15 -0700)]
intel/blorp: Add a blorp_emit_dynamic macro

This makes it much easier to throw together a bit of dynamic state.  It
also automatically handles flushing so you don't accidentally forget.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agoswr: Enable MSAA in OpenSWR software renderer
Bruce Cherniak [Thu, 13 Apr 2017 22:40:11 +0000 (17:40 -0500)]
swr: Enable MSAA in OpenSWR software renderer

This patch enables multisample antialiasing in the OpenSWR software renderer.

MSAA is a proof-of-concept/work-in-progress with bug fixes and performance
on the way.  We wanted to get the changes out now to allow several customers
to begin experimenting with MSAA in a software renderer.  So as not to
impact current customers, MSAA is turned off by default - previous
functionality and performance remain intact.  It is easily enabled via
environment variables, as described below.

It has only been tested with the glx-lib winsys.  The intention is to
enable other state-trackers, both Windows and Linux and more fully support
FBOs.

There are 2 environment variables that affect behavior:

* SWR_MSAA_FORCE_ENABLE - force MSAA on, for apps that are not designed
  for MSAA... Beware, results will vary.  This is mainly for testing.

* SWR_MSAA_MAX_SAMPLE_COUNT - sets maximum supported number of
  samples (1,2,4,8,16), or 0 to disable MSAA altogether.
  (The default is currently 0.)

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
4 years agoswr: Removed unnecessary PIPE_BIND flags from swr_is_format_supported
Bruce Cherniak [Wed, 12 Apr 2017 23:53:01 +0000 (18:53 -0500)]
swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supported

Removed unnecessary and probably wrong PIPE_BIND_SCANOUT and PIPE_BIND_SHARED
flags in favor of check on single PIPE_BIND_DISPLAY_TARGET flag.

Reference llvmpipe change <bee4c7718a3bd57e3d99f0913d9081cd13fe5fd>

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
4 years agoswr: Align swr_context allocation to SIMD alignment.
Bruce Cherniak [Wed, 12 Apr 2017 23:43:25 +0000 (18:43 -0500)]
swr: Align swr_context allocation to SIMD alignment.

The context now contains SIMD vectors which must be aligned (specifically
samplePositions in the rastState in the derived state).  Failure to align
can result in segv crash on unaligned memory access in vector
instructions.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
4 years agoswr: update gallium driver docs
Tim Rowley [Thu, 13 Apr 2017 18:10:18 +0000 (13:10 -0500)]
swr: update gallium driver docs

v2: add back scons section, mention additional built swr libraries

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoradv: remove irrelevant comment
Grazvydas Ignotas [Fri, 14 Apr 2017 16:54:35 +0000 (19:54 +0300)]
radv: remove irrelevant comment

A leftover from anv.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: report timestampPeriod correctly
Grazvydas Ignotas [Fri, 14 Apr 2017 17:00:26 +0000 (20:00 +0300)]
radv: report timestampPeriod correctly

The kernel returns frequency in kHz, so to convert to nanosecond
interval that Vulkan uses the dividend should be 1000000.0 and not
100000.0.

This fixes the GPU graph in DOOM and matches the amdgpu-pro blob.

Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agonir/print: add compute shader info
Rob Clark [Thu, 6 Apr 2017 15:56:23 +0000 (11:56 -0400)]
nir/print: add compute shader info

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agogallium/docs: small correction about register files for atomics
Rob Clark [Wed, 12 Apr 2017 15:47:22 +0000 (11:47 -0400)]
gallium/docs: small correction about register files for atomics

These can operate on MEMORY[], in addition to BUFFER[] and IMAGE[]

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agofreedreno: enable draw/batch reordering by default
Rob Clark [Fri, 7 Apr 2017 14:02:53 +0000 (10:02 -0400)]
freedreno: enable draw/batch reordering by default

Probably should have flipped the switch a long time ago, since it
doesn't seem to cause any problems and is a nice perf boost in a number
of cases.

Signed-off-by: Rob Clark <robdclark@gmail.com>
4 years agofreedreno/ir3: small re-order
Rob Clark [Wed, 5 Apr 2017 20:02:36 +0000 (16:02 -0400)]
freedreno/ir3: small re-order

Small re-order of switch statement to handled op-code categories in
order.

Signed-off-by: Rob Clark <robdclark@gmail.com>
4 years agofreedreno/ir3: move 'keeps' to block level
Rob Clark [Wed, 5 Apr 2017 00:29:53 +0000 (20:29 -0400)]
freedreno/ir3: move 'keeps' to block level

For things like SSBOs and atomics we'll want to track this at a block
level.

Signed-off-by: Rob Clark <robdclark@gmail.com>
4 years agofreedreno/ir3: convert dynamic arrays to ralloc
Rob Clark [Wed, 5 Apr 2017 00:22:57 +0000 (20:22 -0400)]
freedreno/ir3: convert dynamic arrays to ralloc

Want to move one of these under ir3_block, so that gives a reason to
migrate the remaining malloc/realloc to ralloc.

Signed-off-by: Rob Clark <robdclark@gmail.com>
4 years agoswr: add linux to scons build
George Kyriazis [Thu, 13 Apr 2017 13:44:08 +0000 (08:44 -0500)]
swr: add linux to scons build

Make swr compile for both linux and windows.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
4 years agoradv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.
Bas Nieuwenhuizen [Thu, 13 Apr 2017 21:49:00 +0000 (23:49 +0200)]
radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.

v2: Also convert the calculations.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
4 years agodocs: Update MESA_shader_integer_functions spec to version 3.
Kenneth Graunke [Thu, 13 Apr 2017 16:28:10 +0000 (09:28 -0700)]
docs: Update MESA_shader_integer_functions spec to version 3.

When publishing this spec on the OpenGL ES registry, Jon Leech noticed
that it didn't actually mention what the ES dependencies and
interactions were.  I looked at extensions_table.h and noted that we
expose it in ES 3.0 contexts, and he added the obvious spec texts.

The updated copy also contains our official extension number.

https://github.com/KhronosGroup/OpenGL-Registry/issues/3

Acked-by: Matt Turner <mattst88@gmail.com>
4 years agoradv: Set descriptor set limits.
Bas Nieuwenhuizen [Thu, 13 Apr 2017 20:34:33 +0000 (22:34 +0200)]
radv: Set descriptor set limits.

Properly and with comments this time.

Signed-off-by: Bas Nieuwenhuizen <bansi@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agoradv: Increase integer sizes in descriptor sets.
Bas Nieuwenhuizen [Thu, 13 Apr 2017 20:18:35 +0000 (22:18 +0200)]
radv: Increase integer sizes in descriptor sets.

Needed if we want to allow them taking more than 64 KiB. The calculations
of these already used 32 bits.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agoradv: support S8_UINT as a depth/stencil format.
Dave Airlie [Thu, 13 Apr 2017 19:34:26 +0000 (05:34 +1000)]
radv: support S8_UINT as a depth/stencil format.

This enables a bunch of NotSupported CTS tests.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agoradv: bump maxGeometryShaderInvocations.
Dave Airlie [Thu, 13 Apr 2017 19:28:52 +0000 (05:28 +1000)]
radv: bump maxGeometryShaderInvocations.

This bumps it to the same level as amdgpu-pro, it also
moves a bunch of dEQP-VK.geometry.instanced.* from
NotSupported to Pass.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agost/nine: Fix support for ps 1.4 dw and dz modifiers
Axel Davy [Sun, 26 Mar 2017 20:57:15 +0000 (22:57 +0200)]
st/nine: Fix support for ps 1.4 dw and dz modifiers

RCP was used incorrectly to support NINED3DSPSM_DW and
NINED3DSPSM_DZ. src.x was used as input instead of src.w
or src.z.

Fixes: https://github.com/iXit/Mesa-3D/issues/271
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
4 years agoclover: Add missing include to compat header
Jan Vesely [Thu, 13 Apr 2017 16:20:21 +0000 (12:20 -0400)]
clover: Add missing include to compat header

Fixes build failure with LLVM 4

Fixes: a981e68c26dc4079a335101da0033185030207f6
(clover: Fix build against clang SVN >= r299965)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
4 years agogallium/radeon: never use staging buffers with AMD_pinned_memory
Nicolai Hähnle [Wed, 12 Apr 2017 10:41:05 +0000 (12:41 +0200)]
gallium/radeon: never use staging buffers with AMD_pinned_memory

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
4 years agoradeonsi: fix gl_BaseVertex in non-indexed draws
Nicolai Hähnle [Wed, 12 Apr 2017 09:01:19 +0000 (11:01 +0200)]
radeonsi: fix gl_BaseVertex in non-indexed draws

gl_BaseVertex is supposed to be 0 in non-indexed draws. Unfortunately, the
way they're implemented, the VGT always generates indices starting at 0,
and the VS prolog adds the start index.

There's a VGT_INDX_OFFSET register which causes the VGT to start at a
driver-defined index. However, this register cannot be written from
indirect draws.

So fix this unlikely case by setting a bit to tell the VS whether the
draw is indexed or not, so that gl_BaseVertex can be adjusted accordingly
when used.

Fixes a bug in
KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters.*

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: provide VS_STATE input to all VS variants
Nicolai Hähnle [Wed, 12 Apr 2017 08:46:22 +0000 (10:46 +0200)]
radeonsi: provide VS_STATE input to all VS variants

v2: fix incorrect change in get_tcs_out_patch_stride

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoradeonsi: change the bit-packing of LS out/TCS in data
Nicolai Hähnle [Wed, 12 Apr 2017 08:16:07 +0000 (10:16 +0200)]
radeonsi: change the bit-packing of LS out/TCS in data

Avoid conflicts when merging various VS state bits.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>