mesa.git
2 years agoheaders: Add GL_MESA_EGL_sync token to GL
Heinrich Fink [Tue, 30 Jul 2019 14:14:07 +0000 (16:14 +0200)]
headers: Add GL_MESA_EGL_sync token to GL

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoregistry: update gl.xml with GL_MESA_EGL_sync token
Heinrich Fink [Tue, 30 Jul 2019 14:12:20 +0000 (16:12 +0200)]
registry: update gl.xml with GL_MESA_EGL_sync token

As added by upstream GL registry changes

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agospecs: Add GL_MESA_EGL_sync
Heinrich Fink [Mon, 29 Jul 2019 14:47:20 +0000 (16:47 +0200)]
specs: Add GL_MESA_EGL_sync

Adds GL_MESA_EGL_sync as defined in upstream OpenGL registry

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoandroid: fix linking issues with liblog
Tapani Pälli [Fri, 6 Sep 2019 05:05:02 +0000 (08:05 +0300)]
android: fix linking issues with liblog

Fixes Android build errors observed in Intel CI.

Fixes: f9f7cbc1aa3 "util: android logging support"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agoiris: Support the disable_throttling=true driconf option.
Kenneth Graunke [Thu, 5 Sep 2019 08:52:17 +0000 (01:52 -0700)]
iris: Support the disable_throttling=true driconf option.

2 years agonir/dead_cf: Repair SSA if the pass makes progress
Jason Ekstrand [Fri, 30 Aug 2019 16:35:26 +0000 (11:35 -0500)]
nir/dead_cf: Repair SSA if the pass makes progress

The dead_cf pass calls into the CF manipulation helpers which attempt to
keep NIR's SSA form sane.  However, when the only break is removed from
a loop, dominance gets messed up anyway because the CF SSA clean-up code
only looks at phis and doesn't consider the case of code becoming
unreachable.  One solution to this would be to put the loop into LCSSA
form before we modify any of its contents.  Another (and the approach
taken by this pass) is to just run the repair_ssa pass afterwards
because the CF manipulation helpers are smart enough to keep all the
use/def stuff sane; they just don't always preserve dominance
properties.

While we're here, we clean up some bogus indentation.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111405
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111069
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir/repair_ssa: Insert deref casts when needed
Jason Ekstrand [Fri, 30 Aug 2019 19:16:07 +0000 (14:16 -0500)]
nir/repair_ssa: Insert deref casts when needed

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir/repair_ssa: Repair dominance for unreachable blocks
Jason Ekstrand [Mon, 2 Sep 2019 17:54:31 +0000 (12:54 -0500)]
nir/repair_ssa: Repair dominance for unreachable blocks

NIR currently assumes that unreachable blocks are trivially dominated by
everything.  However, when considering well-formed SSA, there is no path
from any block to an unreachable block.  Therefore, we can break any
use-def chains where the use is in an unreachable block.  This removes
any dependencies on code created by uses in unreachable blocks and lets
DCE do a better job of cleaning it up.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Add a block_is_unreachable helper
Jason Ekstrand [Mon, 2 Sep 2019 17:53:16 +0000 (12:53 -0500)]
nir: Add a block_is_unreachable helper

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Don't infinitely recurse in lower_ssa_defs_to_regs_block
Jason Ekstrand [Fri, 30 Aug 2019 18:55:02 +0000 (13:55 -0500)]
nir: Don't infinitely recurse in lower_ssa_defs_to_regs_block

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agonir: Handle complex derefs in nir_split_array_vars
Jason Ekstrand [Fri, 30 Aug 2019 18:21:00 +0000 (13:21 -0500)]
nir: Handle complex derefs in nir_split_array_vars

We already bail and don't split the vars but we were passing a NULL to
_mesa_hash_table_search which is not allowed.

Fixes: f1cb3348f1 "nir/split_vars: Properly bail in the presence of ..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2 years agointel/blorp: Use wide formats for nicely aligned stencil clears
Jason Ekstrand [Sat, 3 Feb 2018 17:12:15 +0000 (09:12 -0800)]
intel/blorp: Use wide formats for nicely aligned stencil clears

In the case where the stencil clear is nicely aligned, we can clear
stencil much more efficiently by mapping it as a wide format (say
RGBA32_UINT) and blasting out the stencil clear value with a repclear.
On Unigine Heaven, this makes one stencil clear go from non-trivial to
unnoticeable when looking at per-draw timings.

In order for this change to work properly, ANV needs to do a bit more
flushing around depth and stencil clears.  i965 and iris already have
the cache tracking logic to handle this so no changes are required
there.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/blorp: Expose surf_fake_interleaved_msaa internally
Jason Ekstrand [Sun, 1 Sep 2019 14:07:38 +0000 (09:07 -0500)]
intel/blorp: Expose surf_fake_interleaved_msaa internally

2 years agointel/blorp: Expose surf_retile_w_to_y internally
Jason Ekstrand [Sat, 3 Feb 2018 19:46:04 +0000 (11:46 -0800)]
intel/blorp: Expose surf_retile_w_to_y internally

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoblorp: Memset surface info to zero when initializing it
Jason Ekstrand [Sat, 31 Aug 2019 04:57:52 +0000 (23:57 -0500)]
blorp: Memset surface info to zero when initializing it

This isn't known to fix any current bugs but it does prevent a
regression in a subsequent commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/tools: Decode PS kernels on SNB
Jason Ekstrand [Sat, 31 Aug 2019 19:11:49 +0000 (14:11 -0500)]
intel/tools: Decode PS kernels on SNB

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNB
Jason Ekstrand [Sat, 31 Aug 2019 19:02:15 +0000 (14:02 -0500)]
intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNB

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agonir/lower_io_to_vector: don't merge compact varyings
Rhys Perry [Fri, 6 Sep 2019 20:38:57 +0000 (21:38 +0100)]
nir/lower_io_to_vector: don't merge compact varyings

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 02bc4aabb48 ('nir/lower_io_to_vector: allow FS outputs to be vectorized')
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agodrirc: override minImageCount=2 for gfxbench
Eric Engestrom [Thu, 29 Aug 2019 23:23:01 +0000 (00:23 +0100)]
drirc: override minImageCount=2 for gfxbench

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110765
Fixes: 4689e98fe884d9412b72 ("vulkan/wsi: Set X11 minImageCount to 3.")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoradv: add support for vk_x11_override_min_image_count
Eric Engestrom [Thu, 29 Aug 2019 22:52:52 +0000 (23:52 +0100)]
radv: add support for vk_x11_override_min_image_count

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoamd: move adaptive sync to performance section, as it is defined in xmlpool
Eric Engestrom [Fri, 30 Aug 2019 16:03:12 +0000 (17:03 +0100)]
amd: move adaptive sync to performance section, as it is defined in xmlpool

Fixes: 3844ed8d44677588bc29 ("radv: Add adaptive_sync driconfig option and enable it by default.")
Fixes: e260493f2ab2483e5a55 ("radeonsi: Enable adaptive_sync by default for radeon")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: add support for vk_x11_override_min_image_count
Eric Engestrom [Thu, 29 Aug 2019 22:55:29 +0000 (23:55 +0100)]
anv: add support for vk_x11_override_min_image_count

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agowsi: add minImageCount override
Eric Engestrom [Thu, 29 Aug 2019 22:49:29 +0000 (23:49 +0100)]
wsi: add minImageCount override

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: add support for driconf
Eric Engestrom [Wed, 24 Apr 2019 15:42:25 +0000 (16:42 +0100)]
anv: add support for driconf

No option is supported yet, this is just the boilerplate.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agogallivm: drop LLVM<3.3 code paths as no build system allows that
Eric Engestrom [Tue, 3 Sep 2019 21:40:32 +0000 (22:40 +0100)]
gallivm: drop LLVM<3.3 code paths as no build system allows that

Suggested-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agomeson/scons/android: drop now-unused HAVE_LLVM
Eric Engestrom [Tue, 27 Aug 2019 23:58:18 +0000 (00:58 +0100)]
meson/scons/android: drop now-unused HAVE_LLVM

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agollvmpipe: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR
Eric Engestrom [Tue, 27 Aug 2019 23:36:37 +0000 (00:36 +0100)]
llvmpipe: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoclover: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR
Eric Engestrom [Tue, 27 Aug 2019 23:36:45 +0000 (00:36 +0100)]
clover: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agogallivm: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR
Eric Engestrom [Tue, 27 Aug 2019 23:36:25 +0000 (00:36 +0100)]
gallivm: replace more complex 3.x version check with LLVM_VERSION_MAJOR/MINOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoclover: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:07:00 +0000 (00:07 +0100)]
clover: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agogallivm: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:06:21 +0000 (00:06 +0100)]
gallivm: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoswr: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:06:45 +0000 (00:06 +0100)]
swr: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoamd: replace major llvm version checks with LLVM_VERSION_MAJOR
Eric Engestrom [Tue, 27 Aug 2019 23:06:03 +0000 (00:06 +0100)]
amd: replace major llvm version checks with LLVM_VERSION_MAJOR

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agosvga: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
Eric Engestrom [Tue, 27 Aug 2019 22:59:14 +0000 (23:59 +0100)]
svga: replace binary HAVE_LLVM checks with LLVM_AVAILABLE

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agor600: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
Eric Engestrom [Tue, 27 Aug 2019 22:58:57 +0000 (23:58 +0100)]
r600: replace binary HAVE_LLVM checks with LLVM_AVAILABLE

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoaux/draw: replace binary HAVE_LLVM checks with LLVM_AVAILABLE
Eric Engestrom [Tue, 27 Aug 2019 22:56:55 +0000 (23:56 +0100)]
aux/draw: replace binary HAVE_LLVM checks with LLVM_AVAILABLE

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agomeson/scons/android: add LLVM_AVAILABLE binary flag
Eric Engestrom [Tue, 27 Aug 2019 23:56:24 +0000 (00:56 +0100)]
meson/scons/android: add LLVM_AVAILABLE binary flag

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agogallivm: replace `0x` version print with actual version string
Eric Engestrom [Tue, 27 Aug 2019 22:54:52 +0000 (23:54 +0100)]
gallivm: replace `0x` version print with actual version string

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2 years agoanv,iris: L3ALLOC register replaces L3CNTLREG for gen12
Jordan Justen [Wed, 13 Dec 2017 04:24:57 +0000 (20:24 -0800)]
anv,iris: L3ALLOC register replaces L3CNTLREG for gen12

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agointel/gen12: Add L3 configurations
Anuj Phogat [Sat, 5 Jan 2019 00:04:07 +0000 (16:04 -0800)]
intel/gen12: Add L3 configurations

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoutil: include u_endian.h in u_math.h
Rhys Perry [Thu, 5 Sep 2019 19:51:30 +0000 (20:51 +0100)]
util: include u_endian.h in u_math.h

u_endian.h needs to be included, otherwise PIPE_ARCH_BIG_ENDIAN might not
be defined on big-endian architectures and the endian conversion macros
will be incorrect.

I don't think anything is broken because of this, I just noticed this when
looking at the file.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoanv: Bump maxComputeWorkgroupSize
Jason Ekstrand [Tue, 3 Sep 2019 15:00:23 +0000 (10:00 -0500)]
anv: Bump maxComputeWorkgroupSize

Fixes: 9a129510f56f "anv: Bump maxComputeWorkgroupInvocations"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111552
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel: Stop redirecting state cache to command streamer cache section
Kenneth Graunke [Sat, 31 Aug 2019 00:00:22 +0000 (17:00 -0700)]
intel: Stop redirecting state cache to command streamer cache section

This bit redirects the state cache from the unified/RO sections of the
L3 cache to the "CS command buffer" section of the cache, which would
be set up via TCCNTLREG.  The documentation says:

   "Additionaly, this redirection should be enabled only if there is a
    non-zero allocation for the CS command buffer section."

We don't allocate any cache to the CS command buffer section, so
enabling this redirection effectively disabled the state cache.
The Windows driver only sets up that section when using POSH, which
we do not currently use.  So, leave it unallocated and disable the
redirection to get a functional state cache again.

Improves performance in Civilization VI by 18%, Manhattan 3.0 by 6%,
and Car Chase by 2%.

2 years agoiris: Invalidate state/texture/constant caches after STATE_BASE_ADDRESS
Kenneth Graunke [Tue, 3 Sep 2019 22:34:54 +0000 (15:34 -0700)]
iris: Invalidate state/texture/constant caches after STATE_BASE_ADDRESS

Jason pointed out that the caches likely refer to offsets from dynamic
and surface state base addresses, so when we change those, we need to
invalidate the caches.

Comment borrowed from src/intel/vulkan/genX_cmd_buffer.c.

2 years agofreedreno/a6xx: Implement primitive count queries on GPU
Kristian H. Kristensen [Thu, 5 Sep 2019 22:12:23 +0000 (15:12 -0700)]
freedreno/a6xx: Implement primitive count queries on GPU

The driver can't determine PIPE_QUERY_PRIMITIVES_GENERATED or
PIPE_QUERY_PRIMITIVES_EMITTED once we support geometry or
tessellation, since these stages add primitives at runtime.  Use the
WRITE_PRIMITIVE_COUNTS event to write back the primitive counts and
implement a hw query for this.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agofreedreno/a6xx: Let the GPU track streamout offsets
Kristian H. Kristensen [Thu, 5 Sep 2019 22:07:55 +0000 (15:07 -0700)]
freedreno/a6xx: Let the GPU track streamout offsets

The GPU writes out streamout offsets as it goes to the FLUSH_BASE
pointer.  We use that value with CP_MEM_TO_REG when appending to the
stream so that we don't have to track the offsets with the CPU in the
driver.  This ensures that streamout continues to work once we enable
geometry and tessellation shader stages that add geometry.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2 years agollvmpipe: fix CALLOC vs. free mismatches
Roland Scheidegger [Fri, 6 Sep 2019 02:12:06 +0000 (04:12 +0200)]
llvmpipe: fix CALLOC vs. free mismatches

Should fix some issues we're seeing. And use REALLOC instead of realloc.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2 years agoradv/gfx10: determine the number of vertices per primitive for TES
Samuel Pitoiset [Thu, 5 Sep 2019 10:19:22 +0000 (12:19 +0200)]
radv/gfx10: determine the number of vertices per primitive for TES

This doesn't fix anything known but it's correct now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agonir/lower_io_to_vector: add flat mode
Rhys Perry [Fri, 17 May 2019 14:04:39 +0000 (15:04 +0100)]
nir/lower_io_to_vector: add flat mode

This has lower_io_to_vector try to turn variables into arrays of 4-sized
vectors when possible and fall back to the old approach when that isn't
possible.

This is so that lower_io_to_vector can guarantee that only one variable is
used for each fragment shader output.

v2: handle dual-source blending
v3: don't try to merge structs and non-32-bit types in get_flat_type()
v3: fix per-vertex inputs
v3: fix and cleanup location advancement in get_flat_type() and it's
    calling code
v4: prioritize the original mode over the flat mode
v4: don't create flat variables to merge only one variable
v5: don't skip an entire slot when encountering structs in the old mode

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agonir/lower_io_to_vector: allow FS outputs to be vectorized
Rhys Perry [Fri, 17 May 2019 10:53:32 +0000 (11:53 +0100)]
nir/lower_io_to_vector: allow FS outputs to be vectorized

v2: handle dual-source blending
v3: use a higher MAX_SLOTS

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agoradv/gfx10: make use the output usage mask when exporting NGG GS params
Samuel Pitoiset [Fri, 6 Sep 2019 08:34:35 +0000 (10:34 +0200)]
radv/gfx10: make use the output usage mask when exporting NGG GS params

It shouldn't matter much because output varyings should have been
compacted during NIR shader linking but it mirrors what the driver
does when emitting NGG GS vertex parameters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: account for the subpass view for the NGG GS storage
Samuel Pitoiset [Fri, 6 Sep 2019 08:32:13 +0000 (10:32 +0200)]
radv/gfx10: account for the subpass view for the NGG GS storage

If the fragment shader needs the layer index, we have to allocate
one more dword in the NGG GS storage. Found by inspection. This
doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agopanfrost/ci: Increase timeouts
Tomeu Vizoso [Fri, 6 Sep 2019 14:17:26 +0000 (16:17 +0200)]
panfrost/ci: Increase timeouts

Sometimes LAVA jobs will timeout due to transient issues, and the Gitlab
job will fail in that case. Increase the timeouts to reduce the
likeliness of that happening and reduce false positives.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2 years agopanfrost/ci: Use special runner for LAVA jobs
Tomeu Vizoso [Fri, 6 Sep 2019 13:56:01 +0000 (15:56 +0200)]
panfrost/ci: Use special runner for LAVA jobs

So repositories don't need to be specially configured with a token to
access LAVA, store this token in a bind volume for a special runner.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2 years agopanfrost/ci: Re-add support for armhf
Tomeu Vizoso [Mon, 2 Sep 2019 06:33:11 +0000 (08:33 +0200)]
panfrost/ci: Re-add support for armhf

Now that Volt supports armhf, build again images and submit to LAVA for
RK3288.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2 years agoradv: calculate esgs_itemsize in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 16:20:07 +0000 (18:20 +0200)]
radv: calculate esgs_itemsize in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: calculate the GSVS vertex size in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 16:16:33 +0000 (18:16 +0200)]
radv: calculate the GSVS vertex size in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: gather primitive ID in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 16:12:33 +0000 (18:12 +0200)]
radv: gather primitive ID in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: gather layer in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 16:09:00 +0000 (18:09 +0200)]
radv: gather layer in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: gather viewport in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 16:05:25 +0000 (18:05 +0200)]
radv: gather viewport in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: gather pointsize in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 16:04:43 +0000 (18:04 +0200)]
radv: gather pointsize in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: gather clip/cull distances in the shader info pass
Samuel Pitoiset [Tue, 3 Sep 2019 15:55:02 +0000 (17:55 +0200)]
radv: gather clip/cull distances in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: move ac_fill_shader_info() to radv_nir_shader_info_pass()
Samuel Pitoiset [Tue, 3 Sep 2019 15:48:07 +0000 (17:48 +0200)]
radv: move ac_fill_shader_info() to radv_nir_shader_info_pass()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: merge radv_shader_variant_info into radv_shader_info
Samuel Pitoiset [Tue, 3 Sep 2019 15:39:23 +0000 (17:39 +0200)]
radv: merge radv_shader_variant_info into radv_shader_info

Having two different structs is useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradeon: Fix mjpeg issue for ARCTURUS
Zhu, James [Wed, 4 Sep 2019 17:59:39 +0000 (17:59 +0000)]
radeon: Fix mjpeg issue for ARCTURUS

ARCTURUS mjpeg is using direct register access.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
2 years agoradeon/vcn: add RENOIR VCN decode support
Leo Liu [Wed, 4 Sep 2019 17:27:02 +0000 (13:27 -0400)]
radeon/vcn: add RENOIR VCN decode support

It has same VCN2.x block as Navi1x

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
2 years agoglsl: Fix unroll of do{} while(false) like loops
Danylo Piliaiev [Thu, 22 Aug 2019 10:32:50 +0000 (13:32 +0300)]
glsl: Fix unroll of do{} while(false) like loops

For loops which condition is false on the first iteration
iteration count was falsely calculated under the assumption
that loop's condition is true until it becomes false, meaning
it's true at least one time.
Now such loops are reported as having 0 iteration.

Similar to the fix e71fc7f2 done in NIR.

Fixes tests/shaders/glsl-fs-loop-while-false-02.shader_test

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2 years agotgsi_to_nir: Remove dependency on libglsl.
Timur Kristóf [Wed, 4 Sep 2019 13:56:09 +0000 (16:56 +0300)]
tgsi_to_nir: Remove dependency on libglsl.

This commit removes the GLSL dependency in TTN by manually recording
the textures used and calling nir_lower_samplers
instead of its GL counterpart.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agonir: Carve out nir_lower_samplers from GLSL code.
Timur Kristóf [Wed, 28 Aug 2019 20:34:14 +0000 (22:34 +0200)]
nir: Carve out nir_lower_samplers from GLSL code.

Lowering samplers is needed to produce NIR that can actually be
consumed by some gallium drivers, so it doesn't make sense to
to keep it only in the GLSL code.

This commit introduces nir_lower_samplers to compiler/nir,
while maintains the GL-specific function too.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agoradeonsi: Release storage for smda_uploads when the context is destroyed
Gert Wollny [Tue, 3 Sep 2019 17:24:09 +0000 (19:24 +0200)]
radeonsi: Release storage for smda_uploads when the context is destroyed

This fixes a memory leak in the flush code:

Direct leak of 128 byte(s) in 1 object(s) allocated from:
    #0 in __interceptor_realloc .../gcc-8.3.0/libsanitizer/asan/asan_malloc_linux.cc:105
    #1 in si_buffer_do_flush_region src/gallium/drivers/radeonsi/si_buffer.c:573
    #2 in si_buffer_flush_region src/gallium/drivers/radeonsi/si_buffer.c:608
    #3 in si_buffer_flush_region src/gallium/drivers/radeonsi/si_buffer.c:597

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoandroid: mesa: revert "Enable asm unconditionally"
Mauro Rossi [Sun, 14 Jul 2019 08:53:19 +0000 (10:53 +0200)]
android: mesa: revert "Enable asm unconditionally"

This patch partially reverts 20294dc ("mesa: Enable asm unconditionally, ...")

Android makefile build logic needs to disable assembler optimization
in 32bit builds to avoid text relocations for libglapi.so shared

Fixes the following build error with Android x86 32bit target:

[  0% 4/477] target SharedLib: libglapi (out/target/product/x86/obj/SHARED_LIBRARIES/libglapi_intermediates/LINKED/libglapi.so)
FAILED: out/target/product/x86/obj/SHARED_LIBRARIES/libglapi_intermediates/LINKED/libglapi.so
...
prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/x86_64-linux-android/bin/ld: warning: shared library text segment is not shareable
prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/x86_64-linux-android/bin/ld: error: treating warnings as errors
clang-6.0: error: linker command failed with exit code 1 (use -v to see invocation)

Fixes: 20294dc ("mesa: Enable asm unconditionally, now that gen_matypes is gone.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2 years agoradv/gfx10: always set ballot_mask_bits to 64
Samuel Pitoiset [Tue, 27 Aug 2019 07:01:02 +0000 (09:01 +0200)]
radv/gfx10: always set ballot_mask_bits to 64

The codegen handles it and it adds the correct casts. This fixes
a bunch of LLVM validation errors when enabling Wave32 for compute.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agonir/lower_explicit_io: Handle 1 bit loads and stores
Caio Marcelo de Oliveira Filho [Wed, 28 Aug 2019 01:32:07 +0000 (18:32 -0700)]
nir/lower_explicit_io: Handle 1 bit loads and stores

Load a 32-bit value then convert to 1-bit.  Convert 1-bit to 32-bit
value, then Store it.

These cases started to appear when we changed Anvil to use derefs for
shared memory.

v2: Use `bit_size` in a couple of places we were missing.  (Jason)
    Reassign `value` instead of `src[0]`.  (Jason)

Fixes: 024a46a4079 ("anv: use derefs for shared memory access")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoRevert "intel/fs: Move the scalar-region conversion to the generator."
Jason Ekstrand [Mon, 2 Sep 2019 03:12:07 +0000 (22:12 -0500)]
Revert "intel/fs: Move the scalar-region conversion to the generator."

This reverts commit c0504569eac5e5c305e9f0c240e248aca9d8891f.  Now that
we're doing interpolation lowering in NIR, we can continue to stride the
FS input registers directly in the brw_fs_nir code like we did before.
This fixes SIMD32 fragment shaders which broke because lower_simd_width
depended on the 0 stride to split PLN instructions correctly.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2 years agointel/fs: Fix FB write inst groups
Jason Ekstrand [Mon, 2 Sep 2019 02:57:05 +0000 (21:57 -0500)]
intel/fs: Fix FB write inst groups

This commit does two things.  First, it simplifies the way we compute
the FB write group bit.  There's no reason to use a ternary because
inst->group / 16 can only be 0 or 1.  Second, it fixes an order-of-
operations bug where the ternary wasn't selecting between (1 << 11) and
0 but between (1 << 11) and 0 | brw_dp_write_desc(...).

Fixes: 0d9648416 "intel/compiler: Use generic SEND for Gen7+ FB writes"
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agolima/ppir: don't lower phis to scalar
Vasily Khoruzhick [Thu, 29 Aug 2019 06:09:38 +0000 (23:09 -0700)]
lima/ppir: don't lower phis to scalar

Utgard PP is vec4 architecture, so lowering phis to scalars
increases instruction count and potentially interferes with
spilling.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agofreedreno/a2xx: formats update
Jonathan Marek [Thu, 5 Sep 2019 02:34:23 +0000 (22:34 -0400)]
freedreno/a2xx: formats update

For render formats, update fd2_pipe2color to only work with HW supported
render formats, and remove the format whitelist is_format_supported. This
patch enables float render formats (which work).

For vertex/texture formats, use a generic function which translates using
the bitsize of the channels. Since we fake support for some vertex formats,
check for these in is_format_supported to avoid enabling them as sampler
formats.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a2xx: fix depth gmem restore
Jonathan Marek [Wed, 4 Sep 2019 19:23:27 +0000 (15:23 -0400)]
freedreno/a2xx: fix depth gmem restore

Use fd_gmem_restore_format() to avoid trying to use unsupported Z24S8/Z16
render formats for gmem restore.

Also apply this change to gmem2mem so it doesn't depend on fd2_pipe2color
working with depth formats.

gmem2mem/mem2gmem also doesn't need to use the swap/swizzle, since dst/src
formats are the same.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a2xx: implement polygon offset
Jonathan Marek [Thu, 5 Sep 2019 21:21:54 +0000 (17:21 -0400)]
freedreno/a2xx: implement polygon offset

Fixes failures in the following deqp tests:
dEQP-GLES2.functional.polygon_offset.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a2xx: fix SRC_ALPHA_SATURATE for alpha blend function
Jonathan Marek [Thu, 5 Sep 2019 02:36:00 +0000 (22:36 -0400)]
freedreno/a2xx: fix SRC_ALPHA_SATURATE for alpha blend function

Fixes failures in the following deqp tests:
dEQP-GLES2.functional.fragment_ops.*src_alpha_saturate*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a2xx: ir2: update register state in scalar insert
Jonathan Marek [Thu, 5 Sep 2019 15:25:07 +0000 (11:25 -0400)]
freedreno/a2xx: ir2: update register state in scalar insert

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a2xx: ir2: fix incorrect instruction reordering
Jonathan Marek [Thu, 5 Sep 2019 15:23:53 +0000 (11:23 -0400)]
freedreno/a2xx: ir2: fix incorrect instruction reordering

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a2xx: ir2: check opcode on the right instruction in export cp
Jonathan Marek [Thu, 5 Sep 2019 15:21:16 +0000 (11:21 -0400)]
freedreno/a2xx: ir2: check opcode on the right instruction in export cp

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a2xx: ir2: fix saturate in cp
Jonathan Marek [Thu, 5 Sep 2019 15:19:21 +0000 (11:19 -0400)]
freedreno/a2xx: ir2: fix saturate in cp

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a2xx: ir2: set lower_fdph
Jonathan Marek [Thu, 5 Sep 2019 15:18:45 +0000 (11:18 -0400)]
freedreno/a2xx: ir2: set lower_fdph

The fdph opcode is not supported.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a2xx: ir2: remove pointcoord y invert
Jonathan Marek [Thu, 5 Sep 2019 15:17:45 +0000 (11:17 -0400)]
freedreno/a2xx: ir2: remove pointcoord y invert

Fixes the following deqp test:
dEQP-GLES2.functional.shaders.builtin_variable.pointcoord

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a2xx: ir2: fix lowering of instructions after float lowering
Jonathan Marek [Wed, 4 Sep 2019 19:18:09 +0000 (15:18 -0400)]
freedreno/a2xx: ir2: fix lowering of instructions after float lowering

Some instructions generated by int/bool float lowering need to be lowered
by opt_algebraic.

Fixes: 43dbd7d6
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agolima/ppir: don't lower vector {b,f}csel to scalar if condition is scalar
Vasily Khoruzhick [Fri, 30 Aug 2019 04:28:36 +0000 (21:28 -0700)]
lima/ppir: don't lower vector {b,f}csel to scalar if condition is scalar

Utgard PP has vector fcsel operation, but its condition is scalar. Add
filtering callback that checks whether {b,f}csel condition is not scalar
to lower {b,f}csel to scalar only in this case.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agonir: allow specifying filter callback in lower_alu_to_scalar
Vasily Khoruzhick [Fri, 30 Aug 2019 04:14:54 +0000 (21:14 -0700)]
nir: allow specifying filter callback in lower_alu_to_scalar

Set of opcodes doesn't have enough flexibility in certain cases. E.g.
Utgard PP has vector conditional select operation, but condition is always
scalar. Lowering all the vector selects to scalar increases instruction
number, so we need a way to filter only those ops that can't be handled
in hardware.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agoutil: android logging support
Rob Clark [Tue, 3 Sep 2019 18:43:40 +0000 (11:43 -0700)]
util: android logging support

In particular, it would be nice for failed debug_assert() msgs to show
up in logcat.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agofreedreno/ir3: allow copy propagation for relative
Rob Clark [Fri, 9 Aug 2019 16:08:20 +0000 (09:08 -0700)]
freedreno/ir3: allow copy propagation for relative

This appears to work fine (with the additional constraint of keeping the
indirect load in the same block that a0.x was loaded).

We can probably lift this restriction on earlier gens after testing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: fix cp cmps.s opt
Rob Clark [Wed, 4 Sep 2019 18:28:26 +0000 (11:28 -0700)]
freedreno/ir3: fix cp cmps.s opt

Need to use ir3_instr_set_address(), otherwise the instruction might not
get added to the indirects table.  This becomes a problem when we turn
on copy propagation for relative accesses, as check_instr() in the sched
pass won't realize there is an indirect consumer of address register
load that is ready to be scheduled.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: assert that only single address
Rob Clark [Mon, 2 Sep 2019 17:08:37 +0000 (10:08 -0700)]
freedreno/ir3: assert that only single address

An instruction can reference only a single address register value.
Add an assert to catch bugs.

Also, address value should also be local to the same block as the
instruction.

(The one spot where changing the instruction address is actually legit
needs to clear the address first.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: fix mad copy propagation special case
Rob Clark [Fri, 30 Aug 2019 21:28:01 +0000 (14:28 -0700)]
freedreno/ir3: fix mad copy propagation special case

After the next patch enabling copy propagation for relative sources,
we'll need to dereference the n'th src in valid_flags(), so we actually
need to swap the sources before calling valid_flags().

But the logic was already a bit cumbersome, so move it into a helper
function.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: fix addr/pred spilling
Rob Clark [Mon, 12 Aug 2019 18:34:18 +0000 (11:34 -0700)]
freedreno/ir3: fix addr/pred spilling

The live_values and use_count was not being properly updated.  This
starts triggering problems with the next patch, where we allow copy
propagation for RELATIV access.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/ir3: cleanup "partially const" ubo srcs
Rob Clark [Thu, 8 Aug 2019 22:09:23 +0000 (15:09 -0700)]
freedreno/ir3: cleanup "partially const" ubo srcs

Move the constant part of the indirect offset into nir intrinsic base.
When we have multiple indirect accesses with different constant offsets,
this lets other opt passes clean up things to use a single address
register value.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agolima/ppir: improve regalloc spill cost calculation
Erico Nunes [Tue, 27 Aug 2019 23:09:12 +0000 (01:09 +0200)]
lima/ppir: improve regalloc spill cost calculation

Now that spilling ops can be inserted into existing instructions, it
makes sense to increase cost to spill registers that would cause the
creation of a new instruction.
Experimental results showed that penalizing too much due to this caused
worse results, however it is beneficial as a tie resolver between
registers with the same number of components.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/ppir: optimizations in regalloc spilling code
Erico Nunes [Tue, 27 Aug 2019 23:07:55 +0000 (01:07 +0200)]
lima/ppir: optimizations in regalloc spilling code

Avoid creating unnecessary instructions for the load/store temp nodes
when not required, to further reduce register pressure.

The store_temp operation seems to be unable to do any spilling.
At least the offline shader seems to never output instructions accessing
swizzled components, and attempting to output that in ppir results in
errors. So, force spilled registers to allocate a full vec4 register.
This seems to be the optimal way as it is possible to always keep stores
and temps in a single instruction that can be pipelined.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agolima/ppir: mark regalloc created ssa unspillable
Erico Nunes [Mon, 26 Aug 2019 18:59:57 +0000 (20:59 +0200)]
lima/ppir: mark regalloc created ssa unspillable

One ssa created in the spillinc code in ppir_update_spilled_src was not
properly being marked 'spilled', which made it a candidate for future
spilling attempts.
Since it was being inserted by the spilling code itself, let's mark it
unspillable to avoid an infinite spilling loop.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agov3d: writes to magic registers aren't RF writes after THREND
Jose Maria Casanova Crespo [Wed, 24 Jul 2019 20:01:00 +0000 (22:01 +0200)]
v3d: writes to magic registers aren't RF writes after THREND

Shaders must not attempt to write to the register files in the last
three instructions, but that doesn't include the magic registers:

nop                  ; nop               ; thrsw; ldtmu.- *** ERROR ***
nop                  ; nop
nop                  ; nop

v2: Simplify validation rules. (Eric Anholt)
v3: Adjust validation even more. (Eric Anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>