mesa.git
2 years agoglx: convert a malloc+memset to calloc
Adam Jackson [Wed, 14 Aug 2019 16:04:42 +0000 (12:04 -0400)]
glx: convert a malloc+memset to calloc

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agoglx: Fix parameter documentation of glx_config_create_list
Adam Jackson [Wed, 14 Aug 2019 16:02:49 +0000 (12:02 -0400)]
glx: Fix parameter documentation of glx_config_create_list

'minimum_size' is not, in fact, an argument to this function.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2 years agoanv: inline uniforms blocks don't count toward descriptor set limits
Arcady Goldmints-Orlov [Sat, 27 Jul 2019 19:52:41 +0000 (14:52 -0500)]
anv: inline uniforms blocks don't count toward descriptor set limits

In a descriptor set inline uniform blocks don't use up any bindings.
However, the presence of any inline uniform blocks doed require the
use of the descriptor buffer, which takes up one binding.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir: add divergence analysis pass.
Daniel Schürmann [Mon, 20 May 2019 12:58:23 +0000 (14:58 +0200)]
nir: add divergence analysis pass.

This pass expects the shader to be in LCSSA form.
The algorithm is based on 'The Simple Divergence Analysis' from
Diogo Sampaio, Rafael De Souza, Sylvain Collange, Fernando Magno Quintão Pereira.
Divergence Analysis. ACM Transactions on Programming Languages and Systems (TOPLAS)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2 years agonir/subgroups: Lower clustered reductions with cluster_size >= subgroup_size into...
Rhys Perry [Wed, 24 Apr 2019 09:25:25 +0000 (10:25 +0100)]
nir/subgroups: Lower clustered reductions with cluster_size >= subgroup_size into reductions

The behavior for reductions with cluster_size >= subgroup_size is implementation defined.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir/lcssa: allow to create LCSSA phis for loop-invariant booleans
Rhys Perry [Mon, 5 Aug 2019 14:24:18 +0000 (15:24 +0100)]
nir/lcssa: allow to create LCSSA phis for loop-invariant booleans

ACO depends on LCSSA phis for divergent booleans to work correctly.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir/lcssa: Skip loop invariant variables when converting to LCSSA.
Daniel Schürmann [Thu, 28 Mar 2019 11:17:51 +0000 (12:17 +0100)]
nir/lcssa: Skip loop invariant variables when converting to LCSSA.

Co-authored-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir: make nir_to_lcssa() a general NIR pass.
Rhys Perry [Thu, 31 Jan 2019 16:33:23 +0000 (16:33 +0000)]
nir: make nir_to_lcssa() a general NIR pass.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agonir/lcssa: handle deref instructions properly
Daniel Schürmann [Wed, 14 Aug 2019 16:52:50 +0000 (18:52 +0200)]
nir/lcssa: handle deref instructions properly

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 414148cdc124 "nir: Support deref instructions in loop_analyze"
2 years agotgsi_to_nir: only update TGSI properties of the current shader stage
Jose Maria Casanova Crespo [Mon, 19 Aug 2019 13:05:25 +0000 (15:05 +0200)]
tgsi_to_nir: only update TGSI properties of the current shader stage

The implementation introduced in "tgsi_to_nir: be careful about not
losing any TGSI properties silently (v2)" updates all the TGSI properties,
but it didn't take into account that the shader_info structure uses a union
to store the different attributes for each shader stage.

Now we only update the attributes if they affect current shader stage,
avoiding to overwrite members of the union that should be overwritten.
This has created hundreds of regressions in v3d.

For example the TGSI_PROPERTY_VS_BLIT_SGPRS_AMD was overwritting the
same position used by TGSI_PROPERY_CS_FIXED_BLOCK_DEPTH.

Fixes: e3003651978 ("tgsi_to_nir: be careful about not losing any TGSI properties silently (v2)")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoradv/gfx10: do not emit PA_SC_TILE_STEERING_OVERRIDE twice
Samuel Pitoiset [Mon, 19 Aug 2019 13:01:21 +0000 (15:01 +0200)]
radv/gfx10: do not emit PA_SC_TILE_STEERING_OVERRIDE twice

CLEAR_STATE emits it for us.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: do not emit PKT3_CONTEXT_CONTROL with AMDGPU 3.6.0+
Samuel Pitoiset [Mon, 19 Aug 2019 13:01:20 +0000 (15:01 +0200)]
radv: do not emit PKT3_CONTEXT_CONTROL with AMDGPU 3.6.0+

It's emitted by the kernel.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agomesa/program: Take ARB_framebuffers_no_attachments into account in wpos correction
Gert Wollny [Mon, 19 Aug 2019 15:41:46 +0000 (17:41 +0200)]
mesa/program: Take ARB_framebuffers_no_attachments into account in wpos correction

If a drawbuffer is an fbo without an attachment then its 'Height' will be zero,
and we have to take its 'DefaultGeometry.Height' into account.

Fixes on softpipe (with the exception of tests that use multisample):
  dEQP-GLES31.functional.fbo.no_attachments.*

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoiris: Enable non coherent framebuffer fetch on broadwell
Sagar Ghuge [Tue, 16 Jul 2019 18:29:47 +0000 (11:29 -0700)]
iris: Enable non coherent framebuffer fetch on broadwell

v2: Use GEN_GEN in iris_state (Kenneth Graunke)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Free resource if failed to allocate surface state
Sagar Ghuge [Wed, 7 Aug 2019 21:00:14 +0000 (14:00 -0700)]
iris: Free resource if failed to allocate surface state

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Pass isl_surf to fill_surface_state
Sagar Ghuge [Wed, 7 Aug 2019 17:38:17 +0000 (10:38 -0700)]
iris: Pass isl_surf to fill_surface_state

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Add infrastructure to support non coherent framebuffer fetch
Sagar Ghuge [Tue, 16 Jul 2019 18:08:28 +0000 (11:08 -0700)]
iris: Add infrastructure to support non coherent framebuffer fetch

Create separate SURFACE_STATE for render target read in order to support
non coherent framebuffer fetch on broadwell.

Also we need to resolve framebuffer in order to support CCS_D.

v2: Add outputs_read check (Kenneth Graunke)

v3: 1) Import Curro's comment from get_isl_surf
    2) Rename get_isl_surf method
    3) Clean up allocation in case of failure

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Add helper functions to get tile offset
Sagar Ghuge [Tue, 16 Jul 2019 17:48:19 +0000 (10:48 -0700)]
iris: Add helper functions to get tile offset

All helper functions are ported from i965 driver.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Add helper function to get isl dim layout
Sagar Ghuge [Tue, 16 Jul 2019 17:38:00 +0000 (10:38 -0700)]
iris: Add helper function to get isl dim layout

v2: Add missing space (Caio)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoiris: Add render target read entry in binding table
Sagar Ghuge [Tue, 16 Jul 2019 17:27:03 +0000 (10:27 -0700)]
iris: Add render target read entry in binding table

This will be used in next patches for supporting non coherent
framebuffer fetch on Broadwell.

v2: Fix comment (Kenneth Graunke)

v3: 1) Fix a few nits (Caio)
    2) Add comment (Caio)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agobuild: Bump C++ standard requirement to C++14 to fix FTBFS with LLVM 10
Kai Wasserbäch [Sat, 17 Aug 2019 08:59:43 +0000 (10:59 +0200)]
build: Bump C++ standard requirement to C++14 to fix FTBFS with LLVM 10

When building Mesa against a recent LLVM 10 with C++11, the build fails
if the AMD common code is built as well due to "std::index_sequence"
being undeclared.

LLVM requires a minimum of C++14.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2 years agopanfrost: Add madvise support to BO cache
Rob Herring [Wed, 31 Jul 2019 23:28:37 +0000 (23:28 +0000)]
panfrost: Add madvise support to BO cache

The kernel now supports madvise ioctl to indicate which BOs can be freed
when there is memory pressure. Mark BOs purgeable when they are in the
BO cache. The BOs must also be munmapped when they are in the cache or
they cannot be purged.

We could optimize avoiding the madvise ioctl on older kernels once the
driver version bump lands, but probably not worth it given the other
driver features also being added.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2 years agopanfrost: Sync UAPI header from kernel
Rob Herring [Fri, 9 Aug 2019 19:34:14 +0000 (13:34 -0600)]
panfrost: Sync UAPI header from kernel

Sync the panfrost_drm.h UAPI header with the latest from the kernel.
This adds madvise ioctl and GPU feature params.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2 years agomesa: add ext_dsa GetMultiTexLevelParameterEXT
Pierre-Eric Pelloux-Prayer [Wed, 22 May 2019 16:04:33 +0000 (18:04 +0200)]
mesa: add ext_dsa GetMultiTexLevelParameterEXT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: add EXT_dsa glCompressedMultiTex* functions display list support
Pierre-Eric Pelloux-Prayer [Thu, 23 May 2019 09:59:25 +0000 (11:59 +0200)]
mesa: add EXT_dsa glCompressedMultiTex* functions display list support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: add EXT_dsa glCompressedMultiTex* functions
Pierre-Eric Pelloux-Prayer [Mon, 6 May 2019 13:23:53 +0000 (15:23 +0200)]
mesa: add EXT_dsa glCompressedMultiTex* functions

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: add EXT_dsa glCompressedTex* functions display list support
Pierre-Eric Pelloux-Prayer [Thu, 23 May 2019 09:40:11 +0000 (11:40 +0200)]
mesa: add EXT_dsa glCompressedTex* functions display list support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: add EXT_dsa glCompressedTexture(Sub)Image1D/2D/3D functions
Pierre-Eric Pelloux-Prayer [Mon, 6 May 2019 09:25:04 +0000 (11:25 +0200)]
mesa: add EXT_dsa glCompressedTexture(Sub)Image1D/2D/3D functions

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agomesa: refactor compressed_tex_sub_image function
Pierre-Eric Pelloux-Prayer [Wed, 7 Aug 2019 12:42:59 +0000 (14:42 +0200)]
mesa: refactor compressed_tex_sub_image function

Combine compressed_tex_sub_image, compressed_tex_sub_image_error and
compressed_tex_sub_image_no_error in a single function.

The added "enum tex_mode mode" parameter allows to implement the
DSA / non-DSA variants and their error/no_error combination.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agoradv: Add Renoir support.
Bas Nieuwenhuizen [Mon, 12 Aug 2019 21:11:15 +0000 (23:11 +0200)]
radv: Add Renoir support.

Took the freedom to enable dfsm even though I don't have benchmark
results yet, but it seems Raven-like.

Rest is from radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradeonsi/nir: always lower ballot masks as 64-bit, codegen handles it
Marek Olšák [Tue, 13 Aug 2019 00:37:11 +0000 (20:37 -0400)]
radeonsi/nir: always lower ballot masks as 64-bit, codegen handles it

This fixes KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks.

This solution is better, because the IR isn't dependent on wave32.

2 years agoradeonsi: remove the unsafemath debug option
Marek Olšák [Mon, 12 Aug 2019 23:58:45 +0000 (19:58 -0400)]
radeonsi: remove the unsafemath debug option

unlikely to be used in the future

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi/nir: fix counting shader inputs & outputs
Marek Olšák [Wed, 7 Aug 2019 02:58:21 +0000 (22:58 -0400)]
radeonsi/nir: fix counting shader inputs & outputs

2 years agoradeonsi/nir: fix assertion in si_nir_load_sampler_desc
Marek Olšák [Wed, 7 Aug 2019 01:08:57 +0000 (21:08 -0400)]
radeonsi/nir: fix assertion in si_nir_load_sampler_desc

2 years agoradeonsi: clean up si_llvm_context_set_tgsi
Marek Olšák [Wed, 7 Aug 2019 02:51:56 +0000 (22:51 -0400)]
radeonsi: clean up si_llvm_context_set_tgsi

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: allocate and resize global_buffers as needed
Marek Olšák [Mon, 12 Aug 2019 17:50:00 +0000 (13:50 -0400)]
radeonsi: allocate and resize global_buffers as needed

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi/gfx10: don't set PA_SC_TILE_STEERING_OVERRIDE if CLEAR_STATE sets it
Marek Olšák [Tue, 6 Aug 2019 23:49:16 +0000 (19:49 -0400)]
radeonsi/gfx10: don't set PA_SC_TILE_STEERING_OVERRIDE if CLEAR_STATE sets it

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: don't emit PKT3_CONTEXT_CONTROL on amdgpu
Marek Olšák [Tue, 6 Aug 2019 23:52:24 +0000 (19:52 -0400)]
radeonsi: don't emit PKT3_CONTEXT_CONTROL on amdgpu

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoradeonsi: fix an assertion failure: assert(!res->b.is_shared)
Marek Olšák [Fri, 2 Aug 2019 23:07:58 +0000 (19:07 -0400)]
radeonsi: fix an assertion failure: assert(!res->b.is_shared)

This only appears to happen on Raven2.

Possible way to reproduce:

resource_get_handle(WINSYS_HANDLE_TYPE_KMS) --> sets is_shared = true
resource_get_handle(WINSYS_HANDLE_TYPE_DMABUF) --> fail

Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org>
2 years agoradeonsi: handle the use_ngg_streamout flag in si_update_ngg
Marek Olšák [Fri, 2 Aug 2019 21:27:04 +0000 (17:27 -0400)]
radeonsi: handle the use_ngg_streamout flag in si_update_ngg

2 years agoradeonsi: move the tess factor ring size assertion to a place where it matters
Marek Olšák [Fri, 2 Aug 2019 20:26:21 +0000 (16:26 -0400)]
radeonsi: move the tess factor ring size assertion to a place where it matters

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoac/nir: set image=true when loading FMASK for images
Marek Olšák [Wed, 7 Aug 2019 01:07:21 +0000 (21:07 -0400)]
ac/nir: set image=true when loading FMASK for images

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2 years agoetnaviv: rs: add support for 64bpp clears
Christian Gmeiner [Tue, 16 Jul 2019 18:14:00 +0000 (20:14 +0200)]
etnaviv: rs: add support for 64bpp clears

Starting with HALTI2 the RS supports 64bpp clears.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2 years agoetnaviv: update headers from rnndb
Christian GMEINER [Mon, 19 Aug 2019 15:07:29 +0000 (17:07 +0200)]
etnaviv: update headers from rnndb

Update to etna_viv commit c51353e.

Signed-off-by: Christian GMEINER <christian.GMEINER@bachmann.info>
Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2 years agoswrast: Make the fetch funcs table sparse.
Eric Anholt [Wed, 31 Jul 2019 20:30:22 +0000 (13:30 -0700)]
swrast: Make the fetch funcs table sparse.

This shrinks the table, avoids needing to update the table with NULL
entries on every MESA_FORMAT addition, and removes a surprising,
non-unit-tested format number ordering dependency.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2 years agogallium: Remove manual defining of PIPE_FORMAT enum values.
Eric Anholt [Tue, 13 Aug 2019 00:11:36 +0000 (17:11 -0700)]
gallium: Remove manual defining of PIPE_FORMAT enum values.

Now that SVGA doesn't have a table that has to be in PIPE_FORMAT
order, we can let the enums have whatever values they naturally would
without worrying about holes.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2 years agosvga: Drop unsupported formats from the format table.
Eric Anholt [Tue, 13 Aug 2019 00:03:23 +0000 (17:03 -0700)]
svga: Drop unsupported formats from the format table.

Now that we're using the array initializers, we don't need to manually
fill out all these stub entries.

Produced with "sed -i '/.*INVALID.*INVALID.*INVALID/d'
src/gallium/drivers/svga/svga_format.c"

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2 years agosvga: Remove duplication in the format table.
Eric Anholt [Mon, 12 Aug 2019 23:57:52 +0000 (16:57 -0700)]
svga: Remove duplication in the format table.

By using the [ ] = {} array initializer syntax, we no longer need the
entries to be listed in PIPE_FORMAT_* value order.  This means that
people adding new gallium formats don't need to cargo-cult changes to
this driver or regress that non-unit-tested requirement.

While I'm here, drop the lines for formats that no longer exist (the
numbered ones in the table).

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2 years agosvga: Factor out the format conversion table entry lookup.
Eric Anholt [Mon, 12 Aug 2019 23:50:50 +0000 (16:50 -0700)]
svga: Factor out the format conversion table entry lookup.

Seemed like a sensible cleanup, while I was looking at whether I could
make the table sparse.

To make the svga table not require fixups on every new gallium format,
we may want to change how it's populated.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2 years agonir: Add more source types to nir_tex_instr_src_type
Jason Ekstrand [Mon, 19 Aug 2019 01:53:24 +0000 (20:53 -0500)]
nir: Add more source types to nir_tex_instr_src_type

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Compute liveness per-block
Alyssa Rosenzweig [Thu, 15 Aug 2019 21:53:56 +0000 (14:53 -0700)]
pan/midgard: Compute liveness per-block

Rather than using a regalloc based on live internals, computed hastily
with repeated invocations of a forward-analysis pass, we switch to
compute liveness information on a per-block basis.

Within a given basic block, we compute liveness backwards with a
linear-time algorithm; for common shaders, this may help RA terminate
quicker.

Across blocks, we use a work list (really a work set) and check if we're
making progress. This isn't terribly efficient, but it gets the job
done. Point is, we get the live_in/live_out for each block.

From there, it's simple to rerun the linear-time update algorithm to
compute the interference graph.

The benefit of this technique is the ability to ignore "gaps" in
liveness across intermediate blocks that are never executed. On simple
shaders like the loops in glmark, this results in a minor reduction in
register pressure. The motivation was a complex shader in Krita that
failed register allocation due to an unfortunate interaction between
texture pipeline registers and control flow. This shader now compiles
successfully.

total instructions in shared programs: 3439 -> 3438 (-0.03%)
instructions in affected programs: 22 -> 21 (-4.55%)
helped: 1
HURT: 0

total bundles in shared programs: 2077 -> 2076 (-0.05%)
bundles in affected programs: 12 -> 11 (-8.33%)
helped: 1
HURT: 0

total quadwords in shared programs: 3457 -> 3456 (-0.03%)
quadwords in affected programs: 20 -> 19 (-5.00%)
helped: 1
HURT: 0

total registers in shared programs: 341 -> 338 (-0.88%)
registers in affected programs: 9 -> 6 (-33.33%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Analyze load/store for swizzle propagation
Alyssa Rosenzweig [Fri, 16 Aug 2019 14:54:34 +0000 (07:54 -0700)]
pan/midgard: Analyze load/store for swizzle propagation

If there's a nontrivial swizzle fed into an extra (shortened) argument,
we bail on copyprop. No glmark changes (since it doesn't use fancy
texturing/loads).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Treat cubemaps "stores" as loads
Alyssa Rosenzweig [Fri, 16 Aug 2019 14:50:12 +0000 (07:50 -0700)]
pan/midgard: Treat cubemaps "stores" as loads

It's always been ambiguous which they are, but their primary register is
their output, not their input; therefore, they are loads.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Clamp cubemap swizzle to XYXX
Alyssa Rosenzweig [Fri, 16 Aug 2019 14:41:29 +0000 (07:41 -0700)]
pan/midgard: Clamp cubemap swizzle to XYXX

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Clamp st_vary swizzle by number of components
Alyssa Rosenzweig [Thu, 15 Aug 2019 23:53:03 +0000 (16:53 -0700)]
pan/midgard: Clamp st_vary swizzle by number of components

Same issue with liveness analysis. If we store out a vec3, we should not
reference the .w component.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Use type-appropriate swizzle for texture coordinate
Alyssa Rosenzweig [Thu, 15 Aug 2019 23:41:53 +0000 (16:41 -0700)]
pan/midgard: Use type-appropriate swizzle for texture coordinate

The texture coordinate for a 2D texture could be a vec2 or a vec3,
depending if it's an array texture or not. If it's vec2 (non-array
texture), we should not reference the z component; otherwise, liveness
analysis will get very confused when z is never written.

v2: Fix typo (Ilia).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Set mask for lowered read-hazard moves
Alyssa Rosenzweig [Thu, 15 Aug 2019 23:29:15 +0000 (16:29 -0700)]
pan/midgard: Set mask for lowered read-hazard moves

If we need to lower a move for a read from a vec2 texture coordinate, we
shouldn't write zw, even incidentally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Fix texw lowering with complex control flow
Alyssa Rosenzweig [Thu, 15 Aug 2019 21:23:05 +0000 (14:23 -0700)]
pan/midgard: Fix texw lowering with complex control flow

Fixes shaders with control flow like:

   out = 0;

   if (A) {
      if (B)
         out = texture(A, ...)
   } else {
      out = texture(B, ...)
   }

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_rewrite_index_dst_single helper
Alyssa Rosenzweig [Thu, 15 Aug 2019 21:22:48 +0000 (14:22 -0700)]
pan/midgard: Add mir_rewrite_index_dst_single helper

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Print predecessors in MIR
Alyssa Rosenzweig [Thu, 15 Aug 2019 17:49:33 +0000 (10:49 -0700)]
pan/midgard: Print predecessors in MIR

Just as a sanity check.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Index blocks for printing
Alyssa Rosenzweig [Thu, 15 Aug 2019 17:43:56 +0000 (10:43 -0700)]
pan/midgard: Index blocks for printing

Better than having pointers flying about.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_foreach_src
Alyssa Rosenzweig [Thu, 15 Aug 2019 16:53:25 +0000 (09:53 -0700)]
pan/midgard: Add mir_foreach_src

This is repeated often enough.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_foreach_instr_in_block_rev
Alyssa Rosenzweig [Thu, 15 Aug 2019 16:51:13 +0000 (09:51 -0700)]
pan/midgard: Add mir_foreach_instr_in_block_rev

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_foreach_successor helper
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:48:34 +0000 (08:48 -0700)]
pan/midgard: Add mir_foreach_successor helper

Now we should be able to walk the control-flow graph naturally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_foreach_predecessor utility
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:36:41 +0000 (08:36 -0700)]
pan/midgard: Add mir_foreach_predecessor utility

It's ugly, but c'est la vie.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Link exit block
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:23:48 +0000 (08:23 -0700)]
pan/midgard: Link exit block

The exit block has been 'dangling' in the successors graph, so let's
ensure it's linked in.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_exit_block helper
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:16:38 +0000 (08:16 -0700)]
pan/midgard: Add mir_exit_block helper

The exit block is gauranteed to be empty, signaling the end of the
program.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Maintain block predecessor set
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:11:10 +0000 (08:11 -0700)]
pan/midgard: Maintain block predecessor set

While we already compute the successors array, for backwards data flow
analysis, it is useful to walk the control flow graph backwards based on
predecessors, so let's compute that information as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Use ralloc on ctx/blocks
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:10:46 +0000 (08:10 -0700)]
pan/midgard: Use ralloc on ctx/blocks

This will allow us to get some level of automatic memory management.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Shrink successors[] to 2 length
Alyssa Rosenzweig [Thu, 15 Aug 2019 15:00:04 +0000 (08:00 -0700)]
pan/midgard: Shrink successors[] to 2 length

A block can't have more.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agonir: Add missing dependency in Android.nir.gen.mk
Roman Stratiienko [Wed, 14 Aug 2019 08:38:43 +0000 (11:38 +0300)]
nir: Add missing dependency in Android.nir.gen.mk

Fixes incremental build with Android

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2 years agomeson: build lima tools as part of 'all' tools
Erico Nunes [Fri, 16 Aug 2019 13:19:59 +0000 (15:19 +0200)]
meson: build lima tools as part of 'all' tools

This is primarily so that this build gets tested in CI and we don't
break it again.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2 years agoac/nir: Fix store_scratch with a non-full writemask
Connor Abbott [Fri, 16 Aug 2019 10:46:27 +0000 (12:46 +0200)]
ac/nir: Fix store_scratch with a non-full writemask

By adding one more helper to ac_llvm_build, we can also easily keep
vector stores together.

Fixes the
tests/spec/glsl-1.30/execution/fs-large-local-array-vec4.shader_test
piglit test.

Fixes: 74470baebbd ("ac/nir: Lower large indirect variables to scratch")
Reviewed-by: Marek Olšák <marek.olsak@amd.com
2 years agoglsl/standalone: init shader stage in init_gl_program()
Vasily Khoruzhick [Fri, 16 Aug 2019 05:17:26 +0000 (22:17 -0700)]
glsl/standalone: init shader stage in init_gl_program()

Otherwise lima standalone compiler fails when trying to compile fragment
shader with:

lima_compiler: ../src/compiler/nir/nir.c:55: nir_shader_create: Assertion `si->stage == stage' failed

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agoiris: Only request an input mask if the shader needs it
Jason Ekstrand [Fri, 16 Aug 2019 22:48:53 +0000 (17:48 -0500)]
iris: Only request an input mask if the shader needs it

Fixes: aebca3961b "iris: Fix handling of SIMD32 fragment shaders"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agogallium: add back YVU support
Xiong, James [Thu, 15 Aug 2019 17:02:52 +0000 (10:02 -0700)]
gallium: add back YVU support

PIPE_FORMAT_YV12 is not handled so switching to PIPE_FORMAT_IYUV and
adding back YVU support.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agolima: actually wait for bo in lima_bo_wait
Erico Nunes [Wed, 14 Aug 2019 20:39:33 +0000 (22:39 +0200)]
lima: actually wait for bo in lima_bo_wait

PIPE_TIMEOUT_INFINITE is unsigned and gets assigned to signed fields
where it ends up as -1. When this reaches the kernel as a timeout it
gets translated as no timeout, which cause the waiting functions to
return immediately and not actually wait for a completion.

This seems to cause unstable results with lima where even piglit tests
randomly fail.

Handle this by setting the signed max value in case of infinite timeout.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2 years agonir/algebraic: add a few masking-before-unpack optimizations
Rhys Perry [Thu, 11 Jul 2019 14:31:50 +0000 (15:31 +0100)]
nir/algebraic: add a few masking-before-unpack optimizations

Helps some Dawn of War 3 and F1 2017 shaders with ACO:
Totals from affected shaders:
SGPRS: 2136 -> 2128 (-0.37 %)
VGPRS: 1624 -> 1628 (0.25 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 168068 -> 164332 (-2.22 %) bytes
LDS: 44 -> 44 (0.00 %) blocks
Max Waves: 222 -> 221 (-0.45 %)
Wait states: 0 -> 0 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agolima: fix compilation of standalone compiler
Vasily Khoruzhick [Thu, 15 Aug 2019 05:08:50 +0000 (22:08 -0700)]
lima: fix compilation of standalone compiler

Fixes: e0aeee946004("lima: add summary report for shader-db")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2 years agoRevert "radv/gfx10: Enable DCC for storage images."
Bas Nieuwenhuizen [Thu, 15 Aug 2019 23:13:00 +0000 (01:13 +0200)]
Revert "radv/gfx10: Enable DCC for storage images."

Quite useless without DCC for LAYOUT_GENERAL.

Fixes: b4dad3afaa0 Revert "radv: Do not decompress on LAYOUT_GENERAL."
Acked-by: Dave Airlie <airlied@redhat.com>
2 years agoRevert "radv: Do not decompress on LAYOUT_GENERAL."
Bas Nieuwenhuizen [Thu, 15 Aug 2019 23:06:55 +0000 (01:06 +0200)]
Revert "radv: Do not decompress on LAYOUT_GENERAL."

Causes issues with a bunch of games with DXVK.

Fixes: 50add1b33ae "radv: Do not decompress on LAYOUT_GENERAL."
Acked-by: Dave Airlie <airlied@redhat.com>
2 years agomesa: add support for CET to x86/x86-64 asm files.
Dave Airlie [Fri, 9 Aug 2019 03:25:56 +0000 (13:25 +1000)]
mesa: add support for CET to x86/x86-64 asm files.

Control-flow enforcement technology is a new instructions on x86
processors to denote where indirect jumps can land. Gcc auto adds
the instruction (which encodes as a NOP on older CPUs) to entrypoints
but assembler files need manual adding. This adds it to all the
entry points in the mesa x86/x86-64 assembler files.

This will only happen if mesa is built with the -fcf-protection flag
to gcc as some distros are wanting to do.

Acked-by: Eric Anholt <eric@anholt.net>
2 years agopan/bifrost: Manually constant fold register class
Alyssa Rosenzweig [Thu, 15 Aug 2019 14:03:35 +0000 (07:03 -0700)]
pan/bifrost: Manually constant fold register class

Fixes errors for some people building Mesa:

../src/panfrost/bifrost/bifrost_sched.c:32:31: error: initializer
element is not constant
 const unsigned max_vec2_reg = max_primary_reg / 2;

../src/panfrost/bifrost/bifrost_sched.c:33:31: error: initializer
element is not constant
 const unsigned max_vec3_reg = max_primary_reg / 4; // XXX: Do we need
to align vec3 to vec4 boundary?

../src/panfrost/bifrost/bifrost_sched.c:34:31: error: initializer
element is not constant
 const unsigned max_vec4_reg = max_primary_reg / 4;

../src/panfrost/bifrost/bifrost_sched.c:35:32: error: initializer
element is not constant
 const unsigned max_registers = max_primary_reg +

../src/panfrost/bifrost/bifrost_sched.c:40:28: error: initializer
element is not constant
 const unsigned vec2_base = primary_base + max_primary_reg;

../src/panfrost/bifrost/bifrost_sched.c:41:28: error: initializer
element is not constant
 const unsigned vec3_base = vec2_base + max_vec2_reg;

../src/panfrost/bifrost/bifrost_sched.c:42:28: error: initializer
element is not constant
 const unsigned vec4_base = vec3_base + max_vec3_reg;

../src/panfrost/bifrost/bifrost_sched.c:43:27: error: initializer
element is not constant
 const unsigned vec4_end = vec4_base + max_vec4_reg;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agogallium/util: widen type before multiplication
Erik Faye-Lund [Tue, 13 Aug 2019 11:02:24 +0000 (13:02 +0200)]
gallium/util: widen type before multiplication

This method returns size_t, but the multiplication multiplies two
integers, leading to overflow rather than type widening.

Noticed by compiling with MSVC, which emits a warning.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agomesa: avoid warning on Windows
Erik Faye-Lund [Tue, 13 Aug 2019 11:01:42 +0000 (13:01 +0200)]
mesa: avoid warning on Windows

On Windows, p_atomic_inc_return returns an unsigned long long rather
than the type the pointer refers to, so let's make sure we cast the
result to the right type. Otherwise, we'll trigger a warning about
the wrong format-string for the type.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agowin32: unify strcasecmp definitions
Erik Faye-Lund [Thu, 8 Aug 2019 12:08:16 +0000 (14:08 +0200)]
win32: unify strcasecmp definitions

There was two incompatible definitions of strcasecmp, which lead to a
compiler warning. Let's clean this up by only leaving one of them, and
using that one all the time.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agomesa/main: avoid warning when casting offset to pointer
Erik Faye-Lund [Thu, 8 Aug 2019 12:01:57 +0000 (14:01 +0200)]
mesa/main: avoid warning when casting offset to pointer

This generates a warning on some 64-bit systems, so let's cast to a
properly sized integer first.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agonir: avoid warning when casting bogus pointer
Erik Faye-Lund [Thu, 8 Aug 2019 11:59:44 +0000 (13:59 +0200)]
nir: avoid warning when casting bogus pointer

This intentionally-bogus pointer generates a warning on some 64-bit
systems, so let's cast to a properly-sized integer first.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoglsl: fixup u64-warning
Erik Faye-Lund [Mon, 5 Aug 2019 15:37:15 +0000 (17:37 +0200)]
glsl: fixup u64-warning

Similarly to the unsigned-version, we need to first cast the result to a
suiting integer before negating the number, otherwise we'll trigger a
warning.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoisl: Enable Unorm Path in Color Pipe
Kenneth Graunke [Wed, 14 Aug 2019 20:54:55 +0000 (13:54 -0700)]
isl: Enable Unorm Path in Color Pipe

Improves performance on my Icelake 8x8 locked to 700Mhz.  For example,
some GfxBench5 subtests have the following results:

- [i965] gl_manhattan: ................ 7.01119% +/- 0.180971% (n=5)
- [i965] gl_4 (Car Chase):              4.24351% +/- 0.175622% (n=5)
- [i965] gl_blending:  ................ 3.36327% +/- 0.180267% (n=5)
- [i965] gl_5_normal (Aztec Ruins):     1.67962% +/- 0.243534% (n=10)
- [iris] gl_manhattan: ................ 3.92357% +/- 0.073965% (n=25)
- [iris] gl_4 (Car Chase):              2.17746% +/- 0.0826858% (n=5)
- [iris] gl_blending:  ................ 2.79599% +/- 0.803652% (n=15)
- [iris] gl_5_normal (Aztec Ruins):     1.30930% +/- 0.106523% (n=25)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoanv: Properly initialize device->slice_hash.
Rafael Antognolli [Wed, 14 Aug 2019 22:13:55 +0000 (15:13 -0700)]
anv: Properly initialize device->slice_hash.

When subslices_delta == 0 and we take the early return,
device->slice_hash is not initialized on GEN11. It then causes a
segfault when going through anv_DestroyDevice, if compiled with
valgrind.

Fixes: 7bc022b4bbc ("anv/gen11: Emit SLICE_HASH_TABLE when pipes are
                    unbalanced.)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agointel/compiler: Fix resource leak in error path
Danylo Piliaiev [Tue, 13 Aug 2019 08:25:03 +0000 (11:25 +0300)]
intel/compiler: Fix resource leak in error path

CID: 1452261

Fixes: 04a99515 "intel/compiler: add ability to override shader's assembly"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2 years agopanfrost: Implement native RECT textures
Alyssa Rosenzweig [Wed, 14 Aug 2019 15:44:40 +0000 (08:44 -0700)]
panfrost: Implement native RECT textures

We started honouring the normalized_coords flag in the texture
descriptor, but a bisection revealed that broke RECT textures -- since
we were *also* lowering them in the shader. So just remove the
shader-based lowering, use native RECT textures, and enjoy the nominal
reduction in complexity and performance boost.

Fixes: 3e47a1181b7 ("panfrost: Add MALI_SAMP_NORM_COORDS flag")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Add R10G10B10A2_SSCALED vertex format
Alyssa Rosenzweig [Tue, 13 Aug 2019 17:27:09 +0000 (10:27 -0700)]
panfrost: Add R10G10B10A2_SSCALED vertex format

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Disassemble UBO index explicitly
Alyssa Rosenzweig [Tue, 13 Aug 2019 18:10:06 +0000 (11:10 -0700)]
pan/midgard: Disassemble UBO index explicitly

It's a bit of a special case but that's fine.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Account for unaligned UBOs when promoting uniforms
Alyssa Rosenzweig [Tue, 13 Aug 2019 16:27:43 +0000 (09:27 -0700)]
pan/midgard: Account for unaligned UBOs when promoting uniforms

We only know how to promote aligned accesses, although theoretically we
should be able to promote unaligned to swizzles in the future. Check
this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add mir_ubo_shift helper
Alyssa Rosenzweig [Tue, 13 Aug 2019 16:27:16 +0000 (09:27 -0700)]
pan/midgard: Add mir_ubo_shift helper

Different UBO reads have different shift requirements.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Address emit_ubo_read offset in bytes
Alyssa Rosenzweig [Tue, 13 Aug 2019 16:13:31 +0000 (09:13 -0700)]
pan/midgard: Address emit_ubo_read offset in bytes

We'll want to be smarter about unaligned reads, so let's get this code
all in one place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Wire writemask into UBO reads
Alyssa Rosenzweig [Tue, 13 Aug 2019 16:11:48 +0000 (09:11 -0700)]
pan/midgard: Wire writemask into UBO reads

Helps the disassembly be clearer and maybe regalloc be smarter.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Identify UBO/SSBO op symmetry
Alyssa Rosenzweig [Tue, 13 Aug 2019 15:51:40 +0000 (08:51 -0700)]
pan/midgard: Identify UBO/SSBO op symmetry

It's the same thing, just shifted.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>