meta: Abort meta path if ReadPixels need rgb to luminance conversion

After recent addition of pbo testing in piglit test getteximage-luminance,
it fails on i965. This patch makes a sub test pass.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa: Turn need_rgb_to_luminance_conversion() in to a global function

This will be used by _mesa_meta_pbo_GetTexSubImage() in a later patch.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa: Use helper function need_rgb_to_luminance_conversion()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

mesa: Handle integer formats in need_rgb_to_luminance_conversion()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

meta: Use is_power_of_two() helper function

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()

We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

i965: Remove break after return

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

nv50/ir: OP_JOIN is a flow instruction

OP_JOIN instructions are assumed to be flow instructions and mercilessly
casted to FlowInstruction.

This patch fixes an instance where an OP_JOIN is created as a plain
instruction. This can cause crashes in the ir printer.

[imirkin: add ->fixed = 1]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

docs: add news item and link release notes for mesa 10.6.0

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256sums for the 10.6.0 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 5d327b373531861f86a726db669b3d656f1b5f8d)

docs: Update 10.6.0 release notes

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 3b9cde5c8138fb5cc45c652f2a5c15c5fa222bd7)

ilo: add ilo_state_raster_{line,poly}_stipple

Initialize hardware stipple states on bound instead of on emission.

ilo: add ilo_state_sample_pattern

Move sample pattern initialization from ilo_render to
ilo_state_sample_pattern.

ilo: add 3DSTATE_AA_LINE_PARAMETERS to ilo_state_raster

Utilize ilo_state_raster to avoid redundant state change.

gallium/util: add util_last_bit64

This will be needed by radeonsi.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: fix "tesselation" typo

Trivial.

r600g: handle TGSI input/output array declarations correctly

Most of this code could be removed if r600g used tgsi_shader_info.

ilo: merge ilo_state_3d*.[ch] to ilo_state.[ch]

With most code replaced to ilo_state_*, what was left did not belong there
anymore.

ilo: add ilo_state_ps to ilo_shader_cso

ilo: add ilo_state_{vs,hs,ds,gs} to ilo_shader_cso

ilo: embed ilo_state_sbe in ilo_shader

ilo: embed ilo_state_vf in ilo_ve_state

ilo: embed ilo_state_urb in ilo_state_vector

ilo: embed ilo_state_sol in ilo_shader

ilo: embed ilo_state_cc in ilo_blend_state

ilo: embed ilo_state_raster in ilo_rasterizer_state

ilo: embed ilo_state_viewport in ilo_viewport_state

ilo: replace ilo_sampler_cso with ilo_state_sampler

ilo: replace ilo_view_surface with ilo_state_surface

ilo: replace ilo_zs_surface with ilo_state_zs

ilo: add ilo_state_ps

We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs,ps}.

ilo: add ilo_state_{vs,hs,ds,gs}

We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs} and ps
payload.

ilo: add ilo_state_sbe

We want to replace ilo_kernel_routing with ilo_state_sbe.

ilo: add ilo_state_vf

We want to replace ilo_ve_state with ilo_state_vf.

ilo: add ilo_state_urb

ilo: add ilo_state_sol

ilo: add ilo_state_cc

We want to replace ilo_dsa_state and ilo_blend_state with ilo_state_cc.

ilo: add ilo_state_raster

We want to replace ilo_rasterizer_state with ilo_state_raster.

ilo: add ilo_state_viewport

We want to replace ilo_viewport_cso and ilo_scissor_state with
ilo_state_viewport.

ilo: add ilo_state_sampler

We want to replace ilo_sampler_cso with ilo_state_sampler.

ilo: add ilo_state_surface

We want to replace ilo_view_surface with ilo_state_surface.

ilo: add ilo_state_zs

We want to replace ilo_zs_surface with ilo_state_zs.  One noteworthy
difference is that ilo_state_zs always aligns level 0 to 8x4 when HiZ is
enabled.  HiZ will not be enabled for 1D surfaces as a result.

ilo: update genhw headers

Generate these new enums

  enum gen_reorder_mode;
  enum gen_clip_mode;
  enum gen_front_winding;
  enum gen_fill_mode;
  enum gen_cull_mode;
  enum gen_pixel_location;
  enum gen_sample_count;
  enum gen_inputattr_select;
  enum gen_msrast_mode;
  enum gen_prefilter_op;

Correct the type of GEN6_SAMPLER_DW0_BASE_LOD.  Rename gen_logicop_function,
gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and
others.

ilo: add ilo_image_disable_aux()

When aux bo allocation fails, ilo_image_disable_aux() should be called to
disable aux buffer.

ilo: add array_size and level_count to ilo_image

We will use them for bound checking.

ilo: add pipe_texture_target to ilo_image

Save the target in ilo_image instead of passing it around.

ilo: fix "Render Cache Read Write Mode"

It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.

ilo: avoid resource owning in core

It is up to the users whether to reference count the BOs or not.

ilo: assert core objects are zero-initialized

Core objects are usually embedded inside calloc()'ed objects and we expect
them to be zero-initialized.

radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallivm: Only build lp_profile() body when PROFILE is defined

The only use of lp_profile() is wrapped in #if defined(PROFILE),
so there is no reason to build it unless this macro is defined.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

glsl: fix compile error message

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965/gen8+: Add aux buffer alignment assertions

This helped find the incorrect HALIGN values from the previous patches.

v2: Add PRM references for assertions (Chad)

v3: Remove duplicated part of commit message, assert num_samples > 1, instead of
num_samples > 0. (Chad)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/gen9: Set HALIGN_16 for all aux buffers

Just like the previous patch, but for the GEN9 constraints.

v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.

v3:
Remove stray whitespace introduced in v2 (Chad)
Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part
about gen7 (Chad).

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v1)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/gen8: Correct HALIGN for AUX surfaces

This restriction was attempted in this commit:
commit 47053464630888f819ef8cc44278f1a1220159b9
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date:   Fri Feb 13 11:21:21 2015 -0800

   i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT

However, the commit itself doesn't achieve the desired goal as determined by the
asserts which the next patch adds. mcs_mt is NULL (never set) we're in the
process of allocating the mcs_mt miptree when we get to this function. I didn't
check, but perhaps this would work with blorp, however, meta clears allocate the
miptree structure (which AFAICT needs the alignment also) way before it
allocates using meta clears where the renderbuffer is allocated way before the
aux buffer.

The restriction is referenced in a few places, but the most concise one [IMO]
from the spec is for Gen9. Gen8 loosens the restriction in that it only requires
this for non-msrt surface.

   When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
   be used.

With the code before the miptree layout flag rework (patches preceding this),
accomplishing this workaround is very difficult.

v2:
bugfix: Don't set HALIGN16 for gens before 8 (Chad)

v3:
non-trivial rebase

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965: Extract tiling from fast clear decision

There are several constraints when determining if one can fast clear a surface.
Some of these are alignment, pixel density, tiling formats, and others that vary
by generation. The helper function which exists today does a suitable job,
however it conflates "BO properties" with "Miptree properties" when using
tiling. I consider the former to be attributes of the physical surface, things
which are determined through BO allocation, and the latter being attributes
which are derived from the API, and having nothing to do with the underlying
surface.

Determining tiling properties and creating miptrees are related operations
(when we allocate a BO for a miptree) with some disjoint constraints. By
extracting the decisions into two distinct choices (tiling vs. miptree
properties), we gain flexibility throughout the code to make determinations
about when we can or cannot fast clear strictly on the miptree.

To signify this change, I've also renamed the function to indicate it is a
distinction made on the miptree. I am torn as to whether or not it was a good
idea to remove "non_msrt" since it's a really nice thing for grep.

v2:
Reword some comments (Chad)
intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad)
Make full if ladder for gens in above function (Chad)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

i965/gen9: Only allow Y-Tiled MCS buffers

For GEN9, much of the logic to use X-Tiled buffers has been stripped out. It is
still supported in some places, but it's never desirable. Unfortunately we don't
yet have the ability to have Y-Tiled scanout (see:
http://patchwork.freedesktop.org/patch/46984/),

NOTE: This patch shouldn't actually do anything since SKL doesn't yet use fast
clears (they are disabled because they are causing regressions). THerefore, the
only case we can get to this function on SKL is by way of
intel_update_winsys_renderbuffer_miptree.

v2: Update commit message to be more clear that the NOTE is for SKL only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Consolidate certain miptree params to flags

I think pretty much everyone agrees that having more than a single bool as a
function argument is bordering on a bad idea. What sucks about the current
code is in several instances it's necessary to propagate these boolean
selections down to lower layers of the code. This requires plumbing (mechanical,
but still churn) pretty much all of the miptree functions each time.  By
introducing the flags paramater, it is possible to add miptree constraints very
easily.

The use of this, as is already the case, is sometimes we have some information
at the time we create the miptree that needs to be known all the way at the
lowest levels of the create/allocation, disable_aux_buffers is currently one
such example. There will be another example coming up in a few patches.

v2:
Tab fix. (Ben)
Long line fixes (Topi)
Use anonymous enum instead of #define for layout flags (Chad)
Use 'X != 0' instead of !!X (everyone except Chad)

v3:
Some non-trivial conflict resolution on top of Anuj's patches.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: "Pohjolainen, Topi" <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl: enforce restriction on AoA interface blocks in GLSL ES 3.10

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

glsl: enforce fragment shader input restrictions in GLSL ES 3.10

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

glsl: enforce output variable rules for GLSL ES 3.10

Some rules are already applied this just adds the missing ones.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

i965/nir: Support barrier intrinsic function

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: Implement support for ir_barrier

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Add brw_barrier to emit a Gateway Barrier SEND

This will be used to implement the Gateway Barrier SEND needed to implement
the barrier function.

v2:
 * notify => gateway_notify (Ken)
 * combine short lines of brw_barrier proto/decl (mattst88)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Add brw_WAIT to emit wait instruction

This will be used to implement the barrier function.

v2:
 * Rename to brw_WAIT (mattst88)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Add notification register

This will be used by the wait instruction when implementing the barrier()
function.

v2:
 * Changes suggested by mattst88

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Disassemble Gateway SEND messages

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/inst: Add gateway_notify and gateway_subfuncid fields

These fields will be used when emitting a send for the barrier function.

Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor

v2:
 * notify => gateway_notify (Ken)
 * define bits for gen4-gen6 (bwidawsk, Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add GATEWAY_SFID definitions

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

nir: Add barrier intrinsic function

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

glsl: Add builtin barrier() function

[jordan.l.justen@intel.com: Add CS support]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Add ir node for barrier

v2:
 * Changes suggested by mattst88

[jordan.l.justen@intel.com: Add nir support]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/cs: Use exec all for CS terminate

This prevents an assertion from being hit with SIMD16:

Assertion `inst->exec_size == dispatch_width() || force_writemask_all' failed.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Fix unused variable warning

Annotate offset_components with attribute 'unused'.

Reviewed-by: Matt Turner <mattst88@gmail.com>

vc4: automake: enable subdir-objects

Silence the warnings about the future incompatibility with automake 2.0

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: build xmlconfig to a separate static library

As we use the file from both the dri modules and loader, we end up with
multiple definition of the symbols provided in our gallium dri  modules.
Additionally we compile the file twice.

Resolve both issues, effectively enabling the build on toolchains which
don't support -Wl,--allow-multiple-definition.

v2: [Emil Velikov]
 - Fix the Scons/Android build.
 - Resolve libgbm build issues (bring back the missing -lm)

Cc: Julien Isorce <j.isorce@samsung.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90310
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90905
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/nine: link against libnir/libglsl_util

Based on commit 101142c4010(xa: support for drivers which use NIR)

Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90466
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

pipe-loader: add libnir and libglsl_util to the link

Based on commit 101142c4010(xa: support for drivers which use NIR)

Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90466
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa; add a dummy _mesa_error_no_memory() symbol  to libglsl_util

Rather than forcing everyone to provide their own definition of the symbol
provide a common (dummy) one.

This helps us resolve the build of the standalone pipe-drivers (amongst
others), which are missing the symbol.

Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

gallium: use $(top_builddir) when referencing static archives

Just like every other place in gallium.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

freedreno: use CXX linker rather than explicit link against libstdc++

Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: coding style fixes

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: plug some obvious memory leaks

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: minor surface management cleanups

Drop the stub/unused function haiku_create_surface() and add some basic implementation for destroy_surface()

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: kill off haiku_log()

It's an incomplete copy of the default _eglLog() implementation. Just
use the default logger.

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: we don't use src/loader, drop all the references to it

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: remove unused variables in struct haiku_egl_driver

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: handle memory allocation failure

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: use CALL/TRACE/ERROR over _eglLog() for haiku specifics

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: remove commented out code

It serves little to no purpose. As the driver gets updated, one can
look at the existing implementation (dri2) for reference rather than
letting the commented functions bitrot.

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl/haiku: use correct version variable

Earlier commit folded the two separate variables into one, but forgot to
update the haiku driver.

Fixes: 0e4b564ef28(egl: combine VersionMajor and VersionMinor into one
variable)
Cc: Marek Olšák <marek.olsak@amd.com>>
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

trace: Add missing p_compiler.h include.

For boolean.

Trivial.

i965/fs: Remove one more fixed brw_null_reg() from the visitor.

Instead use fs_builder::null_reg_f() which has the correct register
width.  Avoids the assertion failure in fs_builder::emit() hit by the
"ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment"
GLES3 conformance test introduced by 4af4cfba9ee1014baa4a777660fc9d53d57e4c82.

Reported-and-reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."

This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043.

The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.
interpolation.lines_wide" test appears to be broken on Cherryview when
we expose line widths greater than 12.0.  I'm not sure why.

For now, just go back to the limits we used on older platforms.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902
Acked-by: Matt Turner <mattst88@gmail.com>

i965: Re-index SSA definitions before printing NIR code.

This makes the SSA definitions use sequential numbers (0, 1, 2, ...)
instead of seemingly random ones.  There's not much point normally,
but it makes debug output much easier to read.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

gallium: remove explicit values from PIPE_CAP_ enums

The other PIPE_CAPF_ and PIPE_SHADER_CAP_ enums don't have explicit values.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa/main: Don't use ONCE_FLAG_INIT as a r-value.

It should only be used as an initializer expression.

Trivial, and fixes Windows builds.

Nevertheless, overwriting an once_flag like this seems dangerous and
should be revised.

i965/gen8: Fix antialiased line rendering with width < 1.5

The same fix Marius implemented for gen6 (commit a9b04d8a) and
gen7 (commit 24ecf37a).

Also, we need the same code to handle special cases of line width
in gen6, gen7 and now gen8, so put that in the helper function
we use to compute the line width.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: fix constructing a vector from a matrix

Without this patch, the following constructs (not an extensive list)
would crash mesa:

- mat2 foo = mat2(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); ivec4 bar = ivec4(foo);

The first case is explicitely allowed by the GLSL spec, as seen on
page 101 of the GLSL 4.40 spec:

"vec4(mat2) // the vec4 is column 0 followed by column 1"

The other cases are implicitely allowed also.

The actual changes are quite minimal. We first split each column of
the matrix to a list of vectors and then use them to initialize the
vector. An additional check to make sure that we are not trying to
copy 0 elements of a vector fix the (i)vec4(mat3) case as the last
vector (3rd column) is not needed at all.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>

mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1

(increases ES31-CTS.draw_indirect.basic.* passing tests)

v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>