mesa.git
3 years agoloader: add loader_open_render_node(..)
Christian Gmeiner [Thu, 9 Aug 2018 05:12:22 +0000 (07:12 +0200)]
loader: add loader_open_render_node(..)

This helper is almost a 1:1 copy of tegra_open_render_node().

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
3 years agotegra: fix memory leak
Christian Gmeiner [Fri, 10 Aug 2018 09:51:25 +0000 (11:51 +0200)]
tegra: fix memory leak

Fixes: 1755f608f52 ("tegra: Initial support")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
3 years agost/dri: Don't expose sRGB formats to clients
Daniel Stone [Fri, 31 Aug 2018 16:34:03 +0000 (17:34 +0100)]
st/dri: Don't expose sRGB formats to clients

Though the SARGB8888 format is used internally through its FourCC value,
it is not a real format as defined by drm_fourcc.h; it cannot be used
with KMS or other interfaces expecting drm_fourcc.h format codes.

Ensure we don't advertise it through the dmabuf format/modifier query
interfaces, preventing us from tripping over an assert.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reported-by: Michel Dänzer <michel.daenzer@amd.com>
Fixes: 8c1b9882b2e0 ("egl/dri2: Guard against invalid fourcc formats")
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
3 years agoradv: add missing support for protected memory properties
Samuel Pitoiset [Thu, 30 Aug 2018 09:43:47 +0000 (11:43 +0200)]
radv: add missing support for protected memory properties

Fixes Vulkan CTS CL#2849. Similar to the ANV driver.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: remove dead code in scan_shader_output_decl()
Samuel Pitoiset [Thu, 30 Aug 2018 08:33:37 +0000 (10:33 +0200)]
radv: remove dead code in scan_shader_output_decl()

Never used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: remove radv_shader_context::num_output_{clips,culls}
Samuel Pitoiset [Thu, 30 Aug 2018 08:33:00 +0000 (10:33 +0200)]
radv: remove radv_shader_context::num_output_{clips,culls}

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: adjust the cull dist mask in scan_shader_output_decl()
Samuel Pitoiset [Thu, 30 Aug 2018 08:30:54 +0000 (10:30 +0200)]
radv: adjust the cull dist mask in scan_shader_output_decl()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: get length of the clip/cull distances array from usage mask
Samuel Pitoiset [Thu, 30 Aug 2018 08:12:03 +0000 (10:12 +0200)]
radv: get length of the clip/cull distances array from usage mask

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: do not recompute the output usage mask for clipdist twice
Samuel Pitoiset [Thu, 30 Aug 2018 08:01:26 +0000 (10:01 +0200)]
radv: do not recompute the output usage mask for clipdist twice

The shader info pass takes care of this now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: gather the output usage mask for clip/cull distances correctly
Samuel Pitoiset [Thu, 30 Aug 2018 07:43:29 +0000 (09:43 +0200)]
radv: gather the output usage mask for clip/cull distances correctly

It's a special case because both are combined into a single array.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: add set_output_usage_mask() helper
Samuel Pitoiset [Thu, 30 Aug 2018 07:35:41 +0000 (09:35 +0200)]
radv: add set_output_usage_mask() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: fix passing clip/cull distances from VS to PS
Samuel Pitoiset [Wed, 29 Aug 2018 20:13:52 +0000 (22:13 +0200)]
radv: fix passing clip/cull distances from VS to PS

CTS doesn't test input clip/cull distances for the fragment
shader stage, which explains why this was totally broken. I
wrote a simple test locally that works now.

This fixes a crash with GTA V and DXVK.

Note that we are exporting unused parameters from the vertex
shader now, but this can't be optimized easily because we don't
keep the fragment shader info...

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107477
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoegl/wayland: do not leak wl_buffer when it is locked
Juan A. Suarez Romero [Thu, 30 Aug 2018 08:14:49 +0000 (10:14 +0200)]
egl/wayland: do not leak wl_buffer when it is locked

If color buffer is locked, do not set its wayland buffer to NULL;
otherwise it can not be freed later.

Rather, flag it in order to destroy it later on the release event.

v2: instruct release event to unlock only or free wl_buffer too (Daniel)

This also fixes dEQP-EGL.functional.swap_buffers_with_damage.* tests.

CC: Daniel Stone <daniel@fooishbar.org>
Reviewed-by: Daniel Stone <daniels@collabora.com>
3 years agoac/radeonsi: fix CIK copy max size
Dave Airlie [Wed, 29 Aug 2018 03:52:15 +0000 (13:52 +1000)]
ac/radeonsi: fix CIK copy max size

While adding transfer queues to radv, I started writing some tests,
the first test I wrote fell over copying a buffer larger than this
limit.

Checked AMDVLK and found the correct limit.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: fix regression in indirect input swizzles.
Dave Airlie [Fri, 31 Aug 2018 00:12:06 +0000 (01:12 +0100)]
radeonsi: fix regression in indirect input swizzles.

This fixes:
tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-dvec3.shader_test
since I reworked the 64-bit swizzles.

Fixes: bb17ae49ee2 (gallivm: allow to pass two swizzles into fetches.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: fix tess/gs fetchs for new swizzle.
Dave Airlie [Thu, 30 Aug 2018 23:27:44 +0000 (00:27 +0100)]
radeonsi: fix tess/gs fetchs for new swizzle.

I have piglit results from my machine, but I must have messed up,
and not built mesa in between properly.

Fixes: bb17ae49ee2 (gallivm: allow to pass two swizzles into fetches.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agomesa: ignore VAO IDs equal to 0 in glDeleteVertexArrays
Marek Olšák [Thu, 30 Aug 2018 19:14:46 +0000 (15:14 -0400)]
mesa: ignore VAO IDs equal to 0 in glDeleteVertexArrays

This fixes a firefox crash.

Fixes: 781a78914c798dc64005b37c6ca1224ce06803fc
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoRevert "intel/tools/aubwrite: Always use physical addresses for traces."
Kenneth Graunke [Thu, 30 Aug 2018 18:19:51 +0000 (11:19 -0700)]
Revert "intel/tools/aubwrite: Always use physical addresses for traces."

This reverts commit f8cfc7766016d0ff7d52953e7a992b1e77c521d0.

This appears to break intel_dump_gpu for Gen9 systems - I can load them
in the simulator, but nothing happens.  Reverting the patch makes the
simulator properly execute our commands and shaders again.

3 years agointel/nir: Lowering image loads and stores trashes all metadata
Jason Ekstrand [Thu, 30 Aug 2018 17:50:31 +0000 (12:50 -0500)]
intel/nir: Lowering image loads and stores trashes all metadata

This fixes the GL_ARB_fragment_shader_interlock piglit test on gen8
platforms where the lack of metadata dirtying was causing another pass
to accidentally delete a much needed loop.

https://bugs.freedesktop.org/show_bug.cgi?id=107745
Fixes: 37f7983bcca1 "intel/compiler: Do image load/store lowering..."
Jason Ekstrand <jason@jlekstrand.net> writes:
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoi965/screen: Allow modifiers on sRGB formats
Jason Ekstrand [Tue, 28 Aug 2018 20:25:23 +0000 (15:25 -0500)]
i965/screen: Allow modifiers on sRGB formats

This effectively reverts a26693493570a9d0f0fba1be617e01ee7bfff4db which
was a misguided attempt at protecting intel_query_dma_buf_modifiers from
invalid formats.  Unfortunately, in some internal EGL cases, we can get
an SRGB format validly in this function.  Rejecting such formats caused
us to not allow CCS in some cases where we should have been allowing it.
This regressed the performance of some SynMark tests as well as GfxBench
ALU2, Tessellation and Manhattan 3.0 tests

There's some question of whether or not we really should be using SRGB
"fourcc" formats that aren't actually in drm_foucc.h but there's not
much harm in allowing them through here.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107223
Fixes: a26693493570 "i965/screen: Return false for unsupported..."
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoegl/dri2: Guard against invalid fourcc formats
Jason Ekstrand [Tue, 28 Aug 2018 21:43:57 +0000 (16:43 -0500)]
egl/dri2: Guard against invalid fourcc formats

We already reject attempts to import images with invalid fourcc formats
but don't really guard the queries all that well.  This makes us error
out in any calls to eglQueryDmaBufModifiersEXT if the given format is
not a valid fourcc format.  We also add an assert to ensure that drivers
don't advertise any non-fourcc formats.

Cc: mesa-stable@lists.freedesktop.org
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoegl/dri2: Add a helper for the number of planes for a FOURCC format
Jason Ekstrand [Tue, 28 Aug 2018 21:31:22 +0000 (16:31 -0500)]
egl/dri2: Add a helper for the number of planes for a FOURCC format

This also serves as a convenient "is this a fourcc format" check as well
which we'll take advantage of in the next commit.

Cc: mesa-stable@lists.freedesktop.org
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agoradv/meta: Set num_components on image_store intrinsics
Jason Ekstrand [Thu, 30 Aug 2018 00:47:19 +0000 (19:47 -0500)]
radv/meta: Set num_components on image_store intrinsics

Now that image load/store intrinsics are variable-width, we need to set
num_components accordingly.  In 15d39f474b890, both glsl_to_nir and
spirv_to_nir were updated to properly set num_components but radv meta
was left behind.

Fixes: 15d39f474b890 "nir: Make image load/store intrinsics..."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agogallivm: Detect VSX separately from Altivec
Vicki Pfau [Sun, 19 Aug 2018 21:17:01 +0000 (14:17 -0700)]
gallivm: Detect VSX separately from Altivec

Previously gallivm would attempt to use VSX instructions on all systems
where it detected that Altivec is supported; however, VSX was added to
POWER long after Altivec, causing lots of crashes on older POWER/PPC
hardware, e.g. PPC Macs. By detecting VSX separately from Altivec we can
automatically disable it on hardware that supports Altivec but not VSX

Signed-off-by: Vicki Pfau <vi@endrift.com>
3 years agonv50: bump compat glsl level to same as core
Ilia Mirkin [Sun, 26 Aug 2018 21:47:12 +0000 (17:47 -0400)]
nv50: bump compat glsl level to same as core

Passes the compat piglits. I'm sure that there will be odd issues that
aren't caught by them, but at least it should basically work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonvc0: bump compat GLSL version to match core
Ilia Mirkin [Sun, 26 Aug 2018 18:21:39 +0000 (14:21 -0400)]
nvc0: bump compat GLSL version to match core

This passes the handful of tests in piglit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agoglsl: avoid lowering texcoord array except in simple cases
Ilia Mirkin [Sun, 26 Aug 2018 17:48:10 +0000 (13:48 -0400)]
glsl: avoid lowering texcoord array except in simple cases

With compat creeping up to geometry and tess shaders, lowering texcoord
accesses/writes becomes more complicated. Since it's an optimization
anyways, just avoid the complication for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agodocs: update calendar 18.2.0-rc5 is out, extend to 18.2.0-rc6
Andres Gomez [Thu, 30 Aug 2018 00:32:02 +0000 (03:32 +0300)]
docs: update calendar 18.2.0-rc5 is out, extend to 18.2.0-rc6

Signed-off-by: Andres Gomez <agomez@igalia.com>
3 years agost/mesa, gallium: add a workaround for No Mans Sky
Timothy Arceri [Wed, 29 Aug 2018 05:48:47 +0000 (15:48 +1000)]
st/mesa, gallium: add a workaround for No Mans Sky

The spec seems clear this is not allowed but the Nvidia binary
forces apps to add layout qualifiers so this works around the
issue for No Mans Sky until the CTS can be sorted out.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoglsl: add a mechanism to allow layout qualifiers on function params
Timothy Arceri [Wed, 29 Aug 2018 05:48:46 +0000 (15:48 +1000)]
glsl: add a mechanism to allow layout qualifiers on function params

The spec is quite clear this is not allowed:

    From Section 4.4. (Layout Qualifiers) of the GLSL 4.60 spec:

       "Layout qualifiers can appear in several forms of declaration.
       They can appear as part of an interface block definition or
       block member, as shown in the grammar in the previous section.
       They can also appear with just an interface-qualifier to establish
       layouts of other declarations made with that qualifier:

          layout-qualifier interface-qualifier ;

       Or, they can appear with an individual variable declared with
       an interface qualifier:

          layout-qualifier interface-qualifier declaration ;"

    From Section 4.10 (Memory Qualifiers) of the GLSL 4.60 spec:

       "Layout qualifiers cannot be used on formal function parameters,
       and layout qualification is not included in parameter matching."

However on the Nvidia binary driver they actually fail to compile
if image function params don't have a layout qualifier. This results
in applications such as No Mans Sky using layout qualifiers on params.

I've submitted a CTS test to expose this problem in the Nvidia driver
but until that is resolved this patch will help Mesa drivers work
around the issue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoglsl: skip stringification in preprocessor if in unreachable branch
Timothy Arceri [Wed, 29 Aug 2018 01:36:51 +0000 (11:36 +1000)]
glsl: skip stringification in preprocessor if in unreachable branch

This fixes compilation of some "No Mans Sky" shaders where the stringification
happens in branches intended for DX12.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoradv: Add missing checks in radv_get_image_format_properties.
Bas Nieuwenhuizen [Wed, 29 Aug 2018 15:04:25 +0000 (17:04 +0200)]
radv: Add missing checks in radv_get_image_format_properties.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agogallivm: allow to pass two swizzles into fetches.
Dave Airlie [Mon, 27 Aug 2018 01:03:41 +0000 (02:03 +0100)]
gallivm: allow to pass two swizzles into fetches.

This hijacks the top 16-bits of swizzle, to pass in the swizzle
for the second channel.

This fixes handling .yx swizzles of 64-bit values.

This should fixup radeonsi and llvmpipe.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: enable radeonsi_zerovram for No Mans Sky
Timothy Arceri [Fri, 24 Aug 2018 11:06:19 +0000 (21:06 +1000)]
radeonsi: enable radeonsi_zerovram for No Mans Sky

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: add radeonsi_zerovram driconfig option
Timothy Arceri [Fri, 24 Aug 2018 11:06:18 +0000 (21:06 +1000)]
radeonsi: add radeonsi_zerovram driconfig option

More and more games seem to require this so lets make it a config
option.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: enable GL 4.5 in compat profile
Timothy Arceri [Fri, 24 Aug 2018 11:06:17 +0000 (21:06 +1000)]
radeonsi: enable GL 4.5 in compat profile

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agomesa: enable ARB_direct_state_access in compat for GL3.1+
Timothy Arceri [Wed, 29 Aug 2018 02:40:12 +0000 (12:40 +1000)]
mesa: enable ARB_direct_state_access in compat for GL3.1+

We could enable it for lower versions of GL but this allows us
to just use the existing version/extension checks that are already
used by the core profile.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: add a thorough clear/copy_buffer benchmark
Marek Olšák [Thu, 2 Aug 2018 22:15:48 +0000 (18:15 -0400)]
radeonsi: add a thorough clear/copy_buffer benchmark

3 years agoradeonsi: let internal compute dispatches tune WAVES_PER_SH
Marek Olšák [Thu, 2 Aug 2018 20:37:17 +0000 (16:37 -0400)]
radeonsi: let internal compute dispatches tune WAVES_PER_SH

3 years agoradeonsi: add TGSI_SEMANTIC_CS_USER_DATA for reading up to 4 SGPRs with TGSI
Marek Olšák [Wed, 25 Jul 2018 05:37:21 +0000 (01:37 -0400)]
radeonsi: add TGSI_SEMANTIC_CS_USER_DATA for reading up to 4 SGPRs with TGSI

3 years agoradeonsi: add SI_QUERY_TIME_ELAPSED_SDMA_SI for measuring DMA on SI
Marek Olšák [Tue, 21 Aug 2018 04:46:53 +0000 (00:46 -0400)]
radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA_SI for measuring DMA on SI

DMA on SI doesn't support the timestamp packet, so it's emulated.

3 years agoradeonsi: add SI_QUERY_TIME_ELAPSED_SDMA for measuring SDMA performance
Marek Olšák [Tue, 24 Jul 2018 17:14:29 +0000 (13:14 -0400)]
radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA for measuring SDMA performance

3 years agoradeonsi: add flag L2_STREAM for minimal cache usage
Marek Olšák [Fri, 3 Aug 2018 00:33:06 +0000 (20:33 -0400)]
radeonsi: add flag L2_STREAM for minimal cache usage

3 years agogallium: add TGSI_MEMORY_STREAM_CACHE_POLICY
Marek Olšák [Wed, 25 Jul 2018 04:41:48 +0000 (00:41 -0400)]
gallium: add TGSI_MEMORY_STREAM_CACHE_POLICY

For internal radeonsi shaders.

3 years agointel/compiler: Remove surface_idx from brw_image_param
Jason Ekstrand [Fri, 17 Aug 2018 14:15:56 +0000 (09:15 -0500)]
intel/compiler: Remove surface_idx from brw_image_param

Now that the drivers are lowering to surface indices themselves, we no
longer need to push the surface index into the shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agointel: Use TXS for image_size when we have a typed surface
Jason Ekstrand [Thu, 16 Aug 2018 16:01:24 +0000 (11:01 -0500)]
intel: Use TXS for image_size when we have a typed surface

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoanv,i965: Lower away image derefs in the driver
Jason Ekstrand [Thu, 16 Aug 2018 21:23:10 +0000 (16:23 -0500)]
anv,i965: Lower away image derefs in the driver

Previously, the back-end compiler turn image access into magic uniform
reads and there was a complex contract between back-end compiler and
driver about setting up and filling out those params.  As of this
commit, both drivers now lower image_deref_load_param_intel intrinsics
to load_uniform intrinsics controlled by the driver and lower the other
image_deref_* intrinsics to image_* intrinsics which take an actual
binding table index.  There are still "magic" uniforms but they are now
added and controlled entirely by the driver and that contract no longer
spans components.

This also has the side-effect of making most image use compile-time
binding table indices.  Previously, all image access pulled the binding
table index from a uniform.  Part of the reason for this was that the
magic uniforms made it difficult to decouple binding table indices from
the uniforms and, since they are indexed completely differently
(especially in Vulkan), it was hard to pull them apart.  Now that the
driver is handling both, it's trivial to decouple the two and provide
actual binding table indices.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166872 -> 15164293 (-0.02%)
    instructions in affected programs: 115834 -> 113255 (-2.23%)
    helped: 191
    HURT: 0

    total cycles in shared programs: 571311495 -> 571196465 (-0.02%)
    cycles in affected programs: 4757115 -> 4642085 (-2.42%)
    helped: 73
    HURT: 67

    total spills in shared programs: 10951 -> 10926 (-0.23%)
    spills in affected programs: 742 -> 717 (-3.37%)
    helped: 7
    HURT: 0

    total fills in shared programs: 22226 -> 22201 (-0.11%)
    fills in affected programs: 1146 -> 1121 (-2.18%)
    helped: 7
    HURT: 0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir: Add handle/index-based image intrinsics
Jason Ekstrand [Thu, 16 Aug 2018 20:11:44 +0000 (15:11 -0500)]
nir: Add handle/index-based image intrinsics

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir: Use a bitfield for image access qualifiers
Jason Ekstrand [Thu, 16 Aug 2018 20:11:12 +0000 (15:11 -0500)]
nir: Use a bitfield for image access qualifiers

This commit expands the current memory access enum to contain the extra
two bits provided for images.  We choose to follow the SPIR-V convention
of NonReadable and NonWriteable because readonly implies that you *can*
read so readonly + writeonly doesn't make as much sense as NonReadable +
NonWriteable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoglsl/link,i965: Make ImageAccess four-state
Jason Ekstrand [Thu, 16 Aug 2018 19:31:28 +0000 (14:31 -0500)]
glsl/link,i965: Make ImageAccess four-state

The GLSL spec allows you to set both the "readonly" and "writeonly"
qualifiers on images to indicate that it can only be used with
imageSize.  However, we had no way of representing this int he linked
shader and flagged it as GL_READ_ONLY.  This is good from a "does it use
this buffer?" perspective but not from a format and access lowering
perspective.  By using GL_NONE for if "readonly" and "writeonly" are
both set, we can detect this case in the driver and handle it correctly.

Nothing currently relies on the type of surface in the "readonly" +
"writeonly" case but that's about to change.  i965 is the only drier
which uses the ImageAccess field and gl_bindless_image::access is
currently unused.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agointel/compiler: Use two components for 1D array image sizes
Jason Ekstrand [Thu, 16 Aug 2018 15:16:41 +0000 (10:16 -0500)]
intel/compiler: Use two components for 1D array image sizes

Having the array length component stored in .z was a small convenience
for the ISL image param filling code and an annoyance in the NIR
lowering code.  The only convenience of treating 1D arrays like 2D
arrays in the lowering code is in the address calculation code so let's
put all the complexity there as well.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoisl: Use the view array length for the image size
Jason Ekstrand [Thu, 16 Aug 2018 15:12:16 +0000 (10:12 -0500)]
isl: Use the view array length for the image size

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agointel/compiler: Do image load/store lowering to NIR
Jason Ekstrand [Sat, 27 Jan 2018 21:19:57 +0000 (13:19 -0800)]
intel/compiler: Do image load/store lowering to NIR

This commit moves our storage image format conversion codegen into NIR
instead of doing it in the back-end.  This has the advantage of letting
us run it through NIR's optimizer which is pretty effective at shrinking
things down.  In the common case of rgba8, the number of instructions
emitted after NIR is done with it is half of what it was with the
lowering happening in the back-end.  On the downside, the back-end's
lowering is able to directly use predicates and the NIR lowering has to
use IFs.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166910 -> 15166872 (<.01%)
    instructions in affected programs: 5895 -> 5857 (-0.64%)
    helped: 15
    HURT: 0

Clearly, we don't have that much image_load_store happening in the
shaders in shader-db....

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/types: Add a wrapper for coordinate_components
Jason Ekstrand [Thu, 16 Aug 2018 15:22:32 +0000 (10:22 -0500)]
nir/types: Add a wrapper for coordinate_components

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoanv/pipeline: Remove dead image loads in lower_input_attacnments
Jason Ekstrand [Wed, 15 Aug 2018 19:04:25 +0000 (14:04 -0500)]
anv/pipeline: Remove dead image loads in lower_input_attacnments

Dead code will get rid of them eventually but it's better if they're
just gone so we guarantee they won't trip up later passes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir: Make image load/store intrinsics variable-width
Jason Ekstrand [Tue, 14 Aug 2018 19:03:05 +0000 (14:03 -0500)]
nir: Make image load/store intrinsics variable-width

Instead of requiring 4 components, this allows them to potentially use
fewer.  Both the SPIR-V and GLSL paths still generate vec4 intrinsics so
drivers which assume 4 components should be safe.  However, we want to
be able to shrink them for i965.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/format_convert: Fix a bitmask in unpack_11f11f10f
Jason Ekstrand [Thu, 16 Aug 2018 14:21:10 +0000 (09:21 -0500)]
nir/format_convert: Fix a bitmask in unpack_11f11f10f

Fixes: 4e337b42f9a2 "nir/format_convert: Add pack/unpack for R11F_G11F_B10F"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/format_convert: Rename pack_r11g11b10f to pack_11f11f10f
Jason Ekstrand [Mon, 13 Aug 2018 22:31:19 +0000 (17:31 -0500)]
nir/format_convert: Rename pack_r11g11b10f to pack_11f11f10f

This matches the unpack function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/format_convert: Add [us]norm conversion helpers
Jason Ekstrand [Mon, 13 Aug 2018 21:13:50 +0000 (16:13 -0500)]
nir/format_convert: Add [us]norm conversion helpers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/format_convert: Rename nir_format_bitcast_uint_vec
Jason Ekstrand [Mon, 13 Aug 2018 19:57:22 +0000 (14:57 -0500)]
nir/format_convert: Rename nir_format_bitcast_uint_vec

We have a name for that, it's called a uvec.  This just makes the
function name a bit shorter.  While we're here, we also add an assert
for one of the assumptions this function makes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/format_convert: Add vec mask and sign-extend helpers
Jason Ekstrand [Mon, 13 Aug 2018 17:04:25 +0000 (12:04 -0500)]
nir/format_convert: Add vec mask and sign-extend helpers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/format_convert: Add support for unpacking signed integers
Jason Ekstrand [Mon, 13 Aug 2018 16:41:41 +0000 (11:41 -0500)]
nir/format_convert: Add support for unpacking signed integers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/opcodes: Make unpack_half_2x16_split_* variable-width
Jason Ekstrand [Wed, 15 Aug 2018 16:58:50 +0000 (11:58 -0500)]
nir/opcodes: Make unpack_half_2x16_split_* variable-width

There is nothing inherent about these opcodes that requires them to only
take scalars.  It's very convenient if we let them take vectors as well.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/algebraic: Add some max/min optimizations
Jason Ekstrand [Wed, 15 Aug 2018 09:29:42 +0000 (04:29 -0500)]
nir/algebraic: Add some max/min optimizations

Found by inspection.  This doesn't help much now but we'll see this
pattern with images if you load UNORM and then store UNORM.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166916 -> 15166910 (<.01%)
    instructions in affected programs: 761 -> 755 (-0.79%)
    helped: 6
    HURT: 0

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/algebraic: Add more extract_[iu](8|16) optimizations
Jason Ekstrand [Tue, 14 Aug 2018 19:37:39 +0000 (14:37 -0500)]
nir/algebraic: Add more extract_[iu](8|16) optimizations

This adds the "(a << N) >> M" family of mask or sign-extensions.  Not a
huge win right now but this pattern will soon be generated by NIR format
lowering code.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166918 -> 15166916 (<.01%)
    instructions in affected programs: 36 -> 34 (-5.56%)
    helped: 2
    HURT: 0

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agonir/algebraic: Be more careful converting ushr to extract_u8/16
Jason Ekstrand [Tue, 14 Aug 2018 20:10:22 +0000 (15:10 -0500)]
nir/algebraic: Be more careful converting ushr to extract_u8/16

If it's not the right bit-size, it may not actually be the correct
extraction.  For now, we'll only worry about 32-bit versions.

Fixes: 905ff8619824 "nir: Recognize open-coded extract_u16"
Fixes: 76289fbfa84a "nir: Recognize open-coded extract_u8"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agointel/tools: new i965_disasm tool
Sagar Ghuge [Wed, 29 Aug 2018 17:52:41 +0000 (10:52 -0700)]
intel/tools: new i965_disasm tool

Adds a new i965 instruction disassemble tool

v2: 1) fix a few nits (Matt Turner)
    2) Remove i965_disasm header (Matt Turner)

v3: 1) Redirect output to correct file descriptors (Matt Turner)
    2) Refactor code (Matt Turner)
    3) Use better formatting style (Matt Turner)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
3 years agost/mesa: Disable blending for integer formats.
Kenneth Graunke [Sat, 25 Aug 2018 06:45:27 +0000 (23:45 -0700)]
st/mesa: Disable blending for integer formats.

Blending isn't valid for integer formats.  Rather than having drivers
worry about this, just disable blending in this case.  This hopefully
will increase hits in the CSO cache as well, by eliminating most of the
meaningless fields in this case.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agosvga: add missing switch cases for shadow textures
Brian Paul [Fri, 24 Aug 2018 02:48:04 +0000 (20:48 -0600)]
svga: add missing switch cases for shadow textures

This doesn't seem to make any difference in testing, but it fixes a
failed assertion when dumping sm3 shaders.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
3 years agosvga: fix vgpu9 sprite coordinate bug
Brian Paul [Thu, 23 Aug 2018 15:25:15 +0000 (09:25 -0600)]
svga: fix vgpu9 sprite coordinate bug

Setting GL_POINT_SPRITE_COORD_ORIGIN to GL_LOWER_LEFT did not work for
vgpu9.  We can use the rasterizer sprite_coord_enable bitfield as-is.
We need to index into it using the TGSI semantic index, not the
register index.

This fixes the Piglit fbo-gl_pointcoord and glsl-fs-pointcoord tests.

Testing done: Piglit, Mesa sprite demos

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
3 years agosvga: fix PIPE_TEXTURE_RECT/BUFFER const buffer issue
Brian Paul [Wed, 22 Aug 2018 17:11:22 +0000 (11:11 -0600)]
svga: fix PIPE_TEXTURE_RECT/BUFFER const buffer issue

The flag_rect and flag_buffer fields didn't sufficiently capture
the state changes needed for those resource types.  For example,
if a texture binding was changed from a 500x500 rect texture to a
400x400 rect texture we didn't set SVGA_NEW_TEXTURE_CONSTS.  But
we need to do that to emit the new texcoord scale factors to the
constant buffers.  Rather than track the sizes of all bound
resources, just set the flag if the resource is a rect.  Same
story with texture buffers.

Also, since rect/buffer textures are usable with VS/GS shaders,
add SVGA_NEW_TEXTURE_CONSTS to the flags we check for emitting
VS/GS constants.

This seems to help with XFCE / xfwm4 desktop scaling.
VMware issue 2156696.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
3 years agosvga: minor improvements in svga_state_constants.c
Brian Paul [Fri, 24 Aug 2018 21:17:20 +0000 (15:17 -0600)]
svga: minor improvements in svga_state_constants.c

Add const qualifiers.  Add 'f' suffix on floats to avoid double
promotion.

Remove unneeded shader type assertion since the switch statement
handled it already.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
3 years agoanv: Free the app and engine name
Jason Ekstrand [Wed, 29 Aug 2018 15:06:56 +0000 (10:06 -0500)]
anv: Free the app and engine name

Fixes: 8c048af5890d4 "anv: Copy the appliation info into the instance"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agonv50/ir: silence partitionLoadStore() unused function warning
Rhys Kidd [Fri, 10 Aug 2018 16:44:37 +0000 (12:44 -0400)]
nv50/ir: silence partitionLoadStore() unused function warning

Move this now-unused function into the existing comment block, which was its only prior use.

../../../../../src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:2645:1: warning:
      unused function 'partitionLoadStore' [-Wunused-function]
partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)

Fixes: ("86e4440361 nouveau: codegen: Disable more old resource handling code")
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agoglsl/linker: Link all out vars from a shader objects on a single stage
vadym.shovkoplias [Tue, 28 Aug 2018 07:32:18 +0000 (10:32 +0300)]
glsl/linker: Link all out vars from a shader objects on a single stage

During intra stage linking some out variables can be dropped because
it is not used in a shader with the main function. But these out vars
can be referenced on later stages which can lead to further linking
errors.

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105731

3 years agoanv: blorp: support multiple aspect blits
Lionel Landwerlin [Tue, 28 Aug 2018 10:16:33 +0000 (11:16 +0100)]
anv: blorp: support multiple aspect blits

Newer blit tests are enabling depth&stencils blits. We currently don't
support it but can do by iterating over the aspects masks (copy some
logic from the CopyImage function).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9f44745eca0e41 ("anv: Use blorp to implement VkBlitImage")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agomesa: allow GL_UNSIGNED_BYTE type for SNORM reads
Tapani Pälli [Mon, 27 Aug 2018 11:40:41 +0000 (14:40 +0300)]
mesa: allow GL_UNSIGNED_BYTE type for SNORM reads

OpenGL ES spec states:
   "For normalized fixed-point rendering surfaces, the combination format
    RGBA and type UNSIGNED_BYTE is accepted."

This fixes following failing VK-GL-CTS tests:

   KHR-GLES3.packed_pixels.pbo_rectangle.rgba8_snorm
   KHR-GLES3.packed_pixels.rectangle.rgba8_snorm
   KHR-GLES3.packed_pixels.varied_rectangle.rgba8_snorm

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
https://bugs.freedesktop.org/show_bug.cgi?id=107658
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Andres Gomez <agomez@igalia.com>
3 years agonir: add loop unroll support for wrapper loops
Timothy Arceri [Sat, 7 Jul 2018 07:56:26 +0000 (17:56 +1000)]
nir: add loop unroll support for wrapper loops

This adds support for unrolling the classic

    do {
        // ...
    } while (false)

that is used to wrap multi-line macros. GLSL IR also wraps switch
statements in a loop like this.

shader-db results IVB:

total loops in shared programs: 2515 -> 2512 (-0.12%)
loops in affected programs: 33 -> 30 (-9.09%)
helped: 3
HURT: 0

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir/opt_loop_unroll: Remove unneeded phis if we make progress
Timothy Arceri [Wed, 11 Jul 2018 00:50:16 +0000 (10:50 +1000)]
nir/opt_loop_unroll: Remove unneeded phis if we make progress

Now that SSA values can be derefs and they have special rules, we have
to be a bit more careful about our LCSSA phis.  In particular, we need
to clean up in case LCSSA ended up creating a phi node for a deref.
This avoids validation issues with some CTS tests with the following
patch, but its possible this we could also see the same problem with
the existing unrolling passes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir: add complex_loop bool to loop info
Timothy Arceri [Sat, 7 Jul 2018 02:09:26 +0000 (12:09 +1000)]
nir: add complex_loop bool to loop info

In order to be sure loop_terminator_list is an accurate
representation of all the jumps in the loop we need to be sure we
didn't encounter any other complex behaviour such as continues,
nested breaks, etc during analysis.

This will be used in the following patch.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir: always attempt to find loop terminators
Timothy Arceri [Sat, 7 Jul 2018 02:02:08 +0000 (12:02 +1000)]
nir: always attempt to find loop terminators

This will help later patches with unrolling loops that end with a
break i.e. loops the always exit on their first interation.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI
Marek Olšák [Tue, 28 Aug 2018 18:39:09 +0000 (14:39 -0400)]
ac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI

This fixes VM faults and corruption.

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoi965/vec4: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1
Ian Romanick [Sat, 25 Aug 2018 00:24:36 +0000 (17:24 -0700)]
i965/vec4: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1

No shader-db changes on any Intel platform.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoi965/fs: Emit BRW_AOP_INC or BRW_AOP_DEC for imageAtomicAdd of +1 or -1
Ian Romanick [Sat, 25 Aug 2018 00:41:01 +0000 (17:41 -0700)]
i965/fs: Emit BRW_AOP_INC or BRW_AOP_DEC for imageAtomicAdd of +1 or -1

v2: Refactor selection of atomic opcode to a separate function.
Suggested by Jason.

No changes on any other Intel platforms.

Skylake
total instructions in shared programs: 14304261 -> 14304241 (<.01%)
instructions in affected programs: 1625 -> 1605 (-1.23%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 5.00 x̃: 5
helped stats (rel) min: 1.01% max: 14.29% x̄: 5.86% x̃: 4.07%
95% mean confidence interval for instructions value: -10.66 0.66
95% mean confidence interval for instructions %-change: -15.91% 4.19%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 527531226 -> 527531194 (<.01%)
cycles in affected programs: 92204 -> 92172 (-0.03%)
helped: 2
HURT: 0

Haswell and Broadwell had similar results. (Broadwell shown)
total instructions in shared programs: 14615730 -> 14615710 (<.01%)
instructions in affected programs: 1838 -> 1818 (-1.09%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 5.00 x̃: 5
helped stats (rel) min: 0.89% max: 13.04% x̄: 5.37% x̃: 3.78%
95% mean confidence interval for instructions value: -10.66 0.66
95% mean confidence interval for instructions %-change: -14.59% 3.85%
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/fs: Refactor image atomics to be a bit more like other atomics
Ian Romanick [Sat, 25 Aug 2018 00:23:26 +0000 (17:23 -0700)]
i965/fs: Refactor image atomics to be a bit more like other atomics

This greatly simplifies the next patch.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoi965/fs: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1
Ian Romanick [Thu, 23 Aug 2018 03:31:11 +0000 (20:31 -0700)]
i965/fs: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1

Funny story... a single shader was hurt for instructions, spills, fills.
That same shader was also the most helped for cycles.  #GPUsAreWeird

No changes on any other Intel platform.

v2: Refactor selection of atomic opcode to a separate function.
Suggested by Jason.

Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14304116 -> 14304261 (<.01%)
instructions in affected programs: 12776 -> 12921 (1.13%)
helped: 19
HURT: 1
helped stats (abs) min: 1 max: 16 x̄: 2.32 x̃: 1
helped stats (rel) min: 0.05% max: 7.27% x̄: 0.92% x̃: 0.55%
HURT stats (abs)   min: 189 max: 189 x̄: 189.00 x̃: 189
HURT stats (rel)   min: 4.87% max: 4.87% x̄: 4.87% x̃: 4.87%
95% mean confidence interval for instructions value: -12.83 27.33
95% mean confidence interval for instructions %-change: -1.57% 0.31%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 527552861 -> 527531226 (<.01%)
cycles in affected programs: 1459195 -> 1437560 (-1.48%)
helped: 16
HURT: 2
helped stats (abs) min: 2 max: 21328 x̄: 1353.69 x̃: 6
helped stats (rel) min: 0.01% max: 5.29% x̄: 0.36% x̃: 0.03%
HURT stats (abs)   min: 12 max: 12 x̄: 12.00 x̃: 12
HURT stats (rel)   min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -3699.81 1295.92
95% mean confidence interval for cycles %-change: -0.94% 0.30%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 8025 -> 8033 (0.10%)
spills in affected programs: 208 -> 216 (3.85%)
helped: 1
HURT: 1

total fills in shared programs: 10989 -> 11040 (0.46%)
fills in affected programs: 444 -> 495 (11.49%)
helped: 1
HURT: 1

Ivy Bridge
total instructions in shared programs: 11709181 -> 11709153 (<.01%)
instructions in affected programs: 3505 -> 3477 (-0.80%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 23 x̄: 9.33 x̃: 4
helped stats (rel) min: 0.11% max: 1.16% x̄: 0.63% x̃: 0.61%

total cycles in shared programs: 254741126 -> 254738801 (<.01%)
cycles in affected programs: 919067 -> 916742 (-0.25%)
helped: 3
HURT: 0
helped stats (abs) min: 21 max: 2144 x̄: 775.00 x̃: 160
helped stats (rel) min: 0.03% max: 0.90% x̄: 0.32% x̃: 0.03%

total spills in shared programs: 4536 -> 4533 (-0.07%)
spills in affected programs: 40 -> 37 (-7.50%)
helped: 1
HURT: 0

total fills in shared programs: 4819 -> 4813 (-0.12%)
fills in affected programs: 94 -> 88 (-6.38%)
helped: 1
HURT: 0

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agointel/compiler: Silence unused parameter warnings in brw_eu.h
Ian Romanick [Sat, 25 Aug 2018 00:24:59 +0000 (17:24 -0700)]
intel/compiler: Silence unused parameter warnings in brw_eu.h

All of the other brw_*_desc functions take a devinfo parameter, and all
of the others at least have an assert that uses it.  Keep the parameter,
but mark it as unused.

Silences 37 warnings like:

In file included from src/intel/common/gen_disasm.c:27:0:
src/intel/compiler/brw_eu.h: In function ‘brw_pixel_interp_desc’:
src/intel/compiler/brw_eu.h:377:53: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
 brw_pixel_interp_desc(const struct gen_device_info *devinfo,
                                                     ^~~~~~~

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
3 years agoi965: enable AMD_depth_clamp_separate
Sagar Ghuge [Tue, 21 Aug 2018 21:28:17 +0000 (14:28 -0700)]
i965: enable AMD_depth_clamp_separate

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoi965: add functional changes for AMD_depth_clamp_separate
Sagar Ghuge [Tue, 21 Aug 2018 21:25:17 +0000 (14:25 -0700)]
i965: add functional changes for AMD_depth_clamp_separate

Gen >= 9 have ability to control clamping of depth values separately at
near and far plane.

z_w is clamped to the range [min(n,f), 0] if clamping at near plane is
enabled, [0, max(n,f)] if clamping at far plane is enabled and [min(n,f)
max(n,f)] if clamping at both plane is enabled.

v2: 1) Use better coding style (Ian Romanick)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agomesa: add EXTRA_EXT for AMD_depth_clamp_separate
Sagar Ghuge [Fri, 27 Jul 2018 22:03:54 +0000 (15:03 -0700)]
mesa: add EXTRA_EXT for AMD_depth_clamp_separate

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agomesa: add support for GL_AMD_depth_clamp_separate tokens
Sagar Ghuge [Tue, 21 Aug 2018 20:40:55 +0000 (13:40 -0700)]
mesa: add support for GL_AMD_depth_clamp_separate tokens

_mesa_set_enable() and _mesa_IsEnabled() extended to accept new two
tokens GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD.

v2: Remove unnecessary parentheses (Marek Olsak)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agomesa: Add support for AMD_depth_clamp_separate
Sagar Ghuge [Fri, 27 Jul 2018 21:55:57 +0000 (14:55 -0700)]
mesa: Add support for AMD_depth_clamp_separate

Enable _mesa_PushAttrib() and _mesa_PopAttrib() to handle
GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD tokens.

Remove DepthClamp, because DepthClampNear + DepthClampFar replaces it,
as suggested by Marek Olsak.

Driver that enables AMD_depth_clamp_separate will only ever look at
DepthClampNear and DepthClampFar, as suggested by Ian Romanick.

v2: 1) Remove unnecessary parentheses (Marek Olsak)
    2) if AMD_depth_clamp_separate is unsupported, TEST_AND_UPDATE
       GL_DEPTH_CLAMP only (Marek Olsak)
    3) Clamp against near and far plane separately (Marek Olsak)
    4) Clip point separately for near and far Z clipping plane (Marek
       Olsak)

v3: Clamp raster position zw to the range [min(n,f), 0] for near plane
    and [0, max(n,f)] for far plane (Marek Olsak)

v4: Use MIN2 and MAX2 instead of CLAMP (Marek Olsak)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agomesa: Add types for AMD_depth_clamp_separate.
Sagar Ghuge [Fri, 27 Jul 2018 03:08:44 +0000 (20:08 -0700)]
mesa: Add types for AMD_depth_clamp_separate.

Add some basic types and storage for the AMD_depth_clamp_separate
extension.

v2: 1) Drop unnecessary definition (Marek Olsak)
    2) Expose extension in compatibility profile (Marek Olsak)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoglapi: define AMD_depth_clamp_separate
Sagar Ghuge [Fri, 27 Jul 2018 21:42:36 +0000 (14:42 -0700)]
glapi: define AMD_depth_clamp_separate

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoanv: Claim to support depthBounds for ID games
Jason Ekstrand [Tue, 30 Jan 2018 02:41:15 +0000 (18:41 -0800)]
anv: Claim to support depthBounds for ID games

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agoanv: Copy the appliation info into the instance
Jason Ekstrand [Tue, 30 Jan 2018 02:12:04 +0000 (18:12 -0800)]
anv: Copy the appliation info into the instance

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agovulkan/alloc: Add a vk_strdup helper
Jason Ekstrand [Tue, 30 Jan 2018 02:11:38 +0000 (18:11 -0800)]
vulkan/alloc: Add a vk_strdup helper

Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
3 years agomeson: Actually load translation files
Dylan Baker [Fri, 24 Aug 2018 14:05:36 +0000 (07:05 -0700)]
meson: Actually load translation files

Currently we run the script but don't actually load any files, even in a
tarball where they exist.

Fixes: 3218056e0eb375eeda470058d06add1532acd6d4
       ("meson: Build i965 and dri stack")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
3 years agonir: Remove outdated comment
Caio Marcelo de Oliveira Filho [Mon, 27 Aug 2018 22:18:10 +0000 (15:18 -0700)]
nir: Remove outdated comment

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965: Add INTEL_fragment_shader_ordering support.
Kevin Rogovin [Mon, 27 Aug 2018 06:54:24 +0000 (09:54 +0300)]
i965: Add INTEL_fragment_shader_ordering support.

Adds suppport for INTEL_fragment_shader_ordering. We achieve
the fragment ordering by using the same instruction as for
beginInvocationInterlockARB() which is by issuing a memory
fence via sendc.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>