mesa.git
3 years agoetnaviv: enable full overwrite in a few more cases
Lucas Stach [Wed, 14 Nov 2018 13:56:59 +0000 (14:56 +0100)]
etnaviv: enable full overwrite in a few more cases

Take into account the render target format when checking if the color
mask affects all channels of the RT. This allows to enable full
overwrite in a few cases where a non-alpha format is used.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
3 years agonir: avoid uninitialized variable warning
Timothy Arceri [Sun, 6 Jan 2019 23:33:43 +0000 (10:33 +1100)]
nir: avoid uninitialized variable warning

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109231

3 years agost/glsl: refactor st_link_nir()
Timothy Arceri [Wed, 2 Jan 2019 23:03:05 +0000 (10:03 +1100)]
st/glsl: refactor st_link_nir()

The functional change here is moving the nir_lower_io_to_scalar_early()
calls inside st_nir_link_shaders() and moving the st_nir_opts() call
after the call to nir_lower_io_arrays_to_elements().

This fixes a bug with the following piglit test due to the current code
not cleaning up dead code after we lower arrays. This was causing an
assert in the new duplicate varyings link time opt introduced in
70be9afccb23.

tests/spec/glsl-1.10/execution/vsfs-unused-array-member.shader_test

Moving the nir_lower_io_to_scalar_early() calls also allows us to tidy
up the code a little and merge some loops.

Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agov3d: Use the core tex lowering.
Eric Anholt [Thu, 20 Dec 2018 17:43:43 +0000 (09:43 -0800)]
v3d: Use the core tex lowering.

Even without any clever optimization on the unpack operations, this gives
us a useful value for the channels read field, which we can use to avoid
ldtmu instructions to the no-op register.

instructions in affected programs: 890712 -> 881974 (-0.98%)

3 years agonir: Add nir_lower_tex options to lower sampler return formats.
Eric Anholt [Wed, 19 Dec 2018 21:53:39 +0000 (13:53 -0800)]
nir: Add nir_lower_tex options to lower sampler return formats.

I've been doing this in the nir-to-vir and nir-to-qir backends of v3d and
vc4, but nir could potentially do some useful stuff for us (like avoiding
unpack/repacks) if we give it the information.

v2: Skip lowering for txs/query_levels
v3: Fix a crash on old-style shadow
v4: Rename to tex_packing, use nir_format_unpack_sint/uint helpers, pack
    the enum.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir: Allow nir_format_unpack_int/sint to unpack larger values.
Eric Anholt [Wed, 2 Jan 2019 22:50:20 +0000 (14:50 -0800)]
nir: Allow nir_format_unpack_int/sint to unpack larger values.

For V3D, I want to unpack 4-16-bit packed integers for 8 and 16-bit
integer samplers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agointel/blorp: Be more conservative about copying clear colors
Jason Ekstrand [Fri, 4 Jan 2019 17:32:40 +0000 (11:32 -0600)]
intel/blorp: Be more conservative about copying clear colors

In 92eb5bbc68d7324 we attempted to avoid copying clear colors whenever
we weren't doing a resolve.  However, this broke MSAA resolves because
we need the clear color in the source.  This patch makes blorp much more
conservative such that it only avoids the clear color copy if either
aux_usage == NONE or it's explicitly doing a fast-clear.

Fixes: 92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
3 years agov3d: Stop scalarizing our uniform loads.
Eric Anholt [Thu, 3 Jan 2019 19:38:57 +0000 (11:38 -0800)]
v3d: Stop scalarizing our uniform loads.

We can pull a whole vector in a single indirect load.  This saves a bunch
of round-trips to the TMU, instructions for setting up multiple loads,
references to the UBO base in the uniforms, and apparently manages to
reduce register pressure as well.

instructions in affected programs: 3086665 -> 2454967 (-20.47%)
uniforms in affected programs: 919581 -> 721039 (-21.59%)
threads in affected programs: 1710 -> 3420 (100.00%)
spills in affected programs: 596 -> 522 (-12.42%)
fills in affected programs: 680 -> 562 (-17.35%)

Improves 3dmmes performance by 2.29312% +/- 0.139825% (n=5)

3 years agov3d: Do UBO loads a vector at a time.
Eric Anholt [Thu, 3 Jan 2019 20:13:18 +0000 (12:13 -0800)]
v3d: Do UBO loads a vector at a time.

In the process of adding support for SSBOs and CS shared vars, I ended up
needing a helper function for doing TMU general ops.  This helper can be
that starting point, and saves us a bunch of round-trips to the TMU by
loading a vector at a time.

3 years agov3d: Remove dead switch cases and comments from v3d_nir_lower_io.
Eric Anholt [Thu, 3 Jan 2019 19:31:37 +0000 (11:31 -0800)]
v3d: Remove dead switch cases and comments from v3d_nir_lower_io.

Moving things to NIR left this mess around.  All we lower now is uniforms.

3 years agov3d: Fix up VS output setup during precompiles.
Eric Anholt [Thu, 3 Jan 2019 06:48:29 +0000 (22:48 -0800)]
v3d: Fix up VS output setup during precompiles.

I noticed that a VS I was debugging was missing all of its output stores
-- outputs_written was for POS, VAR0, VAR3, while the shader's variables
were POS, VAR9, and VAR12.  I'm not sure what outputs_written is supposed
to be doing here, but we can just walk the declared variables and avoid
both this bug and the emission of extra stvpms for less-than-vec4
varyings.

3 years agov3d: Reinstate the new shader-db output after v3d_compile() refactor.
Eric Anholt [Thu, 3 Jan 2019 01:34:11 +0000 (17:34 -0800)]
v3d: Reinstate the new shader-db output after v3d_compile() refactor.

I misplaced it in the rebase conflicts.

3 years agonir: remove dead code from copy_prop_vars
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 23:23:28 +0000 (15:23 -0800)]
nir: remove dead code from copy_prop_vars

When copy_prop_vars also took care of dead write handling, intrin was
used as part of store_to_entry.  Now it isn't, so this assignment
isn't used really used.  Add a comment clarifying what happens to
intrin.

Fixes: 4dfa7adc100 "nir: Remove handling of dead writes from copy_prop_vars"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965: add CS stall on VF invalidation workaround
Lionel Landwerlin [Thu, 3 Jan 2019 16:18:48 +0000 (16:18 +0000)]
i965: add CS stall on VF invalidation workaround

Even with the previous commit, hangs are still happening. The problem
there is that the VF cache invalidate do happen immediately without
waiting for previous rendering to complete. What happens is that we
invalidate the cache the moment the PIPE_CONTROL is parsed but we
still have old rendering in the pipe which continues to pull data into
the cache with the old high address bits. The later rendering with the
new high address bits then doesn't have the clean cache that it
expects/needs.

v2: Update commit message/explanation with Jason's

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072

3 years agoi965: include draw_params/derived_draw_params for VF cache workaround
Lionel Landwerlin [Thu, 3 Jan 2019 16:17:04 +0000 (16:17 +0000)]
i965: include draw_params/derived_draw_params for VF cache workaround

These buffers are using VB slots and should be included in the
workaround decision.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072

3 years agointel/blorp: emit VF caching workaround before 3DSTATE_VERTEX_BUFFERS
Lionel Landwerlin [Thu, 3 Jan 2019 16:14:50 +0000 (16:14 +0000)]
intel/blorp: emit VF caching workaround before 3DSTATE_VERTEX_BUFFERS

Probably no difference but it's nice to have i965 & blorp emit things
in the same order.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoi965: limit VF caching workaround to gen8/9/10
Lionel Landwerlin [Thu, 3 Jan 2019 16:13:14 +0000 (16:13 +0000)]
i965: limit VF caching workaround to gen8/9/10

Documentation of the 3DSTATE_VERTEX_BUFFERS packet says this is only
needed before ICL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
3 years agoglsl/linker: complete documentation for assign_attribute_or_color_locations
Andres Gomez [Wed, 2 Jan 2019 13:21:17 +0000 (15:21 +0200)]
glsl/linker: complete documentation for assign_attribute_or_color_locations

Commit 27f1298b9d9 ("glsl/linker: validate attribute aliasing before optimizations")
forgot to complete the documentation.

Cc: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agovirgl: remove empty file
Gurchetan Singh [Thu, 3 Jan 2019 00:55:34 +0000 (16:55 -0800)]
virgl: remove empty file

Fixes: 174f53 ("virgl: consolidate transfer code")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
3 years agovirgl: don't flush an empty range
Gurchetan Singh [Fri, 28 Dec 2018 23:07:25 +0000 (00:07 +0100)]
virgl: don't flush an empty range

Otherwise, the gl-1.0-long-dlist Piglit test crashes.

Fixes: db7757 ("virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BIT")
Reported by airlied@

v2: Exit on any invalid range (Erik)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109190
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Jakob Bornecrantz <jakob@collabora.com>
3 years agodocs: advertise distro-provided meson cross-files
Eric Engestrom [Thu, 3 Jan 2019 16:01:18 +0000 (16:01 +0000)]
docs: advertise distro-provided meson cross-files

Hopefully we can kick start the revolution and other distros will start
providing them as well :)

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agodocs: fix the meson aarch64 cross-file
Eric Engestrom [Thu, 3 Jan 2019 15:44:42 +0000 (15:44 +0000)]
docs: fix the meson aarch64 cross-file

`gcc-ar` is preferred over the generic `ar`, and the `arm` family is
for 32-bit ARM [1].

[1] https://mesonbuild.com/Reference-tables.html#cpu-families

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
3 years agovirgl/vtest: Use default socket name from protocol header
Jakob Bornecrantz [Mon, 12 Nov 2018 14:55:43 +0000 (14:55 +0000)]
virgl/vtest: Use default socket name from protocol header

No functional change as the socket name is the same,
just removing the double definition of the path.

Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Signed-off-by: Jakob Bornecrantz <jakob@collabora.com>
3 years agofreedreno: fix staging resource size for arrays
Rob Clark [Wed, 2 Jan 2019 18:24:31 +0000 (13:24 -0500)]
freedreno: fix staging resource size for arrays

A 2d-array texture (for example), should get the # of array elements
from box->depth, rather than depth0 which is minified.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texture.sampler2darray_bias_float_fragment
with tiled textures.

Reported-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: remove blit_via_copy_region()
Rob Clark [Wed, 2 Jan 2019 16:35:02 +0000 (11:35 -0500)]
freedreno: remove blit_via_copy_region()

If we hit the memcpy() path for copy_region(), that will try to do a
transfer_map(), which goes badly for blits to/from staging triggered
by transfer_map() or transfer_unmap().

We could possibly add fd_blit2() which has allow_transfer_map param,
and call that for staging blits.  But I'm not really sure if trying
the blit via copy_region() is very useful.  At least for newer gens
that implement fd_context::blit(), it probably isn't.

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno/a6xx: rework blitter API
Rob Clark [Wed, 2 Jan 2019 16:06:11 +0000 (11:06 -0500)]
freedreno/a6xx: rework blitter API

Switch over to using fd_context::blit(), in the same way that a5xx does.
The previous patch wires fd_resource_copy_region() up to the blitter so
a6xx no longer needs to bypass the core layer to accelerate this.

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: try blitter for fd_resource_copy_region()
Rob Clark [Wed, 2 Jan 2019 16:04:16 +0000 (11:04 -0500)]
freedreno: try blitter for fd_resource_copy_region()

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: rework blit API
Rob Clark [Wed, 2 Jan 2019 15:54:06 +0000 (10:54 -0500)]
freedreno: rework blit API

First step to unify the way fd5 and fd6 blitter works.  Currently a6xx
bypasses the blit API in order to also accelerate resource_copy_region()

But this approach can lead to infinite recursion:

  #0  fd_alloc_staging (ctx=0x5555936480, rsc=0x7fac485f90, level=0, box=0x7fbab29220) at ../src/gallium/drivers/freedreno/freedreno_resource.c:291
  #1  0x0000007fbdebed04 in fd_resource_transfer_map (pctx=0x5555936480, prsc=0x7fac485f90, level=0, usage=258, box=0x7fbab29220, pptrans=0x7fbab29240) at ../src/gallium/drivers/freedreno/freedreno_resource.c:479
  #2  0x0000007fbe5c5068 in u_transfer_helper_transfer_map (pctx=0x5555936480, prsc=0x7fac485f90, level=0, usage=258, box=0x7fbab29220, pptrans=0x7fbab29240) at ../src/gallium/auxiliary/util/u_transfer_helper.c:243
  #3  0x0000007fbde2dcb8 in util_resource_copy_region (pipe=0x5555936480, dst=0x7fac485f90, dst_level=0, dst_x=0, dst_y=0, dst_z=0, src=0x7fac47c780, src_level=0, src_box_in=0x7fbab2945c) at ../src/gallium/auxiliary/util/u_surface.c:350
  #4  0x0000007fbdf2282c in fd_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47c780, src_level=0, src_box=0x7fbab2945c) at ../src/gallium/drivers/freedreno/freedreno_blitter.c:173
  #5  0x0000007fbdf085d4 in fd6_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47c780, src_level=0, src_box=0x7fbab2945c) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:587
  #6  0x0000007fbde2f3d0 in util_try_blit_via_copy_region (ctx=0x5555936480, blit=0x7fbab29430) at ../src/gallium/auxiliary/util/u_surface.c:864
  #7  0x0000007fbdec02c4 in fd_blit (pctx=0x5555936480, blit_info=0x7fbab29588) at ../src/gallium/drivers/freedreno/freedreno_resource.c:993
  #8  0x0000007fbdf08408 in fd6_blit (pctx=0x5555936480, info=0x7fbab29588) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:546
  #9  0x0000007fbdebdc74 in do_blit (ctx=0x5555936480, blit=0x7fbab29588, fallback=false) at ../src/gallium/drivers/freedreno/freedreno_resource.c:129
  #10 0x0000007fbdebe58c in fd_blit_from_staging (ctx=0x5555936480, trans=0x7fac47b7e8) at ../src/gallium/drivers/freedreno/freedreno_resource.c:326
  #11 0x0000007fbdebea38 in fd_resource_transfer_unmap (pctx=0x5555936480, ptrans=0x7fac47b7e8) at ../src/gallium/drivers/freedreno/freedreno_resource.c:416
  #12 0x0000007fbe5c5c68 in u_transfer_helper_transfer_unmap (pctx=0x5555936480, ptrans=0x7fac47b7e8) at ../src/gallium/auxiliary/util/u_transfer_helper.c:516
  #13 0x0000007fbde2de24 in util_resource_copy_region (pipe=0x5555936480, dst=0x7fac485f90, dst_level=0, dst_x=0, dst_y=0, dst_z=0, src=0x7fac47b8e0, src_level=0, src_box_in=0x7fbab2997c) at ../src/gallium/auxiliary/util/u_surface.c:376
  #14 0x0000007fbdf2282c in fd_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47b8e0, src_level=0, src_box=0x7fbab2997c) at ../src/gallium/drivers/freedreno/freedreno_blitter.c:173
  #15 0x0000007fbdf085d4 in fd6_resource_copy_region (pctx=0x5555936480, dst=0x7fac485f90, dst_level=0, dstx=0, dsty=0, dstz=0, src=0x7fac47b8e0, src_level=0, src_box=0x7fbab2997c) at ../src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:587
  ...

Instead rework the API to push the fallback back to core code, so that
we can rework resource_copy_region() to have it's own fallback path,
and then finally convert fd6 over to work in the same way.

This also makes ctx->blit() optional, and cleans up some unnecessary
callers.

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: skip depth resolve if not written
Rob Clark [Wed, 26 Dec 2018 19:09:55 +0000 (14:09 -0500)]
freedreno: skip depth resolve if not written

For multi-pass rendering, it is common to keep the same depth buffer
from previous pass, to discard geometry that would be hidden by later
draws.  In the later passes with depth-test enabled, but depth-write
disabled, there is no reason to do gmem2mem resolve.

TODO probably do something similar for stencil.. although stencil
buffer isn't used as commonly these days

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agonir: merge some basic consecutive ifs
Timothy Arceri [Thu, 8 Dec 2016 02:25:00 +0000 (13:25 +1100)]
nir: merge some basic consecutive ifs

After trying multiple times to merge if-statements with phis
between them I've come to the conclusion that it cannot be done
without regressions. The problem is for some shaders we end up
with a whole bunch of phis for the merged ifs resulting in
increased register pressure.

So this patch just merges ifs that have no phis between them.
This seems to be consistent with what LLVM does so for radeonsi
we only see a change (although its a large change) in a single
shader.

Shader-db results i965 (SKL):

total instructions in shared programs: 13098176 -> 13098152 (<.01%)
instructions in affected programs: 1326 -> 1302 (-1.81%)
helped: 4
HURT: 0

total cycles in shared programs: 332032989 -> 332037583 (<.01%)
cycles in affected programs: 60665 -> 65259 (7.57%)
helped: 0
HURT: 4

The cycles estimates reported by shader-db for i965 seem inaccurate
as the only difference in the final code is the removal of the
redundent condition evaluations and jumps.

Also the biggest code reduction (~7%) for radeonsi was in a tomb
raider tressfx shader but for some reason this does not get merged
for i965.

Shader-db results radeonsi (VEGA):

Totals from affected shaders:
SGPRS: 232 -> 232 (0.00 %)
VGPRS: 164 -> 164 (0.00 %)
Spilled SGPRs: 59 -> 59 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 14584 -> 13520 (-7.30 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 13 -> 13 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agonir: add rewrite_phi_predecessor_blocks() helper
Timothy Arceri [Tue, 20 Nov 2018 23:04:24 +0000 (10:04 +1100)]
nir: add rewrite_phi_predecessor_blocks() helper

This will also be used by the if merge pass in the following commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agonir: simplify does_varying_match()
Timothy Arceri [Wed, 2 Jan 2019 05:00:12 +0000 (16:00 +1100)]
nir: simplify does_varying_match()

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
3 years agonir: make use of does_varying_match() helper
Timothy Arceri [Wed, 2 Jan 2019 05:00:11 +0000 (16:00 +1100)]
nir: make use of does_varying_match() helper

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
3 years agonir: make nir_opt_remove_phis_impl() static
Timothy Arceri [Wed, 2 Jan 2019 05:00:10 +0000 (16:00 +1100)]
nir: make nir_opt_remove_phis_impl() static

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
3 years agov3d: Refactor compiler entrypoints.
Eric Anholt [Wed, 26 Dec 2018 21:20:25 +0000 (13:20 -0800)]
v3d: Refactor compiler entrypoints.

Before, I had per-stage entryoints with some helpers shared between them.
As I extended for compute shaders and shader-db, it turned out that the
other common code in the middle wanted to be shared too.

3 years agov3d: Handle dynamically uniform IF statements with uniform control flow.
Eric Anholt [Mon, 31 Dec 2018 20:18:34 +0000 (12:18 -0800)]
v3d: Handle dynamically uniform IF statements with uniform control flow.

Loops will be trickier, since we need some analysis to figure out if the
breaks/continues inside are uniform.  Until we get that in NIR, this gets
us some quick wins.

total instructions in shared programs: 6192844 -> 6174162 (-0.30%)
instructions in affected programs: 487781 -> 469099 (-3.83%)

3 years agov3d: Fold comparisons for IF conditions into the flags for the IF.
Eric Anholt [Sat, 29 Dec 2018 00:31:07 +0000 (16:31 -0800)]
v3d: Fold comparisons for IF conditions into the flags for the IF.

total instructions in shared programs: 6193810 -> 6192844 (-0.02%)
instructions in affected programs: 800373 -> 799407 (-0.12%)

3 years agov3d: Don't try to fold non-SSA-src comparisons into bcsels.
Eric Anholt [Mon, 31 Dec 2018 21:09:45 +0000 (13:09 -0800)]
v3d: Don't try to fold non-SSA-src comparisons into bcsels.

There could have been a write of a src in between the comparison and the
bcsel that would invalidate the comparison.

3 years agov3d: Move the "Find the ALU instruction generating our bool" out of bcsel.
Eric Anholt [Mon, 31 Dec 2018 21:05:06 +0000 (13:05 -0800)]
v3d: Move the "Find the ALU instruction generating our bool" out of bcsel.

This will be reused for if statements.

3 years agov3d: Simplify the emission of comparisons for the bcsel optimization.
Eric Anholt [Fri, 28 Dec 2018 21:45:25 +0000 (13:45 -0800)]
v3d: Simplify the emission of comparisons for the bcsel optimization.

I wanted to reuse the comparison stuff for nir_ifs, but for that I just
want the flags and no destination value.  Splitting the conditions from
the destinations ended up cleaning the existing code up, anyway.

3 years agov3d: Don't forget to include RT writes in precompiles.
Eric Anholt [Sun, 30 Dec 2018 16:59:54 +0000 (08:59 -0800)]
v3d: Don't forget to include RT writes in precompiles.

Looking at some assembly dumps for an optimization, we were clearly
missing important parts of the shader!

3 years agov3d: Fix segfault when failing to compile a program.
Eric Anholt [Mon, 31 Dec 2018 19:51:01 +0000 (11:51 -0800)]
v3d: Fix segfault when failing to compile a program.

We'll still fail at draw time, but this avoids a regression in shader-db
execution once I enable TLB writes in precompiles.

Fixes: b38e4d313fc2 ("v3d: Create a state uploader for packing our shaders together.")
3 years agoradeonsi: always unmap texture CPU mappings on 32-bit CPU architectures
Marek Olšák [Fri, 14 Dec 2018 21:03:00 +0000 (16:03 -0500)]
radeonsi: always unmap texture CPU mappings on 32-bit CPU architectures

Team Fortress 2 32-bit version runs out of the CPU address space.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: remove unused variables in si_insert_input_ptr
Marek Olšák [Fri, 14 Dec 2018 20:08:50 +0000 (15:08 -0500)]
radeonsi: remove unused variables in si_insert_input_ptr

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: use u_decomposed_prims_for_vertices instead of u_prims_for_vertices
Marek Olšák [Sat, 10 Nov 2018 03:27:05 +0000 (22:27 -0500)]
radeonsi: use u_decomposed_prims_for_vertices instead of u_prims_for_vertices

It seems to be the same, but this doesn't use integer division with
a variable divisor.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: make si_cp_wait_mem more configurable
Marek Olšák [Mon, 3 Dec 2018 19:58:08 +0000 (14:58 -0500)]
radeonsi: make si_cp_wait_mem more configurable

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: call si_fix_resource_usage for the GS copy shader as well
Marek Olšák [Tue, 13 Nov 2018 02:29:27 +0000 (21:29 -0500)]
radeonsi: call si_fix_resource_usage for the GS copy shader as well

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agoradeonsi: don't emit redundant PKT3_NUM_INSTANCES packets
Marek Olšák [Tue, 13 Nov 2018 01:38:46 +0000 (20:38 -0500)]
radeonsi: don't emit redundant PKT3_NUM_INSTANCES packets

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
3 years agonir: add a way to print the deref chain
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 20:13:46 +0000 (12:13 -0800)]
nir: add a way to print the deref chain

Makes debugging easier when we care about the deref chain and not the
deref instruction itself.  To make it take a const pointer, constify
some of the static functions in nir_print.c.

Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agomeson: Error out if building nouveau and using LLVM without rtti
Dylan Baker [Tue, 1 Jan 2019 03:23:52 +0000 (19:23 -0800)]
meson: Error out if building nouveau and using LLVM without rtti

Nouveau requires rtti. Often LLVM is configured without rtti, and code
with and without cannot be linked safely. Lets just error out if nouveau
is requested and llvm is built without rtti.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109202
Fixes: c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4
       ("meson: fix builds against LLVM built without rtti")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoegl/haiku: Fix reference to disp vs dpy
Alexander von Gluck IV [Thu, 27 Dec 2018 20:41:47 +0000 (20:41 +0000)]
egl/haiku: Fix reference to disp vs dpy

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 00992700c9a812a54563 "egl: set the EGLDevice when creating a display"
3 years agocompiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
Iago Toral Quiroga [Thu, 31 May 2018 08:34:03 +0000 (10:34 +0200)]
compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()

The 16-bit polynomial execution doesn't meet Khronos precision requirements.
Also, the half-float denorm range starts at 2^(-14) and with asin taking input
values in the range [0, 1], polynomial approximations can lead to flushing
relatively easy.

An alternative is to use the atan2 formula to compute asin, which is the
reference taken by Khronos to determine precision requirements, but that
ends up generating too many additional instructions when compared to the
polynomial approximation. Specifically, for the Intel case, doing this
adds +41 instructions to the program for each asin/acos call, which looks
like an undesirable trade off.

So for now we take the easy way out and fallback to using the 32-bit
polynomial approximation, which is better (faster) than the 16-bit atan2
implementation and gives us better precision that matches Khronos
requirements.

v2:
 - Fallback to 32-bit using recursion (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit frexp
Iago Toral Quiroga [Tue, 15 May 2018 08:25:10 +0000 (10:25 +0200)]
compiler/spirv: implement 16-bit frexp

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit hyperbolic trigonometric functions
Iago Toral Quiroga [Wed, 18 Apr 2018 08:14:11 +0000 (10:14 +0200)]
compiler/spirv: implement 16-bit hyperbolic trigonometric functions

v2:
 - use nir_fadd_imm and nir_fmul_imm helpers (Jason)

v3:
 - since we need to define one for fsub use it for fdiv too (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit exp and log
Iago Toral Quiroga [Wed, 18 Apr 2018 08:09:33 +0000 (10:09 +0200)]
compiler/spirv: implement 16-bit exp and log

v2
 - use nir_fmul_imm helper (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit atan2
Iago Toral Quiroga [Wed, 18 Apr 2018 08:07:54 +0000 (10:07 +0200)]
compiler/spirv: implement 16-bit atan2

v2:
 - fix huge_val for 16-bit, it was mean't to be 2^14 not 10^14.

v3:
 - rebase on top of new bool sized opcodes
 - use nir_b2f helper
 - use nir_fmul_imm helper

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit atan
Iago Toral Quiroga [Wed, 18 Apr 2018 07:36:41 +0000 (09:36 +0200)]
compiler/spirv: implement 16-bit atan

v2:
 - use nir_fadd_imm and nir_fmul_imm helpers (Jason)
 - rebased on top of new sized boolean opcodes
 - use nir_b2f helper

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit acos
Iago Toral Quiroga [Wed, 18 Apr 2018 07:15:01 +0000 (09:15 +0200)]
compiler/spirv: implement 16-bit acos

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: implement 16-bit asin
Iago Toral Quiroga [Wed, 18 Apr 2018 06:47:53 +0000 (08:47 +0200)]
compiler/spirv: implement 16-bit asin

v2:
  - use nir_fmul_imm and nir_fadd_imm helpers (Jason)

v3:
 - missed one case where we need to replace nir_imm_float
   with nir_imm_floatN_t (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/spirv: handle 16-bit float in radians() and degrees()
Iago Toral Quiroga [Tue, 17 Apr 2018 09:39:48 +0000 (11:39 +0200)]
compiler/spirv: handle 16-bit float in radians() and degrees()

v2:
 - use nir_imm_fmul helper (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/nir: add nir_fadd_imm() and nir_fmul_imm() helpers
Iago Toral Quiroga [Fri, 14 Dec 2018 08:28:56 +0000 (09:28 +0100)]
compiler/nir: add nir_fadd_imm() and nir_fmul_imm() helpers

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agocompiler/nir: add a nir_b2f() helper
Iago Toral Quiroga [Fri, 14 Dec 2018 07:54:36 +0000 (08:54 +0100)]
compiler/nir: add a nir_b2f() helper

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agonir: link time opt duplicate varyings
Timothy Arceri [Mon, 10 Dec 2018 08:36:47 +0000 (19:36 +1100)]
nir: link time opt duplicate varyings

If we are outputting the same value to more than one output
component rewrite the inputs to read from a single component.

This will allow the duplicate varying components to be optimised
away by the existing opts.

shader-db results i965 (SKL):

total instructions in shared programs: 12869230 -> 12860886 (-0.06%)
instructions in affected programs: 322601 -> 314257 (-2.59%)
helped: 3080
HURT: 8

total cycles in shared programs: 317792574 -> 317730593 (-0.02%)
cycles in affected programs: 2584925 -> 2522944 (-2.40%)
helped: 2975
HURT: 477

shader-db results radeonsi (VEGA):

SGPRS: 31576 -> 31664 (0.28 %)
VGPRS: 17484 -> 17064 (-2.40 %)
Spilled SGPRs: 184 -> 167 (-9.24 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 583340 -> 569368 (-2.40 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 6162 -> 6270 (1.75 %)
Wait states: 0 -> 0 (0.00 %)

vkpipeline-db results RADV (VEGA):

Totals from affected shaders:
SGPRS: 14880 -> 15080 (1.34 %)
VGPRS: 10872 -> 10888 (0.15 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 674016 -> 668396 (-0.83 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 2708 -> 2704 (-0.15 %)
Wait states: 0 -> 0 (0.00 %

V2: bunch of tidy ups suggested by Jason

Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agonir: rework nir_link_opt_varyings()
Timothy Arceri [Wed, 19 Dec 2018 09:09:42 +0000 (20:09 +1100)]
nir: rework nir_link_opt_varyings()

This just cleans things up a little and make things more safe for
derefs.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agonir: add can_replace_varying() helper
Timothy Arceri [Tue, 11 Dec 2018 00:53:54 +0000 (11:53 +1100)]
nir: add can_replace_varying() helper

This will be reused by the following patch.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agonir: rename nir_link_constant_varyings() nir_link_opt_varyings()
Timothy Arceri [Tue, 11 Dec 2018 00:49:00 +0000 (11:49 +1100)]
nir: rename nir_link_constant_varyings() nir_link_opt_varyings()

The following patches will add support for an additional
optimisation so this function will no longer just optimise varying
constants.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agost/glsl_to_nir: call nir_lower_load_const_to_scalar() in the st
Timothy Arceri [Tue, 11 Dec 2018 04:06:37 +0000 (15:06 +1100)]
st/glsl_to_nir: call nir_lower_load_const_to_scalar() in the st

This will help the new opt introduced in the following patches
allowing us to remove extra duplicate varyings.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agoradeonsi: make use of ac_are_tessfactors_def_in_all_invocs()
Timothy Arceri [Sat, 15 Dec 2018 04:27:01 +0000 (15:27 +1100)]
radeonsi: make use of ac_are_tessfactors_def_in_all_invocs()

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()
Timothy Arceri [Tue, 18 Dec 2018 01:05:31 +0000 (12:05 +1100)]
ac/nir_to_llvm: add ac_are_tessfactors_def_in_all_invocs()

The following patch will use this with the radeonsi NIR backend
but I've added it to ac so we can use it with RADV in future.

This is a NIR implementation of the tgsi function
tgsi_scan_tess_ctrl().

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: remove unrequired param in si_nir_scan_tess_ctrl()
Timothy Arceri [Tue, 18 Dec 2018 01:04:26 +0000 (12:04 +1100)]
radeonsi: remove unrequired param in si_nir_scan_tess_ctrl()

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agotgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()
Timothy Arceri [Fri, 14 Dec 2018 04:36:02 +0000 (15:36 +1100)]
tgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()

The previous code used a do while loop and continues after walking
a nested loop/if-statement. This means we end up evaluating the
last instruction from the nested block against the while condition
and potentially exit early if it matches the exit condition of the
outer block.

Fixes: 386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agotgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()
Timothy Arceri [Fri, 14 Dec 2018 04:09:38 +0000 (15:09 +1100)]
tgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()

This just happened not to crash/assert because all loops have at
least 1 if-statement and due to a second bug we end up matching
the same ENDIF to exit both the iteration over the if-statment
and the loop.

The second bug is fixed in the following patch.

Fixes: 386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agonv30: disable rendering to 3D textures
Ilia Mirkin [Tue, 1 Jan 2019 20:06:34 +0000 (15:06 -0500)]
nv30: disable rendering to 3D textures

There's no way to tell the 3D engine about swizzling on such textures.
While rendering to NPOT ones may be possible, there's no great way to
expose that in gallium, nor would there be any practical benefit.

Fixes the non-compressed-format "copyteximage 3D" failures. Something
odd going on with the compressed formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agoradv: Do a cache flush if needed before reading predicates.
Bas Nieuwenhuizen [Sun, 30 Dec 2018 22:37:11 +0000 (23:37 +0100)]
radv: Do a cache flush if needed before reading predicates.

This caused random failures for two conditional rendering tests:

dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_discard
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_no_discard

These wrote the predicate with the vertex shader, did a barrier and then
started the conditional rendering. However the cache flushes for the barrier
only happen on first draw, so after the predicate has been read.

Fixes: e45ba51ea45 "radv: add support for VK_EXT_conditional_rendering"
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoanv/autotools: make sure tests link with -msse2
Erik Faye-Lund [Sun, 30 Dec 2018 21:57:46 +0000 (22:57 +0100)]
anv/autotools: make sure tests link with -msse2

Without this, I get the following error when building the tests with
autotools on i686:

---8<---
src/intel/common/gen_clflush.h: In function ‘gen_clflush_range’:
src/intel/common/gen_clflush.h:37:7: warning: implicit declaration of function ‘__builtin_ia32_clflush’; did you mean ‘__builtin_ia32_pause’? [-Wimplicit-function-declaration]
       __builtin_ia32_clflush(p);
       ^~~~~~~~~~~~~~~~~~~~~~
       __builtin_ia32_pause
src/intel/common/gen_clflush.h: In function ‘gen_flush_range’:
src/intel/common/gen_clflush.h:45:4: warning: implicit declaration of function ‘__builtin_ia32_mfence’; did you mean ‘__builtin_ia32_fnclex’? [-Wimplicit-function-declaration]
    __builtin_ia32_mfence();
    ^~~~~~~~~~~~~~~~~~~~~
    __builtin_ia32_fnclex
---8<---

The erros are generated for each of these files:
- mesa/src/intel/vulkan/tests/state_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool.c
- mesa/src/intel/vulkan/tests/block_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool_free_list_only.c

This is obviously because gen_clflush.h contains code that uses
intrinsics that are only available with SSE3. Since the driver already
uses SSE3, it seems reasonable to add this to the tests as well.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Eric Engeström <eric@engestrom.ch>
3 years agoanv/meson: make sure tests link with -msse2
Erik Faye-Lund [Sun, 30 Dec 2018 21:09:06 +0000 (22:09 +0100)]
anv/meson: make sure tests link with -msse2

Without this, I get the following error when building the tests using
meson on i686:

---8<---
In file included from ../../../mesa/src/intel/vulkan/anv_private.h:46,
                 from ../../../mesa/src/intel/vulkan/tests/state_pool_no_free.c:26:
../../../mesa/src/intel/common/gen_clflush.h: In function ‘gen_clflush_range’:
../../../mesa/src/intel/common/gen_clflush.h:37:7: error: implicit declaration of function ‘__builtin_ia32_clflush’; did you mean ‘__builtin_ia32_pause’? [-Werror=implicit-function-declaration]
       __builtin_ia32_clflush(p);
       ^~~~~~~~~~~~~~~~~~~~~~
       __builtin_ia32_pause
../../../mesa/src/intel/common/gen_clflush.h: In function ‘gen_flush_range’:
../../../mesa/src/intel/common/gen_clflush.h:45:4: error: implicit declaration of function ‘__builtin_ia32_mfence’; did you mean ‘__builtin_ia32_fnclex’? [-Werror=implicit-function-declaration]
    __builtin_ia32_mfence();
    ^~~~~~~~~~~~~~~~~~~~~
    __builtin_ia32_fnclex
---8<---

The errors are generated for each of these files:
- mesa/src/intel/vulkan/tests/state_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool.c
- mesa/src/intel/vulkan/tests/block_pool_no_free.c
- mesa/src/intel/vulkan/tests/state_pool_free_list_only.c

This is obviously because gen_clflush.h contains code that uses
intrinsics that are only available with SSE3. Since the driver already
uses SSE3, it seems reasonable to add this to the tests as well.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engeström <eric@engestrom.ch>
3 years agonv30: fix some s3tc layout issues
Ilia Mirkin [Mon, 31 Dec 2018 00:17:10 +0000 (19:17 -0500)]
nv30: fix some s3tc layout issues

s3tc layouts are a bit finicky - they're packed, but not swizzled.
Adjust logic to allow for that case:

  - Don't set a uniform pitch for POT-sized compressed textures
  - Adjust define_rect API to be less confused about block sizes
  - Only mark a texture as linear if it has a uniform pitch set

This has been tested to fix xonotic (as well as the s3tc-* piglits)
on nv3x and keeps it working on nv4x.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: use correct helper to get blocks in y direction
Ilia Mirkin [Thu, 27 Dec 2018 15:27:43 +0000 (10:27 -0500)]
nv30: use correct helper to get blocks in y direction

This doesn't matter since all compressed formats supported by this
hardware use square blocks, but best to use the correct helper.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: add support for multi-layer transfers
Ilia Mirkin [Thu, 27 Dec 2018 15:24:56 +0000 (10:24 -0500)]
nv30: add support for multi-layer transfers

This logic mirrors what we do on nv50. The relatively new
texture_subdata callback can cause this to happen with 3D textures,
which is triggered at least by xonotic, and probably many piglits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: fix rare issue with fp unbinding not finding the bufctx
Ilia Mirkin [Thu, 27 Dec 2018 04:01:21 +0000 (23:01 -0500)]
nv30: fix rare issue with fp unbinding not finding the bufctx

If the last-active context gets deleted, the pushbuf doesn't have a
bufctx to reference. Then there could be a sequence of binds which would
trigger a reset on that bin before validation was done. Instead we just
pass in the bufctx in question directly.

All other instances of PUSH_RESET happen strictly after a validation is
run.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102349
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agonv30: avoid setting user_priv without setting cur_ctx
Ilia Mirkin [Thu, 27 Dec 2018 03:58:54 +0000 (22:58 -0500)]
nv30: avoid setting user_priv without setting cur_ctx

The whole user_priv thing is a mess, but as long as it's there, it
basically has to map 1:1 to the cur_ctx. Unfortunately we were setting
user_priv to some context, then that context could get deleted without
any draws/validations in it, leading user_priv to become NULL, with
cur_ctx still pointing at some old context. Then we wouldn't run the
switch logic, which in turn led to a NULL bufctx being dereferenced.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102349
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
3 years agov3d: Add support for gl_HelperInvocation.
Eric Anholt [Fri, 28 Dec 2018 19:30:52 +0000 (11:30 -0800)]
v3d: Add support for gl_HelperInvocation.

We can just look at the MSF flags -- if they're unset, then we're
definitely in a helper invocation.  Fixes
dEQP-GLES31.functional.shaders.helper_invocation.* with GLES3.1 enabled.

3 years agov3d: Add support for textureSize() on MSAA textures.
Eric Anholt [Fri, 28 Dec 2018 18:09:00 +0000 (10:09 -0800)]
v3d: Add support for textureSize() on MSAA textures.

Fixes failures in
dEQP-GLES31.functional.shaders.builtin_functions.texture_size.samples_1_texture_2d
in the GLES3.1 suite.

3 years agov3d: Add support for requesting the sample offsets.
Eric Anholt [Fri, 28 Dec 2018 07:20:53 +0000 (23:20 -0800)]
v3d: Add support for requesting the sample offsets.

3 years agov3d: Add support for non-constant texture offsets.
Eric Anholt [Thu, 27 Dec 2018 07:35:22 +0000 (23:35 -0800)]
v3d: Add support for non-constant texture offsets.

Fixes
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_pot.clamp_to_edge_repeat
and others.

3 years agov3d: Force sampling from base level for tg4.
Eric Anholt [Thu, 27 Dec 2018 07:15:30 +0000 (23:15 -0800)]
v3d: Force sampling from base level for tg4.

This is what the GLSL ES 310 spec tells us to do, but apparently the
"gather mode" flag doesn't imply it in the HW.  Fixes
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8.filter_mode.min_nearest_mipmap_linear_mag_linear

3 years agov3d: Add a note for a potential performance win on multop/umul24.
Eric Anholt [Wed, 26 Dec 2018 20:54:58 +0000 (12:54 -0800)]
v3d: Add a note for a potential performance win on multop/umul24.

Noticed while debugging a testcase.

3 years agov3d: Dead-code eliminate unused flags updates.
Eric Anholt [Sat, 29 Dec 2018 20:44:22 +0000 (12:44 -0800)]
v3d: Dead-code eliminate unused flags updates.

The greedy comparison folding in bcsel means that we may have left the
original bool-generating NIR ALU instruction dead, but DCE wasn't
eliminating the VIR code for it because of the flags updates.

total instructions in shared programs: 5186024 -> 5100894 (-1.64%)
instructions in affected programs: 1448695 -> 1363565 (-5.88%)

3 years agov3d: Don't generate temps for comparisons.
Eric Anholt [Sat, 29 Dec 2018 21:20:35 +0000 (13:20 -0800)]
v3d: Don't generate temps for comparisons.

This was just generated work for vir_opt_dead_code and cluttered up the
dumps.

3 years agov3d: Move "does this instruction have flags" from sched to generic helpers.
Eric Anholt [Sat, 29 Dec 2018 19:00:25 +0000 (11:00 -0800)]
v3d: Move "does this instruction have flags" from sched to generic helpers.

I wanted to reuse it for DCE of flags updates.

3 years agov3d: Drop incorrect dependency for flpop.
Eric Anholt [Sat, 29 Dec 2018 06:02:27 +0000 (22:02 -0800)]
v3d: Drop incorrect dependency for flpop.

It is just shifting probably-means-flags bits out of a value, it doesn't
actually update the flags on its own.

3 years agov3d: Drop unused count_nir_instrs() helper.
Eric Anholt [Sat, 29 Dec 2018 20:30:19 +0000 (12:30 -0800)]
v3d: Drop unused count_nir_instrs() helper.

This was for shader-db, but I haven't cared about NIR instruction counts
in a long time.

3 years agov3d: Hook up some shader-db output to GL_ARB_debug_output.
Eric Anholt [Thu, 20 Dec 2018 15:45:58 +0000 (07:45 -0800)]
v3d: Hook up some shader-db output to GL_ARB_debug_output.

This allows the original shader-db project's run.c runner to parse things
easily, and is probably a good thing to have for GL_ARB_debug_output in
general.  I formatted it more like Intel's so I can mostly reuse their
report script.

3 years agov3d: Add a "precompile" debug flag for shader-db.
Eric Anholt [Thu, 20 Dec 2018 01:22:41 +0000 (17:22 -0800)]
v3d: Add a "precompile" debug flag for shader-db.

I've been using my apitrace-based shader-db so far, but it's slow
(apitrace decompression), intrusive (apitrace windows spamming the
screen), and doesn't have much coverage.  The original shader-db provides
a lot more coverage and compiles faster, at the expense of not having the
actual runtime variant key.  As v3d has a lot less runtime variation than
vc4 did, this tradeoff makes more sense.

3 years agov3d: Fix uniform pretty printing assertion failure with branches.
Eric Anholt [Thu, 20 Dec 2018 20:00:34 +0000 (12:00 -0800)]
v3d: Fix uniform pretty printing assertion failure with branches.

Fixes: 248a7fb392ba ("v3d: Do uniform pretty-printing in the QPU dump.")
3 years agomeson: Override C++ standard to gnu++11 when building with altivec on ppc64
Dylan Baker [Tue, 4 Dec 2018 21:52:19 +0000 (13:52 -0800)]
meson: Override C++ standard to gnu++11 when building with altivec on ppc64

Otherwise there will be symbol collisions for the vector name.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108943
Distro Bug: https://bugs.gentoo.org/673622
Fixes: 42ea0631f108d82554339530d6c88aa1b448af1e
       ("meson: build clover")
Acked-by: Matt Turner <mattst88@gmail.com>
3 years agointel/aub_viewer: highlight true booleans
Lionel Landwerlin [Sun, 18 Nov 2018 17:25:46 +0000 (17:25 +0000)]
intel/aub_viewer: highlight true booleans

Useful to spot PIPE_CONTROL flags.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: fold binding/sampler table items
Lionel Landwerlin [Sun, 12 Aug 2018 18:17:27 +0000 (19:17 +0100)]
intel/aub_viewer: fold binding/sampler table items

Makes things easier to read rather than a long block of text.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: fix shader view
Lionel Landwerlin [Wed, 19 Dec 2018 17:52:06 +0000 (17:52 +0000)]
intel/aub_viewer: fix shader view

Not decoding the shader at the right offset.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agointel/aub_viewer: print address of missing shader
Lionel Landwerlin [Mon, 5 Nov 2018 20:47:46 +0000 (20:47 +0000)]
intel/aub_viewer: print address of missing shader

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>