mesa.git
4 years agoetnaviv: flush source TS before resolve
Lucas Stach [Mon, 26 Jun 2017 15:26:20 +0000 (17:26 +0200)]
etnaviv: flush source TS before resolve

If we blit from a rendertarget or a depthstencil buffer there might still
be dirty data in the TS buffer which needs to be flushed out.

Fixes missing shadow tiles in glmark2 shadow.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
4 years agoetnaviv: flush color cache and depth cache together before resolves
Philipp Zabel [Tue, 9 May 2017 16:26:57 +0000 (18:26 +0200)]
etnaviv: flush color cache and depth cache together before resolves

Before resolving a rendertarget or a depth/stencil resource into a
texture, flush both the color cache and the depth cache together.

It is unclear whether this is necessary for the following stall to
work properly, or whether the depth flush just adds enough time
for the color cache flush to finish before the resolver is started,
but this change removes artifacts that otherwise appear if a texture
is sampled directly after rendering into it.

The test case is a simple QML scene graph with a QtWebEngine based
WebView rendered on top of a blue background:

import QtQuick 2.0
import QtQuick.Window 2.2
import QtWebView 1.1

Window {
Rectangle {
id: background
anchors.fill: parent
color: "blue"
}

WebView {
id: webView
anchors.fill: parent
}

Component.onCompleted: {
webView.url = "<some animated website>"
}
}

If the website is animated, the WebView renders the site contents into
texture tiles and immediately afterwards samples from them to draw the
tiles into the Qt renderbuffer. Without this patch, a small irregular
triangle in the lower right of each browser tile appears solid blue, as
if the texture sampler samples zeroes instead of the website contents,
and the previously rendered blue Rectangle shows through.

Other attempts such as adding a pipeline stall before the color flush or
a TS cache flush afterwards or flushing multiple times, with stalls
before and after each flush, have shown no effect.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 years agost/mesa: handle stfbi being NULL on entry of st_framebuffer_reuse_or_create
Lucas Stach [Thu, 13 Jul 2017 16:58:04 +0000 (18:58 +0200)]
st/mesa: handle stfbi being NULL on entry of st_framebuffer_reuse_or_create

Apparently this can happen. Just bail out early in that case, as all the called
functions return NULL in that case.

Fixes weston-terminal for me.

Fixes: 147d7fb772a7 ("st/mesa: add a winsys buffers list in st_context")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agoegl/wayland: Use MIN2 for wl_drm version
Daniel Stone [Sat, 10 Jun 2017 13:54:44 +0000 (14:54 +0100)]
egl/wayland: Use MIN2 for wl_drm version

Use a slightly more explicit version cap for binding wl_drm, so we can
add other interfaces with different versioning schemes later.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoegl/wayland: Fix whitespace damage
Daniel Stone [Sat, 10 Jun 2017 13:54:05 +0000 (14:54 +0100)]
egl/wayland: Fix whitespace damage

Convert tabs to spaces, fix misalignments.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoutil: Remove u_math from u_vector
Daniel Stone [Fri, 9 Jun 2017 13:57:20 +0000 (14:57 +0100)]
util: Remove u_math from u_vector

u_vector.h doesn't actually use anything from u_math, but it does mean
everyone has to pull in src/gallium/auxiliary/util includes.

Just remove it, adding a <string.h> include to u_vector.c to cover
memcpy.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoconfigure: only install khrplatform.h if needed
Eric Engestrom [Fri, 14 Jul 2017 10:14:28 +0000 (11:14 +0100)]
configure: only install khrplatform.h if needed

khrplatform.h is only used by EGL and GLES; let's only install it when
one of those is enabled.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jussi Kukkonen <jussi.kukkonen@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agoscons: split out check_header() helper
Eric Engestrom [Mon, 10 Jul 2017 12:27:25 +0000 (13:27 +0100)]
scons: split out check_header() helper

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agoanv/pipeline: do not use BITFIELD64_BIT()
Juan A. Suarez Romero [Fri, 14 Jul 2017 10:31:38 +0000 (10:31 +0000)]
anv/pipeline: do not use BITFIELD64_BIT()

In the previous commit, forgot to apply v2 suggestions.

Fixes: 28d0c38 (anv/pipeline: use unsigned long long constant to check
enable vertex inputs)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
4 years agoanv/pipeline: use unsigned long long constant to check enable vertex inputs
Juan A. Suarez Romero [Thu, 13 Jul 2017 14:33:57 +0000 (14:33 +0000)]
anv/pipeline: use unsigned long long constant to check enable vertex inputs

When initializing the ANV pipeline, one of the tasks is checking which
vertex inputs are enabled. This is done by checking if the enabled bits
in inputs_read.

But the mask to use is computed doing `(1 << (VERT_ATTRIB_GENERIC0 +
desc->location))`. The problem here is that if location is 15 or
greater, the sum is 32 or greater. But C is handling 1 as a 32-bit
integer, which means the displaced bit is out of range and thus the full
value is 0.

Thus, use 1ull, which is an unsigned long long value.

This fixes:
dEQP-VK.pipeline.vertex_input.max_attributes.16_attributes.binding_one_to_one.interleaved

v2: use 1ull instead of BITFIELD64_BIT() (Matt Turner)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
4 years agoi965: Use pushed UBO data in the scalar backend.
Kenneth Graunke [Tue, 29 Nov 2016 13:20:20 +0000 (05:20 -0800)]
i965: Use pushed UBO data in the scalar backend.

This actually takes advantage of the newly pushed UBO data, avoiding
pull loads.

Improves performance in GLBenchmark Manhattan 3.1 by:

   HSW: ~1%, BDW/SKL/KBL GT2: 3-4%, SKL GT4: 7-8%, APL: 4-5%.
   (thanks to Eero Tamminen for these numbers)

shader-db results on Skylake, ignoring programs with spill/fill changes:

   total instructions in shared programs: 13963994 -> 13651893 (-2.24%)
   instructions in affected programs: 4250328 -> 3938227 (-7.34%)
   helped: 28527
   HURT: 0

   total cycles in shared programs: 179808608 -> 172535170 (-4.05%)
   cycles in affected programs: 79720410 -> 72446972 (-9.12%)
   helped: 26951
   HURT: 1248

   LOST:   46
   GAINED: 21

Many "Deus Ex: Mankind Divided" shaders which already spilled end up
spill a lot more (about 240 programs hurt, 9 helped).  The cycle
estimator suggests this is still overall a win (-0.23% in cycle counts)
presumably because we trade pull loads for fills.

v2: Drop "PULL" environment variable left in for initial debugging
    (caught by Matt).

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Factor out push locations.
Kenneth Graunke [Fri, 2 Jun 2017 16:54:31 +0000 (09:54 -0700)]
i965: Factor out push locations.

With UBOs, the answer of "have we decided to push this uniform" gets
a bit more complicated - for one, we have multiple surfaces.  This
patch refactors things so we can add the new code in a single place.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Push UBO data, but don't use it just yet.
Kenneth Graunke [Tue, 29 Nov 2016 10:47:15 +0000 (02:47 -0800)]
i965: Push UBO data, but don't use it just yet.

This patch starts uploading UBO data via 3DSTATE_CONSTANT_* packets,
and updates the compiler to know that there's extra payload data, so
things continue working.  However, it still issues pull loads for all
data.  I wanted to separate the two aspects for greater bisectability.

v2: Update for new intel_bufferobj_buffer parameter.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Pad buffer objects by 2kB in robust contexts to avoid OOB access.
Kenneth Graunke [Sat, 3 Jun 2017 18:46:15 +0000 (11:46 -0700)]
i965: Pad buffer objects by 2kB in robust contexts to avoid OOB access.

This is an annoyingly big hammer, but it seems less mean than disabling
UBO pushing, and I'm not sure what else to do.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Stop re-uploading push constants after URB reconfiguration.
Kenneth Graunke [Tue, 29 Nov 2016 09:37:49 +0000 (01:37 -0800)]
i965: Stop re-uploading push constants after URB reconfiguration.

Previously we would re-upload the constant data to the batchbuffer,
then re-emit the packets.  We only need to do the last step (causing
the existing data in the batchbuffer to be re-uploaded to the push
constant staging area in the L3).

Now that we've separated the two, it's pretty easy to accomplish.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Separate uploading push constant data from the pointer packets.
Kenneth Graunke [Tue, 29 Nov 2016 09:06:50 +0000 (01:06 -0800)]
i965: Separate uploading push constant data from the pointer packets.

I hope to upload UBO via 3DSTATE_CONSTANT_XS packets, in addition to
normal uniforms.  In order to do that, I'll need to re-emit the packets
when UBOs change.  But I don't want to re-copy the regular uniform data
to the batchbuffer every time.

This patch separates out the data uploading from the packet submission.
We're running low on dirty bits, so I made the new atom happen on every
draw call, and added a flag to stage_state indicating that we want the
packet for that stage emitted.

I would have preferred to do this outside the atom system, but it has
to happen between the uploading of push constant data and the binding
table upload.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Introduce a BRW_NEW_DRAW_CALL dirty bit.
Kenneth Graunke [Tue, 29 Nov 2016 11:34:01 +0000 (03:34 -0800)]
i965: Introduce a BRW_NEW_DRAW_CALL dirty bit.

This allows us to have atoms which are signalled on every draw call.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Store per-stage push constant BO pointers.
Kenneth Graunke [Tue, 27 Jun 2017 21:38:13 +0000 (14:38 -0700)]
i965: Store per-stage push constant BO pointers.

Right now, we always upload new push constant data, and immediately
emit 3DSTATE_CONSTANT_* packets.  We call intel_upload_space and store
the resulting BO pointer in brw->curbe.curbe_bo.  We read that when
emitting the packets.  This works today, but is fragile - it depends on
upload and packet emission being interleaved.

If we instead were to upload all the data, then emit all the packets,
then upload BO wrapping will get us into trouble.  For example, the VS
constants may land in one upload BO, but the FS constants may not fit
and land in a second upload BO.  Uploading FS constants would overwrite
the brw->curbe.curbe_bo pointer, so when we emitted 3DSTATE_CONSTANT_VS,
we'd get the wrong BO.

I intend to separate out this code in a future commit, so I need to fix
this.  To fix it, we simply store a per-stage BO pointer.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Select ranges of UBO data to be uploaded as push constants.
Kenneth Graunke [Sat, 2 Jan 2016 11:21:28 +0000 (03:21 -0800)]
i965: Select ranges of UBO data to be uploaded as push constants.

This adds a NIR pass that decides which portions of UBOS we should
upload as push constants, rather than pull constants.

v2: Switch to uint16_t for the UBO block number, because we may
    have a lot of them in Vulkan (suggested by Jason).  Add more
    comments about bitfield trickery (requested by Matt).

v3: Skip vec4 stages for now...I haven't finished wiring up support
    in the vec4 backend, and so pushing the data but not using it
    will just be wasteful.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Require a UBO offset alignment of 32 bytes.
Kenneth Graunke [Mon, 25 Jan 2016 23:23:24 +0000 (15:23 -0800)]
i965: Require a UBO offset alignment of 32 bytes.

Soon, we're going to start providing UBO data to shaders as push
constants, rather than requiring them to issue pull loads.  The
3DSTATE_CONSTANT_* commands require 32 byte aligned pointers.

So, we need to increase this from 16 to 32.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Switch to absolute addressing for constant buffer 0.
Kenneth Graunke [Fri, 15 Aug 2014 05:36:45 +0000 (22:36 -0700)]
i965: Switch to absolute addressing for constant buffer 0.

By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic
state base address.  This makes it unusable for pushing UBOs.  I'd like
to be able to use all four push buffers.

There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake)
which controls whether buffer 0 is relative to dynamic state base
address, or simply a normal pointer.  Setting that gives us full
flexibility.

We can't currently write this on Haswell and earlier, and will need
to update the kernel command parser, and then do the whole version
checking song and dance.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965: Use async maps for BufferSubData to regions with no valid data.
Kenneth Graunke [Wed, 18 Jan 2017 01:18:01 +0000 (17:18 -0800)]
i965: Use async maps for BufferSubData to regions with no valid data.

When writing a region of a buffer via glBufferSubData(), we can write
the data asynchronously if the destination doesn't contain any data.
Even if it's busy, the data was undefined, so the new data is fine too.

Removes all stall avoidance blits on BufferSubData calls in
"Total War: WARHAMMER" on my Skylake GT4.

Decreases the number of stall avoidance blits in Manhattan 3.1:
- Skylake GT4: -18.3544% +/- 6.76483% (n=13)
- Apollolake:  -12.1095% +/- 5.24458% (n=13)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoi965: Track a range of the buffer which contains valid data.
Kenneth Graunke [Wed, 18 Jan 2017 01:18:01 +0000 (17:18 -0800)]
i965: Track a range of the buffer which contains valid data.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoi965: Add a "write" parameter to intel_bufferobj_buffer.
Kenneth Graunke [Wed, 7 Jun 2017 20:26:58 +0000 (13:26 -0700)]
i965: Add a "write" parameter to intel_bufferobj_buffer.

This doesn't do anything yet, but soon we'll want to know whether an
access to a buffer section may write that data, or simply reads it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoi965: Convert GS_STATE to genxml.
Rafael Antognolli [Wed, 7 Jun 2017 20:03:43 +0000 (13:03 -0700)]
i965: Convert GS_STATE to genxml.

Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c,
together with brw_gs_unit_state.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Prepare gs_state emitting code to include gen4-5.
Rafael Antognolli [Tue, 6 Jun 2017 16:38:46 +0000 (09:38 -0700)]
i965: Prepare gs_state emitting code to include gen4-5.

Since we always call brw_batch_emit anyways, we can hopefully make things
simpler by calling it only once, and then branching inside its body. This
can be helpful when bringing the gen4-5 code into this function.

Additionally, check for GEN_GEN == 6 instead of < 7 in cases that won't apply
to lower gens.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Remove upload_gs_state_for_tf.
Rafael Antognolli [Tue, 6 Jun 2017 16:49:11 +0000 (09:49 -0700)]
i965: Remove upload_gs_state_for_tf.

This function only emits a particular case of 3DSTATE_GS. Instead, we can do
that inside genX(upload_gs_state), and later reuse part of that code for
emitting gen4-5 state.

There's the additional benefit of allowing us to remove gen6_gs_state.c, which
was only left because of this function.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Convert BLEND_CONSTANT_COLOR state to genxml.
Rafael Antognolli [Mon, 5 Jun 2017 21:44:44 +0000 (14:44 -0700)]
i965: Convert BLEND_CONSTANT_COLOR state to genxml.

It's a very simple conversion, and it allows us to delete brw_cc.c.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Convert CC state on gen4-5 to genxml.
Rafael Antognolli [Thu, 1 Jun 2017 19:28:41 +0000 (12:28 -0700)]
i965: Convert CC state on gen4-5 to genxml.

Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.

v2:
   - Always check for depth_irb (Ken)
   - Always set Backface Stencil Ref (Ken)
   - Always set alpha reference value (Ken)

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Move color calc code around a bit.
Rafael Antognolli [Tue, 20 Jun 2017 00:15:55 +0000 (17:15 -0700)]
i965: Move color calc code around a bit.

This makes the code more consistent accross generations.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Check for alpha channel just like in gen6+.
Rafael Antognolli [Fri, 2 Jun 2017 21:41:19 +0000 (14:41 -0700)]
i965: Check for alpha channel just like in gen6+.

gen6+ uses _mesa_base_format_has_channel() to check for the alpha
channel, while gen4-5 use ctx->DrawBuffer->Visual.alphaBits. By using
_mesa_base_format_has_channel() here we keep the same behavior accross
all gen.

While initially both ways of checking the alpha channel seemed correct
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Make a helper function for blend entry related state.
Rafael Antognolli [Thu, 1 Jun 2017 18:41:16 +0000 (11:41 -0700)]
i965: Make a helper function for blend entry related state.

Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoi965: Make a helper function for depth/stencil related state.
Kenneth Graunke [Mon, 8 May 2017 23:30:58 +0000 (16:30 -0700)]
i965: Make a helper function for depth/stencil related state.

Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and
BLEND_STATE together into a single COLOR_CALC_STATE structure.

By making a helper function, we'll be able to reuse it when filling
out Gen4-5 COLOR_CALC_STATE without replicating any actual logic.

We use generation-defined typedef to handle the polymorphism.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
4 years agoaubinator: don't leak fd of opened aubfile
Lionel Landwerlin [Thu, 13 Jul 2017 15:39:42 +0000 (16:39 +0100)]
aubinator: don't leak fd of opened aubfile

CID: 1373563
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agoanv: don't use strcpy for copying strings
Lionel Landwerlin [Thu, 13 Jul 2017 15:35:01 +0000 (16:35 +0100)]
anv: don't use strcpy for copying strings

CID: 1358935
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agointel/compiler: no need to check unsigned is >= 0
Lionel Landwerlin [Thu, 13 Jul 2017 15:32:54 +0000 (16:32 +0100)]
intel/compiler: no need to check unsigned is >= 0

CID: 1338342
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agoi965: fix missing NULL return if allocation fails
Lionel Landwerlin [Thu, 13 Jul 2017 15:29:25 +0000 (16:29 +0100)]
i965: fix missing NULL return if allocation fails

CID: 1250585
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agointel/compiler: don't check unsigned is >= 0
Lionel Landwerlin [Thu, 13 Jul 2017 15:23:48 +0000 (16:23 +0100)]
intel/compiler: don't check unsigned is >= 0

CID: 1224468
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agoi965: check pointer before dereferencing it
Lionel Landwerlin [Thu, 13 Jul 2017 15:11:40 +0000 (16:11 +0100)]
i965: check pointer before dereferencing it

Check that irb isn't NULL before accessing irb->Base.Base.NumSamples.

CID: 1026046
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agoi965: map_gtt: check mapping address before adding offset
Lionel Landwerlin [Thu, 13 Jul 2017 15:08:34 +0000 (16:08 +0100)]
i965: map_gtt: check mapping address before adding offset

The NULL check might fail if offset isn't 0.

CID: 971379
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agointel/compiler: remove check unsigned is >= 0
Lionel Landwerlin [Thu, 13 Jul 2017 15:04:28 +0000 (16:04 +0100)]
intel/compiler: remove check unsigned is >= 0

By definition unsigned are always >= 0.

CID: 742212
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agoisl: use 64bit arithmetic to compute size
Lionel Landwerlin [Thu, 13 Jul 2017 14:37:43 +0000 (15:37 +0100)]
isl: use 64bit arithmetic to compute size

If we allow the size to be more than 2^32, then we should compute it
in 64bit arithmetic otherwise we might run into overflow issues.

CID: 14128921412891
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
4 years agonir/lower_io_to_temporaries: don't set compact on shadow vars
Connor Abbott [Thu, 6 Jul 2017 19:23:33 +0000 (12:23 -0700)]
nir/lower_io_to_temporaries: don't set compact on shadow vars

The compact flag doesn't make sense on local variables, since the
packing on them is up to the driver. This fixes nir_validate assertions
in some cases, particularly when lower_io_to_temporaries is used on
per-vertex inputs/outputs.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agonir: don't segfault when printing variables with no name
Connor Abbott [Tue, 27 Jun 2017 00:07:21 +0000 (17:07 -0700)]
nir: don't segfault when printing variables with no name

While normally we give variables whose name field is NULL a temporary
name when called from nir_print_shader(), when we were calling from
nir_print_instr() we never bothered, meaning that we just segfaulted
when trying to print out instructions with such a variable. Since
nir_print_instr() is meant to be called while debugging, we don't need
to bother too much about giving a consistent name, but we don't want to
crash in the middle of debugging.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoi965/urb: Trigger upload_urb on NEW_BLORP
Jason Ekstrand [Tue, 11 Oct 2016 23:39:25 +0000 (16:39 -0700)]
i965/urb: Trigger upload_urb on NEW_BLORP

It's a bit rare, but blorp can trigger a urb reconfiguration.  When
that happens, we need to re-upload the URB config.  Previoulsy blorp
would set BRW_NEW_URB_SIZE, but this is a pretty big hammer as it
would cause back-to-black blorp operations to reconfigure both times.
Using BRW_NEW_BLORP is a small, more accurate hammer.

v2 (idr): Sort BRW_NEW_ tokens to match brw_recalculate_urb_fence and
gen6_urb.

v3 (idr): Don't whack BRW_NEW_URB_SIZE in blorp.  Suggested by Jason.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agomesa: Return GL_INVALID_ENUM for bogus TEXTURE_SRGB_DECODE_EXT params.
Kenneth Graunke [Thu, 13 Jul 2017 02:49:55 +0000 (19:49 -0700)]
mesa: Return GL_INVALID_ENUM for bogus TEXTURE_SRGB_DECODE_EXT params.

Fixes dEQP-GLES31.functional.debug.negative_coverage.get_error.shader.srgb_decode_samplerparameter{f,fv,i,Iiv,Iuiv,iv}.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
4 years agost/dri: add 32-bit RGBX/RGBA formats
Marek Olšák [Sun, 24 Apr 2016 09:51:52 +0000 (11:51 +0200)]
st/dri: add 32-bit RGBX/RGBA formats

Add support for 32-bit RGBX/RGBA formats which are required for Android.

The original patch (commit ccdcf91104a5) was reverted (commit
c0c6ca40a25e) in mesa as it broke GLX resulting in swapped colors. Based
on further investigation by Chad Versace, moving the RGBX/RGBA configs
to the end is enough to prevent breaking GLX.

The handling of RGBA/RGBX in dri_fill_st_visual is a fix from Marek
Olšák.

Cc: Eric Anholt <eric@anholt.net>
Cc: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
4 years agobroadcom/vc4: Add more packets to the v2.1 XML.
Eric Anholt [Wed, 12 Jul 2017 22:08:07 +0000 (15:08 -0700)]
broadcom/vc4: Add more packets to the v2.1 XML.

These will be used to replace vc4_cl_dump.c's hand-written dumping.

4 years agobroadcom: Introduce a header for talking about chip revisions.
Eric Anholt [Fri, 3 Feb 2017 01:45:00 +0000 (17:45 -0800)]
broadcom: Introduce a header for talking about chip revisions.

This will be used by the VC5 driver and various shared VC4/VC5 tooling,
like the XML decoder.

4 years agobroadcom/genxml: Use the same "gen" attr for HW version as Intel does.
Eric Anholt [Thu, 13 Jul 2017 18:02:37 +0000 (11:02 -0700)]
broadcom/genxml: Use the same "gen" attr for HW version as Intel does.

This will let us reuse their tools more easily.

4 years agobroadcom/genxml: Support unpacking fixed-point fractional values.
Eric Anholt [Fri, 30 Dec 2016 19:07:34 +0000 (11:07 -0800)]
broadcom/genxml: Support unpacking fixed-point fractional values.

This was an oversight in the original XML support, because unpacking
wasn't used much.  The new XML-based CL dumper will want it, though.

4 years agost/mesa: Handle st_framebuffer_create returning NULL
Michel Dänzer [Thu, 13 Jul 2017 07:21:00 +0000 (01:21 -0600)]
st/mesa: Handle st_framebuffer_create returning NULL

st_framebuffer_create returns NULL if stfbi == NULL or
st_framebuffer_add_renderbuffer returns false for the colour buffer.

Fixes Xorg crashing on startup using glamor on radeonsi.

Fixes: 147d7fb772a7 ("st/mesa: add a winsys buffers list in st_context")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101775
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
4 years agoswr/rast: Fix use of KNL-only intrinsics in SKX build
Tim Rowley [Thu, 29 Jun 2017 22:44:46 +0000 (17:44 -0500)]
swr/rast: Fix use of KNL-only intrinsics in SKX build

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: Fix build warnings when using the Intel compiler
Tim Rowley [Thu, 29 Jun 2017 22:22:05 +0000 (17:22 -0500)]
swr/rast: Fix build warnings when using the Intel compiler

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: SIMD16 Frontend - Fix USE_SIMD16_FRONTEND build
Tim Rowley [Wed, 28 Jun 2017 21:32:19 +0000 (16:32 -0500)]
swr/rast: SIMD16 Frontend - Fix USE_SIMD16_FRONTEND build

Previous check-ins without testing with USE_SIMD16_FRONTEND have
introduced regressions. This fixes the build, not the regressions.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: Removing unneeded MSVC warning pragma
Tim Rowley [Tue, 27 Jun 2017 21:24:05 +0000 (16:24 -0500)]
swr/rast: Removing unneeded MSVC warning pragma

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: Add support for read-only render targets
Tim Rowley [Mon, 26 Jun 2017 21:46:05 +0000 (16:46 -0500)]
swr/rast: Add support for read-only render targets

Core will ensure hot tiles are loaded for read and write render targets,
and will skip all output merger for read-only render targets.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: Support render target mask instead of render target count
Tim Rowley [Mon, 26 Jun 2017 17:32:01 +0000 (12:32 -0500)]
swr/rast: Support render target mask instead of render target count

WIP to support read-only render targets.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoegl: remove unused err variable
Alejandro Piñeiro [Thu, 13 Jul 2017 09:38:48 +0000 (11:38 +0200)]
egl: remove unused err variable

Fixes: 81e95924ea1 ("egl: call _eglError within _eglParseImageAttribList")
Reviewed-by: Daniel Stone <daniels@collabora.com>
4 years agoradeonsi/gfx9: fix crash building monolithic merged ES-GS shader
Nicolai Hähnle [Wed, 12 Jul 2017 13:38:57 +0000 (15:38 +0200)]
radeonsi/gfx9: fix crash building monolithic merged ES-GS shader

Forwarding from the ES prolog to the ES just barely exceeds the current
maximum array size when 16 vertex attributes are used. Give it a decent
bump to account for merged shaders having up to 32 user SGPRs.

Fixes a crash in GL45-CTS.multi_bind.draw_bind_vertex_buffers.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoloader/dri3: Use dri3_find_back in loader_dri3_swap_buffers_msc
Thomas Hellstrom [Tue, 4 Jul 2017 03:55:15 +0000 (12:55 +0900)]
loader/dri3: Use dri3_find_back in loader_dri3_swap_buffers_msc

If the application hasn't done any drawing since the last call, we
would reuse the same back buffer which was used for the previous swap,
which may not have completed yet. This could result in various issues
such as tearing or application hangs.

In the normal case, the behaviour is unchanged.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97957
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101683
Cc: mesa-stable@lists.freedesktop.org
[Michel Dänzer: Make Thomas' fix from bugzilla actually work as
 intended, write commit log]

4 years agoi965/screen: Drop get_tiled_height
Jason Ekstrand [Tue, 13 Jun 2017 01:57:45 +0000 (18:57 -0700)]
i965/screen: Drop get_tiled_height

It's no longer used.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/screen: Use ISL for doing image import checks
Jason Ekstrand [Tue, 13 Jun 2017 01:57:32 +0000 (18:57 -0700)]
i965/screen: Use ISL for doing image import checks

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/screen: Use ISL for allocating image BOs
Jason Ekstrand [Tue, 13 Jun 2017 01:21:09 +0000 (18:21 -0700)]
i965/screen: Use ISL for allocating image BOs

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agointel/isl: Add a helper to convert tilings from ISL to i915
Jason Ekstrand [Tue, 13 Jun 2017 00:52:41 +0000 (17:52 -0700)]
intel/isl: Add a helper to convert tilings from ISL to i915

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agointel/isl: Add basic modifier introspection
Jason Ekstrand [Mon, 12 Jun 2017 23:52:20 +0000 (16:52 -0700)]
intel/isl: Add basic modifier introspection

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965: Add an isl_device to intel_screen
Jason Ekstrand [Mon, 12 Jun 2017 23:02:00 +0000 (16:02 -0700)]
i965: Add an isl_device to intel_screen

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Move CCS allocation into create_for_dri_image
Jason Ekstrand [Fri, 16 Jun 2017 17:31:31 +0000 (10:31 -0700)]
i965/miptree: Move CCS allocation into create_for_dri_image

Any form of CCS on gen9+ only works on Y-tiled images.  The only caller
of create_for_bo which uses Y-tiled BOs is create_for_dri_image.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965: Use create_for_dri_image in intel_update_image_buffer
Jason Ekstrand [Fri, 16 Jun 2017 17:28:39 +0000 (10:28 -0700)]
i965: Use create_for_dri_image in intel_update_image_buffer

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Add support for window system images to create_for_dri_image
Jason Ekstrand [Fri, 16 Jun 2017 16:57:12 +0000 (09:57 -0700)]
i965/miptree: Add support for window system images to create_for_dri_image

We want to start using create_for_dri_image for all miptrees created
from __DRIimage, including those which come from a window system.  In
order to allow for fast clears to still work on window system buffers,
we need to allow for creating aux surfaces.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Add a colorspace parameter to create_for_dri_image
Jason Ekstrand [Fri, 16 Jun 2017 18:35:32 +0000 (11:35 -0700)]
i965/miptree: Add a colorspace parameter to create_for_dri_image

The __DRI_FORMAT enums are all UNORM but we will frequently want sRGB
when creating miptrees for renderbuffers.  This lets us specify.

Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agomain/formats: Add a get_linear_format_srgb helper
Jason Ekstrand [Wed, 28 Jun 2017 22:13:58 +0000 (15:13 -0700)]
main/formats: Add a get_linear_format_srgb helper

Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agomain/formats: Autogenerate _mesa_get_srgb_format_linear
Jason Ekstrand [Wed, 28 Jun 2017 22:10:34 +0000 (15:10 -0700)]
main/formats: Autogenerate _mesa_get_srgb_format_linear

Due to the wonders of autogeneration, this new version covers a few
formats that the old version was missing:

    MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5
    MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6

Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Allocate mt earlier in update winsys
Ben Widawsky [Tue, 30 May 2017 11:53:58 +0000 (17:23 +0530)]
i965/miptree: Allocate mt earlier in update winsys

Later commits require intel_update_image_buffer() to have control over
the miptree creation.   However, intel_update_winsys_renderbuffer_miptree()
currently  creates it based on the given buffer object. This patch moves
the creation to the caller side.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Add a return for updating of winsys
Ben Widawsky [Tue, 30 May 2017 11:53:57 +0000 (17:23 +0530)]
i965/miptree: Add a return for updating of winsys

There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.

v2: Make the return type a bool (Topi)

v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason)

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v2)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965: Use miptree_create_for_dri_image in image_target_renderbuffer_storage
Jason Ekstrand [Mon, 12 Jun 2017 17:40:46 +0000 (10:40 -0700)]
i965: Use miptree_create_for_dri_image in image_target_renderbuffer_storage

This does make a tiny functional change in that we now also test for
whether or not the format supports texturing and not just rendering.
However, this should have no practical effect as all renderbuffers use
texturable formats.

Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Set level_x/h in create_for_dri_image
Jason Ekstrand [Mon, 12 Jun 2017 17:38:48 +0000 (10:38 -0700)]
i965/miptree: Set level_x/h in create_for_dri_image

Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Add tile_x/y to total_width/height
Jason Ekstrand [Mon, 12 Jun 2017 17:36:18 +0000 (10:36 -0700)]
i965/miptree: Add tile_x/y to total_width/height

This is what we do in intel_image_target_renderbuffer_storage and it
makes more sense than stomping them.  Because the image gets created as
a 2D image with one miplevel, they should already be equal to the
provided width/height.  Adding the tile offset makes some sense
depending on how you interpret the fields.

The only place these fields are used for in state setup is to set up the
image parameters we pass into shaders.  There may be issues here if you
try to use image_load_store on something pulled in from EGL but that's
probably broken already.  This just makes it consistently broken.

Reviewed-by: Chad Versace <chadversary@chromium.org>
4 years agoi965/miptree: Pass the offset into create_for_bo in create_for_dri_image
Jason Ekstrand [Mon, 12 Jun 2017 17:30:44 +0000 (10:30 -0700)]
i965/miptree: Pass the offset into create_for_bo in create_for_dri_image

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
4 years agoi965: Move the DRIimage -> miptree code to intel_mipmap_tree.c
Jason Ekstrand [Mon, 12 Jun 2017 17:25:26 +0000 (10:25 -0700)]
i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c

This is mostly a direct port.  The only bit of refactoring that was done
was to make creating a planar miptree be an early return from the
non-planar case.  Alternatively, we could have three functions: two
helpers and a main function to just call the right helper.  Making the
planar case an early return seemed cleaner.

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
4 years agonv50/ir: fix threads calculation for non-compute shaders
Ilia Mirkin [Tue, 11 Jul 2017 00:58:31 +0000 (20:58 -0400)]
nv50/ir: fix threads calculation for non-compute shaders

We were using the "cp" union fields, which are only valid for compute
shaders. The threads calculation affects the available GPRs, so just
pick a small number for other shader types to avoid limiting available
registers.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
4 years agofreedreno/ir3: fix load_front_face conversion
Ilia Mirkin [Wed, 12 Jul 2017 01:44:12 +0000 (21:44 -0400)]
freedreno/ir3: fix load_front_face conversion

The comments are correct - we get -1 and 0. However by adding 1, we
convert this into 0,1. This mostly works for conditionals, but when
negated, this will yield the wrong result. Instead just negate the
values (as they are backwards -- -1 means back instead of front).

Fixes tests/shaders/glsl-fs-frontfacing-not.shader_test and
dEQP-GLES3.functional.shaders.builtin_variable.frontfacing on A530.

The latter also tested on A306 by Rob Clark.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
4 years agoradv: Fix descriptors for cube images with VK_IMAGE_USAGE_STORAGE_BIT
Alex Smith [Wed, 12 Jul 2017 09:29:52 +0000 (10:29 +0100)]
radv: Fix descriptors for cube images with VK_IMAGE_USAGE_STORAGE_BIT

If a cube image has VK_IMAGE_USAGE_STORAGE_BIT set, the type in an image
view's descriptor was set to a 2D array (and a few other fields adjusted
accordingly). This is correct when the image view is actually bound as a
storage image, but not when bound as a sampled image. In that case the
type should be set as a cube.

Fix by generating 2 sets of descriptors at view creation time for both
storage and non-storage usage, and then choose between them based on
descriptor type when writing descriptor sets.

v2: Generate storage descriptors for images with TRANSFER_DST, since
    those may be used as storage images internally.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: Fix possible invalid free of dynamic descriptors
Alex Smith [Wed, 12 Jul 2017 10:14:21 +0000 (11:14 +0100)]
radv: Fix possible invalid free of dynamic descriptors

This free was left in after dynamic descriptors were changed to not be
allocated separately from the descriptor set, and can cause a crash.

Fixes: 39644fa40a3 ("radv: Don't allocate dynamic descriptors separately")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoswr: Add path to draw directly from client memory without copy.
Bruce Cherniak [Wed, 12 Jul 2017 20:04:47 +0000 (15:04 -0500)]
swr: Add path to draw directly from client memory without copy.

If size of client memory copy is too large, don't copy. The draw will
access user-buffer directly and then block.  This is faster and more
efficient than queuing many large client draws.

Applications that still use large client arrays benefit from this.  VMD
is an example.

The threshold for this path defaults to 32KB.  This value can be
overridden by setting environment variable SWR_CLIENT_COPY_LIMIT.

v2: Use #define for default value, rather than hard-coded constant.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
4 years agoswr: Move environment config options into separate function.
Bruce Cherniak [Wed, 12 Jul 2017 20:04:46 +0000 (15:04 -0500)]
swr: Move environment config options into separate function.

Moved reading of environment config options out of
swr_create_screen_internal, into a separate swr_validate_env_options.
This is to keep from cluttering create_screen.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
4 years agoswr: Remove hard-coded constant and "todo" comment.
Bruce Cherniak [Wed, 12 Jul 2017 20:04:45 +0000 (15:04 -0500)]
swr: Remove hard-coded constant and "todo" comment.

Removed the hard-coded constant in favor of a #define.  Also removed
TODO comment.  The constant value doesn't need an environment
configurable option.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
4 years agoAndroid: Fix vc4 build since XML changes.
Rob Herring [Wed, 5 Jul 2017 18:19:58 +0000 (11:19 -0700)]
Android: Fix vc4 build since XML changes.

Since commit 7f80a9ff1312 ("vc4: Introduce XML-based packet header
generation like Intel's."), the vc4 build on Android is broken:

out/target/product/linaro_x86_64/gen/STATIC_LIBRARIES/libmesa_broadcom_genxml_intermediates/broadcom/cle/v3d_packet_v21_pack.h:12:10: fatal error: 'v3d_packet_helpers.h' file not found
external/mesa3d/src/gallium/drivers/vc4/vc4_cl_dump.c:28:10: fatal error: 'vc4_packet.h' file not found

The path of the generated header needs to be fixed since we build out of
tree.

Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Herring <robh@kernel.org>
4 years agost/mesa: add a winsys buffers list in st_context
Charmaine Lee [Tue, 11 Jul 2017 06:06:11 +0000 (23:06 -0700)]
st/mesa: add a winsys buffers list in st_context

Commit a5e733c6b52e93de3000647d075f5ca2f55fcb71 fixes the dangling
framebuffer object by unreferencing the window system draw/read buffers
when context is released. However this can prematurely destroy the
resources associated with these window system buffers. The problem is
reproducible with Turbine Demo running with VMware driver. In this case,
the depth buffer content was lost when the context is rebound to a
drawable.

To prevent premature destroy of the resources associated with
window system buffers, this patch maintains a list of these buffers in
the context, making sure the reference counts of these buffers will not
reach zero until the associated framebuffer interface objects no
longer exist. This also helps to avoid unnecessary destruction and
re-construction of the resources associated with the framebuffer.

Fixes VMware bug 1909807.

Reviewed-by: Brian Paul <brianp@vmware.com>
4 years agoi965: Drop bogus pthread_mutex_unlock in map_gtt error path.
Kenneth Graunke [Tue, 11 Jul 2017 21:01:20 +0000 (14:01 -0700)]
i965: Drop bogus pthread_mutex_unlock in map_gtt error path.

The locking was supposed to go away in commit 314647c4c206917ec01b7
(i965: Drop global bufmgr lock from brw_bo_map_* functions.), but
this lone unlock remains.

I'm guessing I messed this up when splitting up Chris's patch.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
4 years agointel/compiler: Don't use opt_sampler_eot() optimization on gen10+
Anuj Phogat [Tue, 27 Jun 2017 22:16:35 +0000 (15:16 -0700)]
intel/compiler: Don't use opt_sampler_eot() optimization on gen10+

This optimization has been removed on gen10+.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agovc4: Set shareable BOs as T tiled if possible
Eric Anholt [Mon, 5 Jun 2017 21:50:26 +0000 (14:50 -0700)]
vc4: Set shareable BOs as T tiled if possible

X11 and GL compositor performance on VC4 has been terrible because of our
SHARED-usage buffers all being forced to linear.  This swaps SHARED &&
!LINEAR buffers over to being tiled.

This is an expected win for all GL compositors during rendering (a full
copy of each shared texture per draw call), allows X11 to be used with
decent performance without a GL compositor, and improves X11 windowed
swapbuffers performance as well.  It also halves the memory usage of
shared buffers that get textured from.  The only cost should be idle
systems with a scanout-only buffer that isn't flagged as LINEAR, in which
case the memory bandwidth cost of scanout goes up ~25%.

This implements the EGL_EXT_image_dma_buf_import_modifiers extension,
supporting the VC4 T_TILED modifier.

v2: Added modifier support to resource creation/import, and
    advertisement (by daniels).
v3: Fix old-kernel fallback path, fix compiler error and warnings, and
    comment touchups (by anholt).

Reviewed-by: Daniel Stone <daniels@collabora.com>
4 years agovc4: Use vc4_setup_slices for resource import
Eric Anholt [Thu, 22 Jun 2017 18:45:08 +0000 (19:45 +0100)]
vc4: Use vc4_setup_slices for resource import

Rather than open-coding populating the first slice inside resource
import, use vc4_setup_slices to do it for us.

v2: Rebase on VC4_DEBUG=surf change

Reviewed-by: Daniel Stone <daniels@collabora.com>
4 years agovc4: Make the miptree debug code available under VC4_DEBUG=surf
Eric Anholt [Thu, 29 Jun 2017 00:39:34 +0000 (17:39 -0700)]
vc4: Make the miptree debug code available under VC4_DEBUG=surf

I kept flipping the bool on for debug, so let's just make it available.

Reviewed-by: Daniel Stone <daniels@collabora.com>
4 years agovc4: Switch back to using a local copy of vc4_drm.h.
Eric Anholt [Thu, 15 Jun 2017 23:52:22 +0000 (16:52 -0700)]
vc4: Switch back to using a local copy of vc4_drm.h.

Needing to get our uapi header from libdrm has only complicated things.
Follow intel's lead and drop our requirement for it.

Generated from the same commit mentioned in the README.

v2: Update Android.mk as well, move vc4_drm.h reference for distcheck.

Reviewed-by: Daniel Stone <daniels@collabora.com>
4 years agointel: Move the DRM uapi headers to a non-Intel location.
Eric Anholt [Wed, 28 Jun 2017 23:35:55 +0000 (16:35 -0700)]
intel: Move the DRM uapi headers to a non-Intel location.

I want to remove vc4's dependency on headers from libdrm as well, but
storing multiple copies of drm_fourcc.h in our tree would be silly.

v2: Update Android.mk as well, move distcheck drm*.h references to
    top-level noinst_HEADERS.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Daniel Stone <daniels@collabora.com> (v1)
Reviewed-by: Rob Herring <robh@kernel.org>
4 years agovc4: Remove a stale comment.
Eric Anholt [Wed, 12 Jul 2017 16:41:21 +0000 (09:41 -0700)]
vc4: Remove a stale comment.

The kernel hasn't been synchronous in a couple of years, plus there was
synchronization code right there.

4 years agoanv: Round u_vector element sizes to a power of two
Jason Ekstrand [Wed, 12 Jul 2017 02:04:38 +0000 (19:04 -0700)]
anv: Round u_vector element sizes to a power of two

This fixes 32-bit builds of the driver.  Commit 08413a81b93dc537fb0c3
changed things so that we now put struct anv_states in the u_vector for
binding tables.  On 64-bit builds, sizeof(struct anv_state) is a power
of two but it isn't on 32-bit builds.

Fixes: 08413a81b93dc537fb0c34327ad162f07e8c3427
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
4 years agosvga: whitespace, formatting fixes in svga_swtnl_backend.c
Brian Paul [Wed, 12 Jul 2017 16:27:43 +0000 (10:27 -0600)]
svga: whitespace, formatting fixes in svga_swtnl_backend.c

4 years agosvga: whitespace, formatting fixes in svga_swtnl_draw.c
Brian Paul [Wed, 12 Jul 2017 16:25:10 +0000 (10:25 -0600)]
svga: whitespace, formatting fixes in svga_swtnl_draw.c