mesa.git
17 months agov3d/tex: set up default values for Configuration Parameter 1 if possible
Alejandro Piñeiro [Wed, 29 Apr 2020 08:29:50 +0000 (10:29 +0200)]
v3d/tex: set up default values for Configuration Parameter 1 if possible

Texture access has three configuration parameters, P0 (texture), P1
(sampler) and P2(lookup). P1 and P2 are optional, but if P2 is needed
(like for example to set the offset for texelFetchOffset), then you
need to set P1.

But until now when setting up P1 we were asking the driver to fill up
the address with the shader state. But in that case we can just fill
that address with the default value NULL.

So let's avoid asking the driver to fill that default values, and do
it directly on the compiler. This is a good-to-have on OpenGL, and
likely would be needed on Vulkan.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4962>

17 months agov3d/tex: only look up the 2nd texture gather offset for 1d non-arrays
Alejandro Piñeiro [Tue, 28 Apr 2020 22:33:47 +0000 (00:33 +0200)]
v3d/tex: only look up the 2nd texture gather offset for 1d non-arrays

Commit 1bc71e8b655f2f02b3e3a0af34c7cad12b9cb83d already did that for
the 3rd offset, but it also needs to do it for the 2nd (to handle 1d
array).

Fixes assertion failures with Vulkan CTS tests using 1darray
targets. Seems that there isn't too many 1darray tests on OpenGL CTS,
and OpenGL-ES don't support 1d arrays, but the same problem could
arise eventually on OpenGL.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4962>

17 months agodrirc: Enable glthread for rpcs3
Ani [Mon, 11 May 2020 14:45:47 +0000 (14:45 +0000)]
drirc: Enable glthread for rpcs3

Closes: #2939
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4988>

17 months agopan/midgard: Fix old style shadows
Icecream95 [Mon, 11 May 2020 22:16:31 +0000 (10:16 +1200)]
pan/midgard: Fix old style shadows

This fixes the sky being red in OpenMW, as well as some of the Mesa
demos using shadows (shadowtex, shadow_sampler).

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4997>

17 months agogallium/util: Fix leak in the live shader cache
Axel Davy [Sun, 10 May 2020 18:12:56 +0000 (20:12 +0200)]
gallium/util: Fix leak in the live shader cache

When the nir backend is used, the create_shader
call is supposed to release state->ir.nir.
When the cache hits, create_shader is not called,
thus state->ir.nir should be freed.

There is nothing to be done for the TGSI case as the
tokens release is done by the caller.

This fixes a leak noticed in:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/2931

Fixes: 4bb919b0b8b4ed6f6a7049c3f8d294b74b50e198
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4980>

17 months agonir/algebraic: Eliminate useless extract before unpack
Ian Romanick [Tue, 31 Mar 2020 23:57:03 +0000 (16:57 -0700)]
nir/algebraic: Eliminate useless extract before unpack

The shader helped for spills and fills is the big compute shader in Dirt
Showdown.  One of the shaders hurt for spills and fills on Broadwell is
the big compute shader in Bioshock Infinite, but combined with the
previous commit, it's still an impovement.

Tiger Lake
total instructions in shared programs: 21833218 -> 21832449 (<.01%)
instructions in affected programs: 66104 -> 65335 (-1.16%)
helped: 106
HURT: 14
helped stats (abs) min: 1 max: 67 x̄: 7.87 x̃: 5
helped stats (rel) min: 0.19% max: 5.76% x̄: 1.27% x̃: 0.95%
HURT stats (abs)   min: 1 max: 14 x̄: 4.64 x̃: 1
HURT stats (rel)   min: 0.19% max: 4.12% x̄: 1.41% x̃: 0.19%
95% mean confidence interval for instructions value: -8.51 -4.30
95% mean confidence interval for instructions %-change: -1.23% -0.69%
Instructions are helped.

total cycles in shared programs: 506180109 -> 506196314 (<.01%)
cycles in affected programs: 1671429 -> 1687634 (0.97%)
helped: 37
HURT: 84
helped stats (abs) min: 1 max: 490 x̄: 73.27 x̃: 24
helped stats (rel) min: 0.02% max: 7.98% x̄: 1.25% x̃: 0.41%
HURT stats (abs)   min: 1 max: 5000 x̄: 225.19 x̃: 8
HURT stats (rel)   min: 0.03% max: 10.22% x̄: 1.22% x̃: 0.42%
95% mean confidence interval for cycles value: 2.85 265.00
95% mean confidence interval for cycles %-change: 0.04% 0.88%
Cycles are HURT.

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 19961317 -> 19960543 (<.01%)
instructions in affected programs: 30268 -> 29494 (-2.56%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 142 x̄: 19.85 x̃: 7
helped stats (rel) min: 0.19% max: 7.87% x̄: 2.33% x̃: 2.31%
95% mean confidence interval for instructions value: -29.46 -10.23
95% mean confidence interval for instructions %-change: -2.95% -1.71%
Instructions are helped.

total cycles in shared programs: 498863755 -> 498865843 (<.01%)
cycles in affected programs: 1831136 -> 1833224 (0.11%)
helped: 57
HURT: 65
helped stats (abs) min: 1 max: 1400 x̄: 128.93 x̃: 25
helped stats (rel) min: 0.05% max: 3.49% x̄: 0.89% x̃: 0.71%
HURT stats (abs)   min: 1 max: 1887 x̄: 145.18 x̃: 15
HURT stats (rel)   min: 0.02% max: 9.88% x̄: 1.83% x̃: 0.73%
95% mean confidence interval for cycles value: -58.30 92.53
95% mean confidence interval for cycles %-change: 0.16% 0.97%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 8774 -> 8773 (-0.01%)
spills in affected programs: 20 -> 19 (-5.00%)
helped: 1
HURT: 0

total fills in shared programs: 9496 -> 9494 (-0.02%)
fills in affected programs: 40 -> 38 (-5.00%)
helped: 1
HURT: 0

Broadwell
total instructions in shared programs: 17859373 -> 17858548 (<.01%)
instructions in affected programs: 38452 -> 37627 (-2.15%)
helped: 31
HURT: 0
helped stats (abs) min: 1 max: 143 x̄: 26.61 x̃: 10
helped stats (rel) min: 0.19% max: 7.87% x̄: 2.57% x̃: 2.69%
95% mean confidence interval for instructions value: -39.79 -13.44
95% mean confidence interval for instructions %-change: -3.25% -1.89%
Instructions are helped.

total cycles in shared programs: 525858109 -> 525869236 (<.01%)
cycles in affected programs: 2058597 -> 2069724 (0.54%)
helped: 44
HURT: 75
helped stats (abs) min: 2 max: 1330 x̄: 187.84 x̃: 23
helped stats (rel) min: 0.04% max: 31.31% x̄: 2.13% x̃: 0.85%
HURT stats (abs)   min: 1 max: 3915 x̄: 258.56 x̃: 47
HURT stats (rel)   min: 0.02% max: 10.53% x̄: 2.81% x̃: 2.21%
95% mean confidence interval for cycles value: -26.06 213.07
95% mean confidence interval for cycles %-change: 0.19% 1.78%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 25744 -> 25730 (-0.05%)
spills in affected programs: 1578 -> 1564 (-0.89%)
helped: 4
HURT: 2

total fills in shared programs: 31710 -> 31689 (-0.07%)
fills in affected programs: 4346 -> 4325 (-0.48%)
helped: 3
HURT: 3

Haswell
total instructions in shared programs: 16228399 -> 16227783 (<.01%)
instructions in affected programs: 22201 -> 21585 (-2.77%)
helped: 27
HURT: 0
helped stats (abs) min: 1 max: 68 x̄: 22.81 x̃: 11
helped stats (rel) min: 0.19% max: 7.87% x̄: 2.92% x̃: 2.86%
95% mean confidence interval for instructions value: -31.96 -13.66
95% mean confidence interval for instructions %-change: -3.68% -2.15%
Instructions are helped.

total cycles in shared programs: 538613967 -> 538701354 (0.02%)
cycles in affected programs: 1653044 -> 1740431 (5.29%)
helped: 36
HURT: 81
helped stats (abs) min: 2 max: 708 x̄: 104.50 x̃: 17
helped stats (rel) min: <.01% max: 15.01% x̄: 1.67% x̃: 0.65%
HURT stats (abs)   min: 1 max: 30100 x̄: 1125.30 x̃: 304
HURT stats (rel)   min: 0.02% max: 16.21% x̄: 8.98% x̃: 11.60%
95% mean confidence interval for cycles value: 23.78 1470.01
95% mean confidence interval for cycles %-change: 4.29% 7.12%
Cycles are HURT.

total spills in shared programs: 23418 -> 23409 (-0.04%)
spills in affected programs: 177 -> 168 (-5.08%)
helped: 2
HURT: 0

total fills in shared programs: 25919 -> 25896 (-0.09%)
fills in affected programs: 568 -> 545 (-4.05%)
helped: 3
HURT: 0

Ivy Bridge
total instructions in shared programs: 15265983 -> 15265759 (<.01%)
instructions in affected programs: 8418 -> 8194 (-2.66%)
helped: 5
HURT: 0
helped stats (abs) min: 18 max: 99 x̄: 44.80 x̃: 26
helped stats (rel) min: 1.74% max: 4.26% x̄: 3.12% x̃: 3.00%
95% mean confidence interval for instructions value: -86.29 -3.31
95% mean confidence interval for instructions %-change: -4.43% -1.81%
Instructions are helped.

total cycles in shared programs: 422930336 -> 422929589 (<.01%)
cycles in affected programs: 59347 -> 58600 (-1.26%)
helped: 3
HURT: 2
helped stats (abs) min: 72 max: 1060 x̄: 433.33 x̃: 168
helped stats (rel) min: 1.14% max: 3.48% x̄: 2.23% x̃: 2.06%
HURT stats (abs)   min: 265 max: 288 x̄: 276.50 x̃: 276
HURT stats (rel)   min: 4.79% max: 5.64% x̄: 5.22% x̃: 5.22%
95% mean confidence interval for cycles value: -829.08 530.28
95% mean confidence interval for cycles %-change: -4.43% 5.93%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 4953 -> 4946 (-0.14%)
spills in affected programs: 344 -> 337 (-2.03%)
helped: 2
HURT: 0

total fills in shared programs: 5548 -> 5521 (-0.49%)
fills in affected programs: 838 -> 811 (-3.22%)
helped: 2
HURT: 0

No shader-db changes on any earlier Intel platform.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4515>

17 months agonir/algebraic: Add some half packing optimizations for pack_half_2x16_split
Ian Romanick [Thu, 2 Apr 2020 19:20:57 +0000 (12:20 -0700)]
nir/algebraic: Add some half packing optimizations for pack_half_2x16_split

Like 1f72857739b ("nir/algebraic: add some half packing optimizations"),
but for the pack_half_2x16_split variant.

The shader helped for spills and fills is the big compute shader in
Bioshock Infinite.

Tiger Lake
total instructions in shared programs: 21834539 -> 21833218 (<.01%)
instructions in affected programs: 60119 -> 58798 (-2.20%)
helped: 105
HURT: 0
helped stats (abs) min: 5 max: 50 x̄: 12.58 x̃: 9
helped stats (rel) min: 0.86% max: 26.46% x̄: 2.58% x̃: 1.70%
95% mean confidence interval for instructions value: -14.35 -10.81
95% mean confidence interval for instructions %-change: -3.20% -1.97%
Instructions are helped.

total cycles in shared programs: 506215169 -> 506180109 (<.01%)
cycles in affected programs: 1445088 -> 1410028 (-2.43%)
helped: 97
HURT: 8
helped stats (abs) min: 1 max: 16882 x̄: 387.76 x̃: 26
helped stats (rel) min: 0.05% max: 18.31% x̄: 1.77% x̃: 1.34%
HURT stats (abs)   min: 21 max: 635 x̄: 319.12 x̃: 212
HURT stats (rel)   min: 0.39% max: 20.08% x̄: 8.96% x̃: 4.46%
95% mean confidence interval for cycles value: -782.96 115.15
95% mean confidence interval for cycles %-change: -1.74% -0.16%
Inconclusive result (value mean confidence interval includes 0).

Ice Lake, Skylake, and Broadwell had similar results. (Ice Lake shown)
total instructions in shared programs: 19962974 -> 19961317 (<.01%)
instructions in affected programs: 63471 -> 61814 (-2.61%)
helped: 105
HURT: 0
helped stats (abs) min: 6 max: 82 x̄: 15.78 x̃: 11
helped stats (rel) min: 1.11% max: 28.65% x̄: 3.17% x̃: 2.16%
95% mean confidence interval for instructions value: -18.38 -13.18
95% mean confidence interval for instructions %-change: -3.86% -2.48%
Instructions are helped.

total cycles in shared programs: 498908953 -> 498863755 (<.01%)
cycles in affected programs: 1566998 -> 1521800 (-2.88%)
helped: 89
HURT: 15
helped stats (abs) min: 2 max: 17502 x̄: 532.19 x̃: 69
helped stats (rel) min: 0.07% max: 18.54% x̄: 4.71% x̃: 3.12%
HURT stats (abs)   min: 3 max: 661 x̄: 144.47 x̃: 16
HURT stats (rel)   min: 0.14% max: 20.57% x̄: 4.29% x̃: 0.30%
95% mean confidence interval for cycles value: -903.93 34.74
95% mean confidence interval for cycles %-change: -4.50% -2.32%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 8776 -> 8774 (-0.02%)
spills in affected programs: 25 -> 23 (-8.00%)
helped: 1
HURT: 0

total fills in shared programs: 9500 -> 9496 (-0.04%)
fills in affected programs: 46 -> 42 (-8.70%)
helped: 1
HURT: 0

Haswell
total instructions in shared programs: 16229912 -> 16228399 (<.01%)
instructions in affected programs: 61257 -> 59744 (-2.47%)
helped: 105
HURT: 0
helped stats (abs) min: 6 max: 51 x̄: 14.41 x̃: 11
helped stats (rel) min: 0.77% max: 28.65% x̄: 3.08% x̃: 2.15%
95% mean confidence interval for instructions value: -16.14 -12.68
95% mean confidence interval for instructions %-change: -3.77% -2.40%
Instructions are helped.

total cycles in shared programs: 538654481 -> 538613967 (<.01%)
cycles in affected programs: 1448966 -> 1408452 (-2.80%)
helped: 58
HURT: 47
helped stats (abs) min: 9 max: 22604 x̄: 957.00 x̃: 74
helped stats (rel) min: 0.40% max: 18.81% x̄: 6.22% x̃: 3.03%
HURT stats (abs)   min: 5 max: 3720 x̄: 318.98 x̃: 49
HURT stats (rel)   min: 0.20% max: 34.50% x̄: 5.05% x̃: 2.12%
95% mean confidence interval for cycles value: -999.84 228.14
95% mean confidence interval for cycles %-change: -2.86% 0.51%
Inconclusive result (value mean confidence interval includes 0).

Ivy Bridge
total instructions in shared programs: 15266086 -> 15265983 (<.01%)
instructions in affected programs: 7272 -> 7169 (-1.42%)
helped: 3
HURT: 0
helped stats (abs) min: 21 max: 41 x̄: 34.33 x̃: 41
helped stats (rel) min: 0.66% max: 5.43% x̄: 2.44% x̃: 1.23%

total cycles in shared programs: 422930883 -> 422930336 (<.01%)
cycles in affected programs: 49259 -> 48712 (-1.11%)
helped: 3
HURT: 0
helped stats (abs) min: 106 max: 221 x̄: 182.33 x̃: 220
helped stats (rel) min: 0.71% max: 5.95% x̄: 2.46% x̃: 0.72%

No changes on any earilier Intel platforms.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4515>

17 months agonir/algebraic: Optimize ushr of pack_half, not ishr
Ian Romanick [Thu, 2 Apr 2020 19:14:12 +0000 (12:14 -0700)]
nir/algebraic: Optimize ushr of pack_half, not ishr

When a = -1.0, pack_half_2x16(vec2(0x0000, 0xBC00)) will produce
0xBC000000.  The ishr will produce 0xFFFFBC00.  The replacement
pack_half_2x16(vec2(0xBC00, 0x0000)) will produce 0x0000BC00.

Fixes: 1f72857739b ("nir/algebraic: add some half packing optimizations")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4515>

17 months agointel: Delete hardcoded devinfo->urb.size values for Gen7+ (sans DG1).
Kenneth Graunke [Fri, 8 May 2020 19:51:11 +0000 (12:51 -0700)]
intel: Delete hardcoded devinfo->urb.size values for Gen7+ (sans DG1).

On all Gen7+ platforms except DG1, the URB is a subsection of the
configurable L3 cache, and so the size can vary.  The size listed
in the documentation on those platforms is an "example size", picked
by calculating it based on an arbitrarily chosen L3 config.

Hardcoding a value for those platforms provides no value and only
confuses people trying to fill out these tables when doing hardware
enabling.  anv and iris never use this field.  i965 uses it to
initialize brw->urb.size, but then updates that in update_urb_size()
to be the correct value, so the initial value doesn't matter.

Delete the values for Gen7+ and update the comment accordingly.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4969>

17 months agoegl: Limit the EGL ver for android
Abhishek Kumar [Thu, 7 May 2020 16:32:02 +0000 (22:02 +0530)]
egl: Limit the EGL ver for android

Android support EGL 1.5 from Q onwards,
so limit EGL ver to 1.4 for P and below.

Closes: #2892
Signed-off-by: Abhishek Kumar <abhishek4.kumar@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4951>

17 months agoamd/common: Fix incorrect use of asprintf instead of vasprintf
Serge Martin [Sun, 10 May 2020 16:23:25 +0000 (18:23 +0200)]
amd/common: Fix incorrect use of asprintf instead of vasprintf

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
17 months agodocs/features: mark GL_NV_conditional_render as done for zink
Erik Faye-Lund [Thu, 30 Apr 2020 18:01:22 +0000 (20:01 +0200)]
docs/features: mark GL_NV_conditional_render as done for zink

Requires VK_EXT_conditional_rendering.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4835>

17 months agozink: enable conditional rendering if available
Dave Airlie [Sun, 14 Oct 2018 23:15:50 +0000 (00:15 +0100)]
zink: enable conditional rendering if available

This doesn't seem to work perfect, but I'm not sure what is possible
in GL vs Vulkan here

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2867
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4835>

17 months agozink: add a GET_PROC_ADDR macro to simplify load_device_extensions
Erik Faye-Lund [Fri, 8 May 2020 10:07:48 +0000 (12:07 +0200)]
zink: add a GET_PROC_ADDR macro to simplify load_device_extensions

This doesn't do much for now, but it will keep thing cleaner in the next
commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4835>

17 months agozink: load vk_GetMemoryFdKHR while creating screen
Erik Faye-Lund [Thu, 30 Apr 2020 17:06:51 +0000 (19:06 +0200)]
zink: load vk_GetMemoryFdKHR while creating screen

We're about to load some more extension-pointers as well, so let's
create a separate place for doing this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4835>

17 months agoradeonsi: do not use cmask with encrypted texture
Pierre-Eric Pelloux-Prayer [Thu, 7 May 2020 19:45:49 +0000 (21:45 +0200)]
radeonsi: do not use cmask with encrypted texture

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeonsi: determine secure flag must be set for gfx IB
Pierre-Eric Pelloux-Prayer [Tue, 25 Feb 2020 20:56:12 +0000 (21:56 +0100)]
radeonsi: determine secure flag must be set for gfx IB

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoamdgpu: use AMDGPU_IB_FLAGS_SECURE when requested
Pierre-Eric Pelloux-Prayer [Fri, 28 Feb 2020 10:54:41 +0000 (11:54 +0100)]
amdgpu: use AMDGPU_IB_FLAGS_SECURE when requested

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeonsi: add support for PIPE_RESOURCE_FLAG_ENCRYPTED
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 09:33:56 +0000 (10:33 +0100)]
radeonsi: add support for PIPE_RESOURCE_FLAG_ENCRYPTED

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agogallium: PIPE_RESOURCE_FLAG_ENCRYPTED
Pierre-Eric Pelloux-Prayer [Mon, 27 Apr 2020 09:21:35 +0000 (11:21 +0200)]
gallium: PIPE_RESOURCE_FLAG_ENCRYPTED

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeonsi/sdma: implement tmz support
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 09:29:31 +0000 (10:29 +0100)]
radeonsi/sdma: implement tmz support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeonsi: force using staging texture when uploading to secure texture
Pierre-Eric Pelloux-Prayer [Fri, 28 Feb 2020 16:10:45 +0000 (17:10 +0100)]
radeonsi: force using staging texture when uploading to secure texture

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoamdgpu: add encrypted slabs support
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 09:40:02 +0000 (10:40 +0100)]
amdgpu: add encrypted slabs support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeonsi: allocate framebuffer texture as secure when using tmz
Pierre-Eric Pelloux-Prayer [Fri, 28 Feb 2020 13:25:54 +0000 (14:25 +0100)]
radeonsi: allocate framebuffer texture as secure when using tmz

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeon: add RADEON_CREATE_ENCRYPTED flag
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 09:33:43 +0000 (10:33 +0100)]
radeon: add RADEON_CREATE_ENCRYPTED flag

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoradeonsi: add AMD_DEBUG=tmz option
Pierre-Eric Pelloux-Prayer [Fri, 28 Feb 2020 13:24:29 +0000 (14:24 +0100)]
radeonsi: add AMD_DEBUG=tmz option

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoamdgpu/radeon: add secure api
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 09:28:10 +0000 (10:28 +0100)]
amdgpu/radeon: add secure api

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

17 months agoac/surface: remove shadowing declaration
Pierre-Eric Pelloux-Prayer [Mon, 11 May 2020 07:18:49 +0000 (09:18 +0200)]
ac/surface: remove shadowing declaration

Fixes: 7691de0dcef ("ac/surface,radeonsi: move the set/get_bo_metadata code to ac_surface.c")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2929
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4983>

17 months agoaco: prevent invalid loads/stores vectorization if robustness is enabled
Samuel Pitoiset [Mon, 4 May 2020 14:03:35 +0000 (16:03 +0200)]
aco: prevent invalid loads/stores vectorization if robustness is enabled

Only UBO, SSBO, global and push constants accesses should matter.

This fixes a bunch of new robustness2 failures. Note that RADV/LLVM
isn't affected because it relies on LLVM for loads/stores
vectorization and LLVM doesn't vectorize in this situation as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4881>

17 months agonir: do not vectorize load/store if offset can overflow and robustness enabled
Samuel Pitoiset [Mon, 4 May 2020 14:02:38 +0000 (16:02 +0200)]
nir: do not vectorize load/store if offset can overflow and robustness enabled

This prevents vectorization for loads/stores that can overflow if
the low offset is negative and the range greater or equal than 0.

The caller can pass the list of variable modes that matter for
robust access.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4881>

17 months agoaco: fix 64-bit trunc with negative exponents on GFX6
Samuel Pitoiset [Wed, 6 May 2020 13:34:07 +0000 (15:34 +0200)]
aco: fix 64-bit trunc with negative exponents on GFX6

v_frexp_exp returns the exponent as an unsigned value.

Also, v_ashr returns either 0 or -1 depending on the sign of the
source operand, but what we want is only the sign bit.

Fixes a bunch of recent dEQP-VK.glsl.builtin.precision_double.* tests.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4921>

17 months agoetnaviv: drm: Normalize nano seconds
Guido Günther [Thu, 23 Jan 2020 08:20:00 +0000 (09:20 +0100)]
etnaviv: drm: Normalize nano seconds

Make sure the nano second part is less than one second. This matches
what clock_settime expects and allows for more concise kernel
interfaces.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3534>

17 months agoetnaviv: drm: Use NSEC_PER_SEC
Guido Günther [Thu, 23 Jan 2020 08:17:07 +0000 (09:17 +0100)]
etnaviv: drm: Use NSEC_PER_SEC

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3534>

17 months agofreedreno: android: add adreno-pm4-pack.xml.h generation to android build
Mauro Rossi [Sat, 9 May 2020 11:59:02 +0000 (13:59 +0200)]
freedreno: android: add adreno-pm4-pack.xml.h generation to android build

Fixes the following building errors:

In file included from external/mesa/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c:40:
external/mesa/src/gallium/drivers/freedreno/a6xx/fd6_pack.h:42:10: fatal error: 'adreno-pm4-pack.xml.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

In file included from external/mesa/src/gallium/drivers/freedreno/a6xx/fd6_blend.c:36:
external/mesa/src/gallium/drivers/freedreno/a6xx/fd6_pack.h:42:10: fatal error: 'adreno-pm4-pack.xml.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

In file included from external/mesa/src/gallium/drivers/freedreno/a6xx/fd6_const.c:26:
external/mesa/src/gallium/drivers/freedreno/a6xx/fd6_pack.h:42:10: fatal error: 'adreno-pm4-pack.xml.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Fixes: ee293160 "freedreno/a6xx: add OUT_PKT()"
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4973>

17 months agofreedreno/drm: android: add libfreedreno_registers static dependency
Mauro Rossi [Sat, 9 May 2020 07:44:35 +0000 (09:44 +0200)]
freedreno/drm: android: add libfreedreno_registers static dependency

The dependency is required to get the necessary generated headers

Fixes the following building error:

In file included from external/mesa/src/freedreno/drm/msm_bo.c:27:
In file included from external/mesa/src/freedreno/drm/msm_priv.h:30:
In file included from external/mesa/src/freedreno/drm/freedreno_priv.h:51:
external/mesa/src/freedreno/drm/freedreno_ringbuffer.h:35:10: fatal error: 'adreno_common.xml.h' file not found
#include "adreno_common.xml.h"
         ^~~~~~~~~~~~~~~~~~~~~
1 error generated.

Fixes: 6c688ae8 ("freedreno: Deduplicate ringbuffer macros with computerator/fdperf")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4973>

17 months agolima/ppir: rework select conditions
Erico Nunes [Tue, 14 Apr 2020 00:54:56 +0000 (02:54 +0200)]
lima/ppir: rework select conditions

This is yet another simple optimization that attemts to save the
insertion of an unnecessary mov for a large number of cases.
If the node outputting the condition for select satisfies a few
requirements (which are common in the case of comparison conditions),
it can just be changed to pipeline output and used directly.
In case of difficult corner cases, just fall back to the mov as before.

The sel_cond op is removed as the scheduler can be smart enough to place
nodes that output to ^fmul in the ALU_SCL_MUL slot, and as there can be
alu ops other than just mov.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4632>

17 months agolima/ppir: add fallback mov option for const scheduler
Erico Nunes [Tue, 14 Apr 2020 00:52:48 +0000 (02:52 +0200)]
lima/ppir: add fallback mov option for const scheduler

It turns out that with more aggressive combining, there can be cases
where the available const slots are not enough for one instruction.
In particular, fcsel can take up to two consts, and a previous alu slot,
such as a comparison condition, might require an additional const.
So add a fallback for it like for uniforms.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4632>

17 months agolima/ppir: rework store output
Erico Nunes [Tue, 14 Apr 2020 00:45:38 +0000 (02:45 +0200)]
lima/ppir: rework store output

In many cases, it is possible to avoid creating a mov for the store
output node.
Additionally, nodes other than alu, such as load varying, can be valid
store output nodes too.

This is another small optimization, but helps a vast majority of
programs by 1 instruction.
Shaders with discard easily become complicated to handle properly.
Some example issues: ppir has to rely on instruction ordering; or a
node with ssa output could be required both before a discard_if (as a
condition) and after it (as the instruction with the 'stop' bit set).
So don't try to handle them here.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4632>

17 months agolima/ppir: rework emit nir to ppir
Erico Nunes [Thu, 13 Feb 2020 19:21:00 +0000 (20:21 +0100)]
lima/ppir: rework emit nir to ppir

The previous code assumed that a ppir node would be created for each nir
instr and used that to add it to the list of nodes and verify success.
This didn't make much sense anymore since some emit paths create
multiple nodes anyway, and this didn't allow for an emit call to not
create any new ppir node while still returning success.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4632>

17 months agolima/ppir: remove unused clone functions
Erico Nunes [Mon, 13 Apr 2020 14:04:26 +0000 (16:04 +0200)]
lima/ppir: remove unused clone functions

With the previous refactors moving these lowering steps to a nir pass,
these are no longer needed.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agolima/ppir: duplicate consts in nir
Erico Nunes [Mon, 13 Apr 2020 13:32:01 +0000 (15:32 +0200)]
lima/ppir: duplicate consts in nir

Move the duplicate consts step to a nir pass.
This makes the nir representation closer to what ppir will have in the
result.
Additionally, it handles the case where a const is used multiple times
by a single node (which can happen in instructions like fcsel). The new
implementation will only emit a single load const for that case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agolima/ppir: duplicate intrinsics in nir
Erico Nunes [Mon, 13 Apr 2020 13:30:25 +0000 (15:30 +0200)]
lima/ppir: duplicate intrinsics in nir

Move the duplicate uniform and varying steps to a nir pass, along with
some changes in the duplicating strategy.

Node duplication is now done per user of the varying/uniform. This is
inspired by what the offline shader compiler seems to usually do, and as
usual aims to reduce register pressure and better utilize the ld_uni and
ld_var instruction slots.
It is worth noting that due to a bug/feature, ppir was already
duplicating uniforms per successor in ppir_node_add_src even if the
comment indicated it was meant to be per-block.
Additionally, ppir was duplicating load uniform nodes twice for nodes
that use the same uniform in more than one source, resulting in one
unnecessary (and unpipelineable) load. This new implementation in nir
only creates one load in that case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agolima/ppir: combine varying loads in node_to_instr
Erico Nunes [Mon, 13 Apr 2020 13:26:16 +0000 (15:26 +0200)]
lima/ppir: combine varying loads in node_to_instr

Varying loads with a single successor have a high potential to be
combined with its successor node, like ppir does for uniforms, rather
than being in a separate instruction.
Even if ppir becomes capable of combining instructions in a separate
step, combining varying loads during node_to_instr is trivial enough
that it seems to be worth doing it in this stage, and this benefits
pretty much every program that uses varyings.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agolima/ppir: do not assume single src for pipeline outputs
Erico Nunes [Mon, 13 Apr 2020 13:24:35 +0000 (15:24 +0200)]
lima/ppir: do not assume single src for pipeline outputs

Even if a node has pipeline output and a single successor, it is still
valid for that successor to have multiple references to that pipeline
node. A trivial example is add(u.x,u.y) where u is a uniform.
It is even possible for this to occur with consts as operands of fcsel.
So remove uses of ppir_node_get_src_for_pred as that would assume a
single src in the node that uses the pipeline.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agolima/ppir: fix lod bias register codegen
Erico Nunes [Mon, 13 Apr 2020 13:22:53 +0000 (15:22 +0200)]
lima/ppir: fix lod bias register codegen

The lod bias register is correctly run through the entire compilation
process, but in the end its allocated register value was never being
added to the instruction.
It seems that most programs were lucky enough that lod bias was assigned
register 0.x so that things worked anyway.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agolima/ppir: introduce liveness internal live set
Erico Nunes [Mon, 13 Apr 2020 13:21:52 +0000 (15:21 +0200)]
lima/ppir: introduce liveness internal live set

The current solution for handling registers that live and die within a
single instruction does not handle all cases. In particular, these
intra-instruction use register also conflict with registers that are
part of the live_in set.
Unfortunately, adding them to the live_in set is not an easy solution as
that would cause them to be propagated upwards. So, add a separate set
to handle these registers in the particular instructions, without
propagating them.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4535>

17 months agogenxml: pack: deal with default field not being simple integers
Lionel Landwerlin [Tue, 5 May 2020 09:43:35 +0000 (12:43 +0300)]
genxml: pack: deal with default field not being simple integers

Storing integers into enums doesn't seem to cause issues in C, but
with our builder tests written in C++ this causes warnings/errors.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>

17 months agogenxml: factor out utility functions
Lionel Landwerlin [Thu, 30 Apr 2020 12:43:01 +0000 (15:43 +0300)]
genxml: factor out utility functions

v2: Use the regexp version (Jordan)
    Also fix regexp that missed the ' character replacement (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>

17 months agogenxml: fix invalid end value for video fields
Lionel Landwerlin [Wed, 29 Apr 2020 16:39:06 +0000 (19:39 +0300)]
genxml: fix invalid end value for video fields

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>

17 months agogenxml: run sorting script
Lionel Landwerlin [Thu, 7 May 2020 09:05:23 +0000 (12:05 +0300)]
genxml: run sorting script

Helps running diff/meld between generations :)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>

17 months agointel/dev: Add device info for RKL
Jordan Justen [Tue, 14 Jan 2020 22:36:25 +0000 (14:36 -0800)]
intel/dev: Add device info for RKL

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by : Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4955>

17 months agointel/dev: Split .num_subslices out of GEN12_FEATURES macro
Jordan Justen [Mon, 4 May 2020 20:29:32 +0000 (13:29 -0700)]
intel/dev: Split .num_subslices out of GEN12_FEATURES macro

The .num_subslices field makes it problematic to reuse the
GEN12_FEATURES macro in other macros.

This also fixes the number of L3 banks for tgl gt1, except that this
was already fixed by Jason (dynamically) in:

86f67952d31 ("intel/devinfo: Compute the correct L3$ size for Gen12")

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by : Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4955>

17 months agopanfrost: don't always build bifrost_compiler
Qiang Yu [Fri, 24 Apr 2020 08:20:25 +0000 (16:20 +0800)]
panfrost: don't always build bifrost_compiler

src/panfrost/shared is shared with lima driver, build
bifrost_compiler for lima driver is meaningless and
get link error when only lima driver is enabled.

So only build bifrost_compiler when configued with:
  meson -Dtools=panfrost

Fixes: ec2a59cd7aa4 "panfrost: Move non-Gallium files outside of Gallium"
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4960>

17 months agoradeonsi: remove emacs style config file
Qiang Yu [Fri, 24 Apr 2020 08:27:03 +0000 (16:27 +0800)]
radeonsi: remove emacs style config file

As radeonsi has synced the code style with main mesa,
remove the orginal radeonsi spec emacs config file and
use the top level dir .dir-locals.el

Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4961>

17 months agointel/dump_gpu: Fix name of LD_PRELOAD in env append logic
D Scott Phillips [Fri, 8 May 2020 21:37:06 +0000 (14:37 -0700)]
intel/dump_gpu: Fix name of LD_PRELOAD in env append logic

Checking for the wrong environment variable name to be set causes
us to stomp any pre-existing LD_PRELOAD.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4970>

17 months agoac/surface: fix broken pitch override on gfx8
Marek Olšák [Fri, 8 May 2020 20:12:56 +0000 (16:12 -0400)]
ac/surface: fix broken pitch override on gfx8

Fixes: 441eaef6a9e - amd: unify code for overriding offset and stride for imported buffers
Closes: #2920
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4968>

17 months agofreedreno: Initialize the bo's iova at creation time.
Eric Anholt [Thu, 7 May 2020 23:58:25 +0000 (16:58 -0700)]
freedreno: Initialize the bo's iova at creation time.

Avoids repeated conditionals at reloc time checking if we need to go ask
the kernel.

No statistically significant difference on the drawoverhead case I'm
looking at (n=300).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4957>

17 months agofreedreno: Rename append_bo() in case it doesn't get inlined.
Eric Anholt [Thu, 7 May 2020 23:40:52 +0000 (16:40 -0700)]
freedreno: Rename append_bo() in case it doesn't get inlined.

In a debugoptimized build, it wasn't inlined and so I wasn't noticing
where a bunch of CPU usage was going in the DRM functions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4957>

17 months agofreedreno: Clean up tests around ORing in the reloc flags.
Eric Anholt [Thu, 7 May 2020 23:34:35 +0000 (16:34 -0700)]
freedreno: Clean up tests around ORing in the reloc flags.

gcc was surprisingly not seeing through this to just do an AND and an OR.
Improves drawoverhead's few uniforms / 1 change throughput 1.64141% +/-
0.188152% (n=60).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4957>

17 months agofreedreno: Deduplicate ringbuffer macros with computerator/fdperf
Eric Anholt [Thu, 7 May 2020 22:40:52 +0000 (15:40 -0700)]
freedreno: Deduplicate ringbuffer macros with computerator/fdperf

They're sugar around freedreno_ringbuffer.h, so put them there and reuse them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4957>

17 months agofreedreno,tu: Don't request fragcoord components not being read.
Hyunjun Ko [Thu, 7 May 2020 06:06:59 +0000 (06:06 +0000)]
freedreno,tu: Don't request fragcoord components not being read.

v1. Replace the existed bool type with new bitfield and edit register
files to take a mask instead of duplicating codes to do masking.

v2. Use fragcoord_compmask != 0 instead of fragcoord_compmask > 0 since
it represents a bitfield.

Tested with
  dEQP-VK.glsl.builtin_var.simple.fragcoord_xyz/w
  dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz/w

Closes: #2680
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4723>

17 months agovulkan/object: Always include the type
Jason Ekstrand [Fri, 8 May 2020 01:07:14 +0000 (20:07 -0500)]
vulkan/object: Always include the type

This was causing problems for some of the ANV unit tests when run in
release mode.  Having a public struct whose layout depends on NDEBUG
seems kind-of sketchy anyway.

Fixes: 32f20783a51 "vulkan: Add run-time object type asserts in..."
Closes: #2903
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4959>

17 months agoanv/allocator: Add a start_offset to anv_state_pool
Jason Ekstrand [Mon, 4 May 2020 22:27:22 +0000 (17:27 -0500)]
anv/allocator: Add a start_offset to anv_state_pool

This allows a pool's allocations to start somewhere other than the base
address.  Our first real use of this will be to use a negative offset
for the binding table pool to make it so that the offset is baked into
the pool and the code in anv_batch_chain.c doesn't have to understand
pool offsetting.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4897>

17 months agoutil: Make process_test path compatible with mingw native toolchains
pal1000 [Fri, 24 Apr 2020 14:06:01 +0000 (17:06 +0300)]
util: Make process_test path compatible with mingw native toolchains

v2: Make sure we require winepath when using mingw crosscompilers

v3: Also take into account mingw clang toolchains

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Fixes: f8f14130 ("util/u_process: add util_get_process_exec_path")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2788
CC: "20.1" <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4731>

17 months agoCI: Disable Panfrost T7x0 jobs
Daniel Stone [Fri, 8 May 2020 13:18:52 +0000 (14:18 +0100)]
CI: Disable Panfrost T7x0 jobs

One of the dispatchers in the office (with all the T7x0 boards) has gone
AWOL, and we don't have physical access to restore it. Disable it until
we can get in and fix it.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4965>

17 months agoLinux: Change minimum priority threads from SCHED_IDLE to nice 19 SCHED_BATCH.
Con Kolivas [Wed, 6 May 2020 08:03:37 +0000 (18:03 +1000)]
Linux: Change minimum priority threads from SCHED_IDLE to nice 19 SCHED_BATCH.

SCHED_IDLE on linux can lead to extraordinarily long periods of no scheduling
leading to starvation of minimum priority threads for such an extended period
that it can eventually lead to GUI stalls. Switch to renicing the threads to
the lowest priority and use the SCHED_BATCH scheduling policy which is a hint
to the scheduler that this is latency insensitive thread instead. This change
has been confirmed to address unexpected GUI related stalls in mesa
applications across a range of different linux kernels.

Signed-off-by: Con Kolivas <kernel@kolivas.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4912>

17 months agodocs/features: add zink features
Erik Faye-Lund [Wed, 6 May 2020 09:42:39 +0000 (11:42 +0200)]
docs/features: add zink features

This is base on the exported extension strings, with some known-bad
extensions removed. There might be more that should be removed, as their
support isn't per-spec, but this gives us some more information, at
least.

There's also a few features that seems to be trivial to enable, simply
by flipping a cap. But let's document what is expected to work first.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2075
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4963>

17 months agoanv: fix alignments for uniform buffers
Lionel Landwerlin [Thu, 7 May 2020 09:25:50 +0000 (12:25 +0300)]
anv: fix alignments for uniform buffers

We were not consistent with minimums reported in the physical device
properties.

Fixes a few CTS tests :
   dEQP-VK.memory.requirements.dedicated_allocation.buffer.regular
   dEQP-VK.memory.requirements.extended.buffer.regular
   dEQP-VK.memory.requirements.core.buffer.regular

v2: Use define for the limit

v3: Rename define

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a0de2e0090535b ("anv: increase minUniformBufferOffsetAlignment to 64")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4940>

17 months agoradv: report correct backend IR in hang reports when ACO is used
Samuel Pitoiset [Wed, 6 May 2020 07:38:17 +0000 (09:38 +0200)]
radv: report correct backend IR in hang reports when ACO is used

Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4911>

17 months agoradv: do not print the LLVM version string twice in hang reports
Samuel Pitoiset [Wed, 6 May 2020 07:31:58 +0000 (09:31 +0200)]
radv: do not print the LLVM version string twice in hang reports

It's already part of the device name, and it should now also
correctly report when ACO is used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4911>

17 months agoradv: remove the LLVM version string when ACO is used
Samuel Pitoiset [Wed, 6 May 2020 07:32:27 +0000 (09:32 +0200)]
radv: remove the LLVM version string when ACO is used

Now that ACO supports all shader stages (the only exception is NGG
GS on Navi10 but it fallbacks to legacy GS) it makes sense to remove
the LLVM version string reported as part of the device name.

The LLVM version string was added in the past for some Feral games
to workaround LLVM issues by detecting the version. With ACO, this
is unecessary because the Mesa version is enough to eventually enable
specific shader workarounds.

When the LLVM version string is missing, it is assumed that an old
LLVM is used and workarounds are automatically applied. The only
Vulkan games that might be affected is Shadow of The Tomb Raider
but the impact should be fairly small.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4911>

17 months agoanv: call base finish only if pass given in DestroyRenderPass
Tapani Pälli [Thu, 7 May 2020 06:24:44 +0000 (09:24 +0300)]
anv: call base finish only if pass given in DestroyRenderPass

Fixes: 682c81bdfb7 ("vulkan,anv: Add a base object struct type")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4936>

17 months agost/wgl: allocate and resolve msaa-textures
Erik Faye-Lund [Tue, 5 May 2020 20:01:42 +0000 (22:01 +0200)]
st/wgl: allocate and resolve msaa-textures

LLVMpipe recently got the ability to render to MSAA-surfaces, but in
order for this to work on Windows, we need to allocate a separate MSAA
resource and resolve using a blit before we can display it.

Without this, we end up always displaying the first sample instead of
the resolved result.

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4926>

17 months agost/wgl: pass st_context_iface into stw_st_framebuffer_present_locked
Erik Faye-Lund [Tue, 5 May 2020 19:59:22 +0000 (21:59 +0200)]
st/wgl: pass st_context_iface into stw_st_framebuffer_present_locked

We're going to need this to be able to resolve MSAA buffers.

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4926>

17 months agoradeonsi: Fix omitted flush when moving suballocated texture
Blaž Tomažič [Wed, 6 May 2020 19:34:10 +0000 (21:34 +0200)]
radeonsi: Fix omitted flush when moving suballocated texture

Fixes: 5e805cc74bc52f97de8f6308fc06bc96623e7e09 "radeonsi: flush the context after resource_copy_region for buffer exports"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4925>

17 months agoaco: either copy-propagate or inline create_vector operands
Daniel Schürmann [Wed, 6 May 2020 16:24:38 +0000 (17:24 +0100)]
aco: either copy-propagate or inline create_vector operands

Don't do both at the same time as it breaks DCE

Fixes: 2dc550202e82c5da198ad0a416a5d24dd89addd8 ('aco: copy-propagate p_create_vector copies of vectors')
Fixes: dEQP-VK.glsl.builtin.precision_double.ldexp.compute.scalar on GFX6-GFX7
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4922>

17 months agoac/surface: override all offsets including metadata offsets
Marek Olšák [Mon, 4 May 2020 11:53:38 +0000 (07:53 -0400)]
ac/surface: override all offsets including metadata offsets

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoamd: unify code for overriding offset and stride for imported buffers
Marek Olšák [Mon, 4 May 2020 11:43:44 +0000 (07:43 -0400)]
amd: unify code for overriding offset and stride for imported buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoac/surface,radeonsi: move the set/get_umd_metadata code into ac_surface.c
Marek Olšák [Sat, 2 May 2020 16:23:51 +0000 (12:23 -0400)]
ac/surface,radeonsi: move the set/get_umd_metadata code into ac_surface.c

The indentation is on purpose. The whole file will be reindented to this
code style some other time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoac/surface,radeonsi: move the set/get_bo_metadata code to ac_surface.c
Marek Olšák [Sat, 2 May 2020 14:58:46 +0000 (10:58 -0400)]
ac/surface,radeonsi: move the set/get_bo_metadata code to ac_surface.c

The indentation is on purpose. The whole file will be reindented to this
code style some other time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoamd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile
Marek Olšák [Sat, 2 May 2020 13:19:18 +0000 (09:19 -0400)]
amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoamd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmask
Marek Olšák [Sat, 2 May 2020 13:19:18 +0000 (09:19 -0400)]
amd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmask

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoamd: remove duplicated definitions from amdgpu_drm.h
Marek Olšák [Sat, 2 May 2020 13:10:42 +0000 (09:10 -0400)]
amd: remove duplicated definitions from amdgpu_drm.h

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agoamd: update amdgpu_drm.h
Marek Olšák [Sat, 2 May 2020 13:05:55 +0000 (09:05 -0400)]
amd: update amdgpu_drm.h

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

17 months agollvmpipe: make sample position a global array.
Dave Airlie [Thu, 7 May 2020 00:04:16 +0000 (10:04 +1000)]
llvmpipe: make sample position a global array.

I messed this up and LLVM asserts on it.

Use the gallivm struct wrappers to make it clearer.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2913
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4933>

17 months agonir/algebraic: Optimize some bfe patterns
Ian Romanick [Thu, 5 Mar 2020 21:32:07 +0000 (13:32 -0800)]
nir/algebraic: Optimize some bfe patterns

v2: Use -x instead of 32-x in shift counts.

Tiger Lake
total instructions in shared programs: 17597691 -> 17597405 (<.01%)
instructions in affected programs: 224557 -> 224271 (-0.13%)
helped: 74
HURT: 17
helped stats (abs) min: 1 max: 71 x̄: 14.36 x̃: 7
helped stats (rel) min: 0.08% max: 1.80% x̄: 0.50% x̃: 0.37%
HURT stats (abs)   min: 1 max: 141 x̄: 45.71 x̃: 40
HURT stats (rel)   min: 0.03% max: 3.55% x̄: 1.20% x̃: 1.14%
95% mean confidence interval for instructions value: -10.53 4.24
95% mean confidence interval for instructions %-change: -0.38% 0.01%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 333595656 -> 333180770 (-0.12%)
cycles in affected programs: 70056467 -> 69641581 (-0.59%)
helped: 91
HURT: 4
helped stats (abs) min: 1 max: 25174 x̄: 4571.40 x̃: 400
helped stats (rel) min: <.01% max: 2.23% x̄: 0.40% x̃: 0.21%
HURT stats (abs)   min: 1 max: 370 x̄: 277.75 x̃: 370
HURT stats (rel)   min: 0.01% max: 0.04% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for cycles value: -5981.55 -2752.89
95% mean confidence interval for cycles %-change: -0.48% -0.29%
Cycles are helped.

Ice Lake, Skylake, Broadwell, and Haswell had similar results. (Ice Lake shown)
total instructions in shared programs: 16117204 -> 16116723 (<.01%)
instructions in affected programs: 207109 -> 206628 (-0.23%)
helped: 100
HURT: 0
helped stats (abs) min: 1 max: 9 x̄: 4.81 x̃: 7
helped stats (rel) min: 0.10% max: 1.58% x̄: 0.23% x̃: 0.20%
95% mean confidence interval for instructions value: -5.51 -4.11
95% mean confidence interval for instructions %-change: -0.27% -0.19%
Instructions are helped.

total cycles in shared programs: 330487341 -> 330082421 (-0.12%)
cycles in affected programs: 68037050 -> 67632130 (-0.60%)
helped: 89
HURT: 7
helped stats (abs) min: 2 max: 24610 x̄: 4567.07 x̃: 400
helped stats (rel) min: <.01% max: 1.52% x̄: 0.39% x̃: 0.22%
HURT stats (abs)   min: 1 max: 370 x̄: 221.29 x̃: 170
HURT stats (rel)   min: 0.01% max: 1.66% x̄: 0.58% x̃: 0.04%
95% mean confidence interval for cycles value: -5780.79 -2655.05
95% mean confidence interval for cycles %-change: -0.42% -0.22%
Cycles are helped.

Ivy Bridge
total instructions in shared programs: 11873641 -> 11873137 (<.01%)
instructions in affected programs: 147464 -> 146960 (-0.34%)
helped: 54
HURT: 0
helped stats (abs) min: 9 max: 10 x̄: 9.33 x̃: 9
helped stats (rel) min: 0.29% max: 0.41% x̄: 0.34% x̃: 0.34%
95% mean confidence interval for instructions value: -9.46 -9.20
95% mean confidence interval for instructions %-change: -0.35% -0.33%
Instructions are helped.

total cycles in shared programs: 175769085 -> 175549519 (-0.12%)
cycles in affected programs: 60770592 -> 60551026 (-0.36%)
helped: 54
HURT: 0
helped stats (abs) min: 252 max: 13434 x̄: 4066.04 x̃: 1290
helped stats (rel) min: 0.02% max: 0.74% x̄: 0.34% x̃: 0.26%
95% mean confidence interval for cycles value: -5323.59 -2808.48
95% mean confidence interval for cycles %-change: -0.41% -0.27%
Cycles are helped.

No changes on any earlier Intel platforms.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>

17 months agonir/algebraic: Split ibfe and ubfe with two constant sources
Ian Romanick [Fri, 6 Mar 2020 21:22:45 +0000 (13:22 -0800)]
nir/algebraic: Split ibfe and ubfe with two constant sources

I also tried splitting ubfe instructions with one or zero constants,
and zero shaders in shader-db were affected.

The "lost" shader is a compute shader that was promoted from SIMD8 to
SIMD16, so is also counted as the gained shader.

v2: Further restrict bfe splitting.  bfe with multiple constants is
better on at least some Radeon GPUs.  Use -x instead of 32-x in shift
counts.

v3: Fix the outer shift count for ibfe lowering.  Add c=0 optimizations
to prevent bad lowering.  Both suggested by Rhys.  Add shift by -32
optimizations.

Tiger Lake
total instructions in shared programs: 17608764 -> 17596316 (-0.07%)
instructions in affected programs: 303765 -> 291317 (-4.10%)
helped: 113
HURT: 46
helped stats (abs) min: 1 max: 458 x̄: 120.67 x̃: 21
helped stats (rel) min: 0.09% max: 11.23% x̄: 3.47% x̃: 1.39%
HURT stats (abs)   min: 1 max: 201 x̄: 25.83 x̃: 6
HURT stats (rel)   min: 0.23% max: 5.18% x̄: 1.53% x̃: 1.11%
95% mean confidence interval for instructions value: -101.13 -55.45
95% mean confidence interval for instructions %-change: -2.61% -1.44%
Instructions are helped.

total cycles in shared programs: 338390770 -> 333530868 (-1.44%)
cycles in affected programs: 79438330 -> 74578428 (-6.12%)
helped: 112
HURT: 64
helped stats (abs) min: 2 max: 268955 x̄: 44261.93 x̃: 1452
helped stats (rel) min: <.01% max: 29.51% x̄: 4.72% x̃: 2.23%
HURT stats (abs)   min: 2 max: 17618 x̄: 1522.41 x̃: 84
HURT stats (rel)   min: <.01% max: 7.34% x̄: 1.35% x̃: 0.34%
95% mean confidence interval for cycles value: -37232.47 -17993.69
95% mean confidence interval for cycles %-change: -3.37% -1.65%
Cycles are helped.

total spills in shared programs: 8944 -> 8138 (-9.01%)
spills in affected programs: 3240 -> 2434 (-24.88%)
helped: 67
HURT: 0

total fills in shared programs: 9373 -> 7842 (-16.33%)
fills in affected programs: 4736 -> 3205 (-32.33%)
helped: 67
HURT: 0

LOST:   1
GAINED: 2

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 16123288 -> 16116876 (-0.04%)
instructions in affected programs: 241155 -> 234743 (-2.66%)
helped: 126
HURT: 2
helped stats (abs) min: 1 max: 209 x̄: 50.90 x̃: 7
helped stats (rel) min: 0.07% max: 5.94% x̄: 1.76% x̃: 0.65%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.05% max: 0.24% x̄: 0.15% x̃: 0.15%
95% mean confidence interval for instructions value: -61.29 -38.89
95% mean confidence interval for instructions %-change: -2.05% -1.42%
Instructions are helped.

total cycles in shared programs: 335419163 -> 330438819 (-1.48%)
cycles in affected programs: 77515502 -> 72535158 (-6.42%)
helped: 139
HURT: 37
helped stats (abs) min: 2 max: 269140 x̄: 36374.19 x̃: 597
helped stats (rel) min: <.01% max: 28.60% x̄: 3.67% x̃: 1.31%
HURT stats (abs)   min: 4 max: 17618 x̄: 2045.08 x̃: 174
HURT stats (rel)   min: 0.02% max: 8.32% x̄: 2.61% x̃: 0.62%
95% mean confidence interval for cycles value: -37799.30 -18795.51
95% mean confidence interval for cycles %-change: -3.13% -1.57%
Cycles are helped.

total spills in shared programs: 8065 -> 7306 (-9.41%)
spills in affected programs: 3153 -> 2394 (-24.07%)
helped: 67
HURT: 0

total fills in shared programs: 8710 -> 7412 (-14.90%)
fills in affected programs: 4466 -> 3168 (-29.06%)
helped: 67
HURT: 0

LOST:   1
GAINED: 1

Broadwell
total instructions in shared programs: 14970538 -> 14965967 (-0.03%)
instructions in affected programs: 227040 -> 222469 (-2.01%)
helped: 126
HURT: 2
helped stats (abs) min: 1 max: 136 x̄: 36.29 x̃: 8
helped stats (rel) min: 0.07% max: 6.02% x̄: 1.47% x̃: 0.89%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.05% max: 0.24% x̄: 0.14% x̃: 0.14%
95% mean confidence interval for instructions value: -43.05 -28.37
95% mean confidence interval for instructions %-change: -1.69% -1.19%
Instructions are helped.

total cycles in shared programs: 336237662 -> 333035960 (-0.95%)
cycles in affected programs: 72066394 -> 68864692 (-4.44%)
helped: 134
HURT: 42
helped stats (abs) min: 4 max: 122640 x̄: 24344.54 x̃: 1833
helped stats (rel) min: <.01% max: 26.93% x̄: 4.02% x̃: 2.38%
HURT stats (abs)   min: 1 max: 17205 x̄: 1439.69 x̃: 92
HURT stats (rel)   min: <.01% max: 7.12% x̄: 1.34% x̃: 0.62%
95% mean confidence interval for cycles value: -23753.58 -12629.40
95% mean confidence interval for cycles %-change: -3.50% -1.98%
Cycles are helped.

total spills in shared programs: 21122 -> 20204 (-4.35%)
spills in affected programs: 3644 -> 2726 (-25.19%)
helped: 67
HURT: 0

total fills in shared programs: 24879 -> 23460 (-5.70%)
fills in affected programs: 4883 -> 3464 (-29.06%)
helped: 67
HURT: 0

Haswell
total instructions in shared programs: 13148269 -> 13145444 (-0.02%)
instructions in affected programs: 137046 -> 134221 (-2.06%)
helped: 97
HURT: 3
helped stats (abs) min: 1 max: 137 x̄: 30.58 x̃: 3
helped stats (rel) min: 0.14% max: 4.38% x̄: 1.38% x̃: 0.44%
HURT stats (abs)   min: 1 max: 70 x̄: 47.00 x̃: 70
HURT stats (rel)   min: 0.05% max: 5.82% x̄: 3.90% x̃: 5.82%
95% mean confidence interval for instructions value: -37.15 -19.35
95% mean confidence interval for instructions %-change: -1.56% -0.89%
Instructions are helped.

total cycles in shared programs: 321221834 -> 318333159 (-0.90%)
cycles in affected programs: 54932349 -> 52043674 (-5.26%)
helped: 95
HURT: 53
helped stats (abs) min: 4 max: 123390 x̄: 30648.39 x̃: 702
helped stats (rel) min: <.01% max: 28.87% x̄: 4.27% x̃: 2.87%
HURT stats (abs)   min: 4 max: 2357 x̄: 432.49 x̃: 113
HURT stats (rel)   min: <.01% max: 3.44% x̄: 1.03% x̃: 0.54%
95% mean confidence interval for cycles value: -26154.16 -12881.99
95% mean confidence interval for cycles %-change: -3.20% -1.55%
Cycles are helped.

total spills in shared programs: 19878 -> 19293 (-2.94%)
spills in affected programs: 3020 -> 2435 (-19.37%)
helped: 41
HURT: 2

total fills in shared programs: 20918 -> 19875 (-4.99%)
fills in affected programs: 3968 -> 2925 (-26.29%)
helped: 41
HURT: 2

LOST:   0
GAINED: 1

Ivy Bridge
total instructions in shared programs: 11875585 -> 11873641 (-0.02%)
instructions in affected programs: 78065 -> 76121 (-2.49%)
helped: 27
HURT: 0
helped stats (abs) min: 8 max: 134 x̄: 72.00 x̃: 72
helped stats (rel) min: 0.36% max: 4.23% x̄: 2.42% x̃: 2.42%
95% mean confidence interval for instructions value: -83.68 -60.32
95% mean confidence interval for instructions %-change: -2.78% -2.07%
Instructions are helped.

total cycles in shared programs: 178232734 -> 175769085 (-1.38%)
cycles in affected programs: 50018707 -> 47555058 (-4.93%)
helped: 27
HURT: 0
helped stats (abs) min: 82035 max: 99953 x̄: 91246.26 x̃: 92278
helped stats (rel) min: 4.40% max: 5.69% x̄: 4.93% x̃: 4.95%
95% mean confidence interval for cycles value: -93674.20 -88818.32
95% mean confidence interval for cycles %-change: -5.09% -4.78%
Cycles are helped.

total spills in shared programs: 4182 -> 3739 (-10.59%)
spills in affected programs: 1089 -> 646 (-40.68%)
helped: 27
HURT: 0

total fills in shared programs: 5216 -> 4345 (-16.70%)
fills in affected programs: 1874 -> 1003 (-46.48%)
helped: 27
HURT: 0

No changes on any earlier Intel platforms.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>

17 months agonir/algebraic: Recognize open-coded byte or word extract from bfe
Ian Romanick [Fri, 6 Mar 2020 16:00:42 +0000 (08:00 -0800)]
nir/algebraic: Recognize open-coded byte or word extract from bfe

v2: Move word-extract patterns up near the byte-extract patterns.
Suggested by Rhys.

Tiger Lake
total instructions in shared programs: 21369236 -> 21368712 (<.01%)
instructions in affected programs: 913104 -> 912580 (-0.06%)
helped: 209
HURT: 165
helped stats (abs) min: 1 max: 30 x̄: 5.35 x̃: 3
helped stats (rel) min: 0.03% max: 6.92% x̄: 0.28% x̃: 0.12%
HURT stats (abs)   min: 1 max: 18 x̄: 3.61 x̃: 3
HURT stats (rel)   min: 0.04% max: 0.87% x̄: 0.16% x̃: 0.12%
95% mean confidence interval for instructions value: -2.04 -0.76
95% mean confidence interval for instructions %-change: -0.14% -0.04%
Instructions are helped.

total cycles in shared programs: 490161481 -> 490175959 (<.01%)
cycles in affected programs: 72557244 -> 72571722 (0.02%)
helped: 193
HURT: 189
helped stats (abs) min: 1 max: 14240 x̄: 509.16 x̃: 71
helped stats (rel) min: <.01% max: 13.71% x̄: 0.44% x̃: 0.05%
HURT stats (abs)   min: 2 max: 4210 x̄: 596.53 x̃: 173
HURT stats (rel)   min: <.01% max: 5.59% x̄: 0.54% x̃: 0.14%
95% mean confidence interval for cycles value: -96.33 172.13
95% mean confidence interval for cycles %-change: -0.07% 0.16%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 10780 -> 10782 (0.02%)
spills in affected programs: 18 -> 20 (11.11%)
helped: 0
HURT: 1

total fills in shared programs: 10396 -> 10370 (-0.25%)
fills in affected programs: 2292 -> 2266 (-1.13%)
helped: 27
HURT: 1

Ice Lake
total instructions in shared programs: 19556356 -> 19555446 (<.01%)
instructions in affected programs: 833336 -> 832426 (-0.11%)
helped: 400
HURT: 0
helped stats (abs) min: 1 max: 20 x̄: 2.27 x̃: 2
helped stats (rel) min: 0.07% max: 4.42% x̄: 0.14% x̃: 0.10%
95% mean confidence interval for instructions value: -2.42 -2.13
95% mean confidence interval for instructions %-change: -0.18% -0.11%
Instructions are helped.

total cycles in shared programs: 488026481 -> 488008714 (<.01%)
cycles in affected programs: 81581708 -> 81563941 (-0.02%)
helped: 193
HURT: 206
helped stats (abs) min: 1 max: 3615 x̄: 576.35 x̃: 131
helped stats (rel) min: <.01% max: 4.50% x̄: 0.49% x̃: 0.22%
HURT stats (abs)   min: 1 max: 2244 x̄: 453.73 x̃: 170
HURT stats (rel)   min: <.01% max: 5.71% x̄: 0.36% x̃: 0.14%
95% mean confidence interval for cycles value: -127.23 38.17
95% mean confidence interval for cycles %-change: -0.12% 0.03%
Inconclusive result (value mean confidence interval includes 0).

total fills in shared programs: 9935 -> 9908 (-0.27%)
fills in affected programs: 2208 -> 2181 (-1.22%)
helped: 27
HURT: 0

Skylake
total instructions in shared programs: 17766078 -> 17765186 (<.01%)
instructions in affected programs: 822017 -> 821125 (-0.11%)
helped: 399
HURT: 1
helped stats (abs) min: 1 max: 20 x̄: 2.27 x̃: 2
helped stats (rel) min: 0.07% max: 4.46% x̄: 0.15% x̃: 0.10%
HURT stats (abs)   min: 12 max: 12 x̄: 12.00 x̃: 12
HURT stats (rel)   min: 0.50% max: 0.50% x̄: 0.50% x̃: 0.50%
95% mean confidence interval for instructions value: -2.39 -2.07
95% mean confidence interval for instructions %-change: -0.18% -0.11%
Instructions are helped.

total cycles in shared programs: 470905548 -> 470907497 (<.01%)
cycles in affected programs: 78598491 -> 78600440 (<.01%)
helped: 202
HURT: 192
helped stats (abs) min: 1 max: 3690 x̄: 228.98 x̃: 60
helped stats (rel) min: <.01% max: 4.51% x̄: 0.24% x̃: 0.03%
HURT stats (abs)   min: 1 max: 2260 x̄: 251.05 x̃: 77
HURT stats (rel)   min: <.01% max: 5.31% x̄: 0.24% x̃: 0.06%
95% mean confidence interval for cycles value: -45.01 54.90
95% mean confidence interval for cycles %-change: -0.07% 0.05%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 9941 -> 9943 (0.02%)
spills in affected programs: 26 -> 28 (7.69%)
helped: 0
HURT: 1

total fills in shared programs: 10293 -> 10268 (-0.24%)
fills in affected programs: 2391 -> 2366 (-1.05%)
helped: 27
HURT: 1

Broadwell
total instructions in shared programs: 17463211 -> 17462366 (<.01%)
instructions in affected programs: 861444 -> 860599 (-0.10%)
helped: 399
HURT: 1
helped stats (abs) min: 1 max: 20 x̄: 2.14 x̃: 2
helped stats (rel) min: 0.03% max: 4.46% x̄: 0.14% x̃: 0.09%
HURT stats (abs)   min: 7 max: 7 x̄: 7.00 x̃: 7
HURT stats (rel)   min: 0.33% max: 0.33% x̄: 0.33% x̃: 0.33%
95% mean confidence interval for instructions value: -2.26 -1.97
95% mean confidence interval for instructions %-change: -0.17% -0.10%
Instructions are helped.

total cycles in shared programs: 507048912 -> 506898243 (-0.03%)
cycles in affected programs: 79806433 -> 79655764 (-0.19%)
helped: 248
HURT: 136
helped stats (abs) min: 1 max: 8450 x̄: 1124.18 x̃: 64
helped stats (rel) min: <.01% max: 5.91% x̄: 0.83% x̃: 0.05%
HURT stats (abs)   min: 2 max: 7632 x̄: 942.12 x̃: 103
HURT stats (rel)   min: <.01% max: 5.62% x̄: 0.71% x̃: 0.08%
95% mean confidence interval for cycles value: -647.01 -137.73
95% mean confidence interval for cycles %-change: -0.47% -0.10%
Cycles are helped.

total spills in shared programs: 22996 -> 22998 (<.01%)
spills in affected programs: 31 -> 33 (6.45%)
helped: 0
HURT: 1

total fills in shared programs: 25951 -> 25923 (-0.11%)
fills in affected programs: 2444 -> 2416 (-1.15%)
helped: 29
HURT: 1

Haswell
total instructions in shared programs: 15841325 -> 15840554 (<.01%)
instructions in affected programs: 869679 -> 868908 (-0.09%)
helped: 394
HURT: 6
helped stats (abs) min: 1 max: 20 x̄: 2.15 x̃: 2
helped stats (rel) min: 0.06% max: 4.46% x̄: 0.14% x̃: 0.09%
HURT stats (abs)   min: 7 max: 18 x̄: 12.83 x̃: 13
HURT stats (rel)   min: 0.32% max: 0.82% x̄: 0.59% x̃: 0.61%
95% mean confidence interval for instructions value: -2.16 -1.69
95% mean confidence interval for instructions %-change: -0.16% -0.09%
Instructions are helped.

total cycles in shared programs: 520417167 -> 520279766 (-0.03%)
cycles in affected programs: 80949963 -> 80812562 (-0.17%)
helped: 246
HURT: 139
helped stats (abs) min: 1 max: 8152 x̄: 790.08 x̃: 129
helped stats (rel) min: <.01% max: 11.46% x̄: 0.70% x̃: 0.09%
HURT stats (abs)   min: 1 max: 7085 x̄: 409.78 x̃: 80
HURT stats (rel)   min: <.01% max: 5.25% x̄: 0.31% x̃: 0.06%
95% mean confidence interval for cycles value: -526.34 -187.43
95% mean confidence interval for cycles %-change: -0.49% -0.18%
Cycles are helped.

total spills in shared programs: 21714 -> 21729 (0.07%)
spills in affected programs: 174 -> 189 (8.62%)
helped: 0
HURT: 6

total fills in shared programs: 22136 -> 22132 (-0.02%)
fills in affected programs: 2848 -> 2844 (-0.14%)
helped: 31
HURT: 6

Ivy Bridge
total instructions in shared programs: 15177059 -> 15177003 (<.01%)
instructions in affected programs: 79370 -> 79314 (-0.07%)
helped: 29
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.93 x̃: 2
helped stats (rel) min: 0.06% max: 0.16% x̄: 0.08% x̃: 0.07%
95% mean confidence interval for instructions value: -2.03 -1.83
95% mean confidence interval for instructions %-change: -0.09% -0.07%
Instructions are helped.

total cycles in shared programs: 420424359 -> 420417254 (<.01%)
cycles in affected programs: 29562648 -> 29555543 (-0.02%)
helped: 23
HURT: 6
helped stats (abs) min: 2 max: 2741 x̄: 432.57 x̃: 142
helped stats (rel) min: <.01% max: 0.26% x̄: 0.04% x̃: 0.02%
HURT stats (abs)   min: 4 max: 1184 x̄: 474.00 x̃: 226
HURT stats (rel)   min: <.01% max: 0.11% x̄: 0.05% x̃: 0.05%
95% mean confidence interval for cycles value: -553.48 63.48
95% mean confidence interval for cycles %-change: -0.05% <.01%
Inconclusive result (value mean confidence interval includes 0).

total fills in shared programs: 6420 -> 6393 (-0.42%)
fills in affected programs: 1901 -> 1874 (-1.42%)
helped: 27
HURT: 0

No changes on any earlier Intel platforms.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>

17 months agogallium/swr: Fix crashes in sampling code
Jan Zielinski [Thu, 7 May 2020 14:49:15 +0000 (16:49 +0200)]
gallium/swr: Fix crashes in sampling code

Add missing functions used by the new
sampling code in llvmpipe (num_samples and
sample_stride)

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4947>

17 months agopanfrost: Handle MALI_RGB8_UNORM in panfrost_format_to_bifrost_blend
Tomeu Vizoso [Thu, 7 May 2020 12:56:53 +0000 (14:56 +0200)]
panfrost: Handle MALI_RGB8_UNORM in panfrost_format_to_bifrost_blend

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>

17 months agopanfrost: Don't trample on top of Bifrost-specific unions
Tomeu Vizoso [Thu, 7 May 2020 12:56:17 +0000 (14:56 +0200)]
panfrost: Don't trample on top of Bifrost-specific unions

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>

17 months agopan/decode: Fix flags_hi printing
Alyssa Rosenzweig [Mon, 4 May 2020 16:48:34 +0000 (12:48 -0400)]
pan/decode: Fix flags_hi printing

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>

17 months agopanfrost: Add checksum BOs to batch
Tomeu Vizoso [Mon, 4 May 2020 07:01:19 +0000 (09:01 +0200)]
panfrost: Add checksum BOs to batch

So they don't get released before the last frame finishes rendering.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>

17 months agoanv: don't expose VK_INTEL_performance_query without kernel support
Lionel Landwerlin [Thu, 7 May 2020 08:36:36 +0000 (11:36 +0300)]
anv: don't expose VK_INTEL_performance_query without kernel support

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2b5f30b1d91b ("anv: implement VK_INTEL_performance_query")
Acked-by: Timothy Strelchun <timothy.strelchun@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4937>

17 months agotu: Support pipelines without a fragment shader
Connor Abbott [Wed, 6 May 2020 22:07:48 +0000 (00:07 +0200)]
tu: Support pipelines without a fragment shader

Apparently this is allowed, and the CTS started doing this more often
recently which resulted in frequent hangs running the entire CTS. I
copied the code to create an empty FS from radv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4928>

17 months agoutil/os_memory: never use os_memory_debug.h
Erik Faye-Lund [Wed, 6 May 2020 13:33:37 +0000 (15:33 +0200)]
util/os_memory: never use os_memory_debug.h

This is currently broken hard, because this code is being used in more
places that it used to be, and fixing that is prohibitively hard right
now.

This is far from ideal, as it leaves the same inconsistency in the
EMBEDDED_DEVICE code-path. But that only used by VMWare, so it's
probably better if they fix it, as they know their requirements better
than we do.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2911
Fixes: 76f79db3f5d ("util: stop including files from mesa/main")
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4919>

17 months agov3d: Include supported DXT formats to enable s3tc/dxt extensions
Jose Maria Casanova Crespo [Thu, 7 May 2020 01:50:16 +0000 (03:50 +0200)]
v3d: Include supported DXT formats to enable s3tc/dxt extensions

DXT1_RGBA and sRGB variants of DXT[135] formats are enabled as
valid format on V3D.

Once all S3TC formats supported by V3C are enabled the following
extensions become exposed by gallium.

    * GL_ANGLE_texture_compression_dxt3
    * GL_ANGLE_texture_compression_dxt5,
    * GL_EXT_texture_compression_dxt1
    * GL_EXT_texture_compression_s3tc
    * GL_S3_s3tc
    * GL_EXT_texture_compression_s3tc_srgb

This enables 206 passing piglit test related to gl_compressed.*s3tc_dxt

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>

17 months agov3d: Fix swizzle in DXT3 and DXT5 formats
Jose Maria Casanova Crespo [Thu, 7 May 2020 01:37:22 +0000 (03:37 +0200)]
v3d: Fix swizzle in DXT3 and DXT5 formats

Swizzles were ignoring the W component of the format DXT3_RGBA and
DXT5_RGBA.

This fixes 15 piglit tests:

spec/!opengl 1.1/copyteximage 2d
spec/!opengl 1.2/copyteximage 3d
spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba
spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba npot
spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_rgba, swizzled, border color only
spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_rgba, border color only
spec/arb_texture_cube_map/copyteximage cube
spec/arb_texture_cube_map/copyteximage cube samples=2
spec/arb_texture_cube_map/copyteximage cube samples=4
spec/arb_texture_rectangle/copyteximage rect
spec/arb_texture_rectangle/copyteximage rect samples=2
spec/arb_texture_rectangle/copyteximage rect samples=4
spec/ext_texture_array/copyteximage 2d_array
spec/ext_texture_array/copyteximage 2d_array samples=2
spec/ext_texture_array/copyteximage 2d_array samples=4

Fixes: 469bbd8387d1 "broadcom/vc5: Move the formats table to per-V3D-version compile."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>

17 months agodocs/envvars: update RADV_FORCE_FAMILY
Rhys Perry [Tue, 5 May 2020 16:39:59 +0000 (17:39 +0100)]
docs/envvars: update RADV_FORCE_FAMILY

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>

17 months agodocs/envvars: document ACO_DEBUG
Rhys Perry [Tue, 5 May 2020 16:31:26 +0000 (17:31 +0100)]
docs/envvars: document ACO_DEBUG

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>