mesa.git
4 years agobroadcom/vc5: Drop signal bit #defines.
Eric Anholt [Thu, 4 Jan 2018 19:21:33 +0000 (11:21 -0800)]
broadcom/vc5: Drop signal bit #defines.

Signals are more complicated than that, and tables ended up being better.

4 years agobroadcom/vc5: Add support for V3Dv4 signal bits.
Eric Anholt [Thu, 4 Jan 2018 05:42:33 +0000 (21:42 -0800)]
broadcom/vc5: Add support for V3Dv4 signal bits.

The WRTMUC replaces the implicit uniform loads in the first two texture
instructions.  LDVPM disappears in favor of an ALU op.  LDVARY, LDTMU,
LDTLB, and LDUNIF*RF now write to arbitrary registers, which required
passing the devinfo through to a few more functions.

4 years agobroadcom/vc5: Fix pack/unpack of vfmul input unpack flags.
Eric Anholt [Thu, 4 Jan 2018 18:34:36 +0000 (10:34 -0800)]
broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.

4 years agobroadcom/vc5: Port the RCL setup to V3D4.1.
Eric Anholt [Thu, 28 Dec 2017 22:00:15 +0000 (14:00 -0800)]
broadcom/vc5: Port the RCL setup to V3D4.1.

The TLB load/store path is rebuilt in this version.  There is no longer a
single-byte resolved store or the 3-byte extended store.  Instead, you get
to always use general loads/stores (which, honestly, was tempting even in
previous versions).

4 years agobroadcom/vc5: Fix per-tile extra clear packet.
Eric Anholt [Tue, 9 Jan 2018 22:59:19 +0000 (14:59 -0800)]
broadcom/vc5: Fix per-tile extra clear packet.

I accidentally emitted this into the RCL instead of the per-tile generic
list, so we wouldn't get tiles after the first cleared.

4 years agobroadcom/vc5: Move the TLB loads and stores to helper functions.
Eric Anholt [Wed, 3 Jan 2018 19:08:53 +0000 (11:08 -0800)]
broadcom/vc5: Move the TLB loads and stores to helper functions.

This is going to get more complicated with V3D 4.1 support, which redoes
all the TLB packets.

4 years agobroadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.
Eric Anholt [Wed, 3 Jan 2018 20:42:13 +0000 (12:42 -0800)]
broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.

To conditionally compile cl_emit() macros per V3D version, we need it to
expand to whatever V3D we're building for.  This required emitting #define
V3D_VERSION 33 in all our currently 3.3-only code.

4 years agobroadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.
Eric Anholt [Tue, 10 Oct 2017 20:25:45 +0000 (13:25 -0700)]
broadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.

This will be used by vc5 for prefixing functions and including the pack
header in v3d-version-dependent code, following the model of anv.

4 years agobroadcom/cle: Fix error path of missing a "type" in the XML.
Eric Anholt [Thu, 28 Dec 2017 21:51:36 +0000 (13:51 -0800)]
broadcom/cle: Fix error path of missing a "type" in the XML.

We try to emit a #error and continue so that you can debug the missing
type at C compile time, but were missing a couple of definitions in that
path (sigh, python).

4 years agobroadcom/vc5: Add XML for V3D v4.1 (BCM7278)
Eric Anholt [Thu, 28 Dec 2017 00:18:02 +0000 (16:18 -0800)]
broadcom/vc5: Add XML for V3D v4.1 (BCM7278)

4 years agoac: add 'const' qualifiers to the shader info pass
Samuel Pitoiset [Thu, 11 Jan 2018 21:07:25 +0000 (22:07 +0100)]
ac: add 'const' qualifiers to the shader info pass

For clarification purposes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoac: remove unused ac_nir_compiler_options from gather_info_input_decl()
Samuel Pitoiset [Thu, 11 Jan 2018 21:07:24 +0000 (22:07 +0100)]
ac: remove unused ac_nir_compiler_options from gather_info_input_decl()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agonir: add a 'const' qualifier to nir_ssa_def_components_read()
Samuel Pitoiset [Thu, 11 Jan 2018 21:07:23 +0000 (22:07 +0100)]
nir: add a 'const' qualifier to nir_ssa_def_components_read()

To avoid compilation warnings and because this helper
shouldn't update anything.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoloader/dri3: Avoid freeing renderbuffers in use
Thomas Hellstrom [Thu, 11 Jan 2018 09:19:23 +0000 (10:19 +0100)]
loader/dri3: Avoid freeing renderbuffers in use

Upon reception of an event that lowered the number of active back buffers,
the code would immediately try to free all back buffers with an id equal to or
higher than the new number of active back buffers.

However, that could lead to an active or to-be-active back buffer being freed,
since the old number of back buffers was used when obtaining an idle back
buffer for use.

This lead to crashes when lowering the number of active back buffers by
transitioning from page-flipping to non-page-flipping presents.

Fix this by computing the number of active back buffers only when trying to
obtain a new back buffer.

Fixes: 15e208c4cc ("loader/dri3: Don't accidently free buffer holding new back content")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Andriy.Khulap <andriy.khulap@globallogic.com>
Tested-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
4 years agoanv: VkDescriptorSetLayoutBinding can have descriptorCount == 0
Samuel Iglesias Gonsálvez [Thu, 11 Jan 2018 10:15:30 +0000 (11:15 +0100)]
anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0

From Vulkan spec:

"descriptorCount is the number of descriptors contained in the binding,
accessed in a shader as an array. If descriptorCount is zero this
binding entry is reserved and the resource must not be accessed from
any stage via this binding within any pipeline using the set layout."

Fixes:

dEQP-VK.binding_model.descriptor_update.empty_descriptor.uniform_buffer

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
4 years agomesa: require at least 14 UBOs for GL 4.3
Roland Scheidegger [Thu, 11 Jan 2018 01:10:25 +0000 (02:10 +0100)]
mesa: require at least 14 UBOs for GL 4.3

ARB_ubo requires 12 UBOs (per stage) at least, but this limit has been
raised by GL 4.3 to 14, so don't advertize GL 4.3 without it (only checking
the vertex stage since all drivers probably have the same limit anyway for
other stages). (piglit has minmax tests for that kind of thing, but they go
only up to 3.3, so this won't really be noticed.)
I think this currently should not affect any driver - r600 until very
recently only supported 12 but now advertizes 14 too.

Reviewed-by: Brian Paul <brianp@vmware.com>
4 years agoutil: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h
Roland Scheidegger [Thu, 11 Jan 2018 00:49:00 +0000 (01:49 +0100)]
util: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h

We've seen some problems internally due to macro redefinition.
Fix this by adding HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h,
and defining it for msvc.
And avoid redefinition just in case.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
4 years agoradv: don't emit unneeded vertex state.
Dave Airlie [Wed, 10 Jan 2018 22:02:52 +0000 (08:02 +1000)]
radv: don't emit unneeded vertex state.

If the number of instances hasn't changed and we've already
emitted it, don't emit it again.

If the vertex shader is the same and the first_instance, vertex_offset
haven't changed don't emit them again.

This increases the fps in GL_vs_VK -t 1 -m -api vk from around 40
to around 60 here, it may not impact anything else.

Dieter also reported smoketest going from 1060->1200 fps.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agoradv: trim buffer load result (fixes dota2)
Dave Airlie [Thu, 11 Jan 2018 02:10:23 +0000 (02:10 +0000)]
radv: trim buffer load result (fixes dota2)

Running dota2 since the below commit crashes with an llvm assert.

Trim the vector like the other user. This possible could also be
avoided by not padding inside the load vec3->vec4.

Fixes: 41c36c4549 (amd/common: use ac_build_buffer_load() for emitting UBO loads)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agomeson: add variable for including include/GL/internal
Dylan Baker [Wed, 3 Jan 2018 20:37:34 +0000 (12:37 -0800)]
meson: add variable for including include/GL/internal

Signed-off-by: <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agomeson: define inc_gbm as empty if not otherwise assigned
Dylan Baker [Wed, 3 Jan 2018 20:33:55 +0000 (12:33 -0800)]
meson: define inc_gbm as empty if not otherwise assigned

Otherwise this could be undefined in the egl directory.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agomeson: move libsensors dependency to libgallium
Dylan Baker [Tue, 12 Dec 2017 20:25:34 +0000 (12:25 -0800)]
meson: move libsensors dependency to libgallium

This simplifies the build by removing the need to link targets against
libsensors.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agomeson: Use dependencies for nir
Dylan Baker [Tue, 12 Dec 2017 20:22:56 +0000 (12:22 -0800)]
meson: Use dependencies for nir

This creates two new internal dependencies, idep_nir_headers and
idep_nir. The former encapsulates the generation of nir_opcodes.h and
nir_builder_opcodes.h and adding src/compiler/nir as an include path.
This ensures that any target that needs nir headers will have the
includes and that the generated headers will be generated before the
target is build. The second, idep_nir, includes the first and
additionally links to libnir.

This is intended to make it easier to avoid race conditions in the build
when using nir, since the number of consumers for libnir and it's
headers are quite high.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
4 years agomeson: don't use intermediate variables that are immediately discarded
Dylan Baker [Tue, 12 Dec 2017 00:16:56 +0000 (16:16 -0800)]
meson: don't use intermediate variables that are immediately discarded

For things like:
loop
    x = func()
    list += x
end

just do:
loop
    list += func()
end

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
4 years agomeson: Use consistent style for tests
Dylan Baker [Tue, 12 Dec 2017 00:13:31 +0000 (16:13 -0800)]
meson: Use consistent style for tests

Don't use intermediate variables, use consistent whitespace.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
4 years agomeson: Use include variables
Dylan Baker [Mon, 11 Dec 2017 23:58:00 +0000 (15:58 -0800)]
meson: Use include variables

These were added after adderlib was mesonified, but it still good to use
them instead of open coding them.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
4 years agomeson: Use consistent style
Dylan Baker [Mon, 11 Dec 2017 23:56:08 +0000 (15:56 -0800)]
meson: Use consistent style

Currently the meosn build has a mix of two styles:
arg : [foo, ...
       bar],

and
arg : [
  foo, ...,
  bar,
]

For consistency let's pick one. I've picked the later style, which I
think is more readable, and is more common in the mesa code base.

v2: - fix commit message

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
4 years agoi965: Use UD types for gl_SampleID setup
Jason Ekstrand [Sat, 6 Jan 2018 02:50:14 +0000 (18:50 -0800)]
i965: Use UD types for gl_SampleID setup

We already had to switch all of the W types to UW to prevent issues
with vector immediates on gen10.  We may as well use unsigned types
everywhere.

Reviewed-by: Matt Turner <mattst88@gmail.com>
4 years agoi965/fs: Use UW types when using V immediates
Jason Ekstrand [Sat, 6 Jan 2018 02:26:58 +0000 (18:26 -0800)]
i965/fs: Use UW types when using V immediates

Gen 10 has a strange hardware bug involving V immediates with W types.
It appears that a mov(8) g2<1>W 0x76543210V will actually result in g2
getting the value {3, 2, 1, 0, 3, 2, 1, 0}.  In particular, the bottom
four nibbles are repeated instead of the top four being taken.  (A mov
of 0x00003210V yields the same result.)  This bug does not appear in any
hardware documentation as far as we can tell and the simulator does not
implement the bug either.

Commit 6132992cdb858268af0e985727d80e4140be389c was mostly a no-op
except that it changed the type of the subgroup invocation from UW to W
and caused us to tickle this bug with basically every compute shader
that uses any sort of invocation ID (which is most of them).  This is
also potentially an issue for geometry shader input pulls and SampleID
setup.  The easy solution is just to change the few places where we use
a vector integer immediate with a W type to use a UW type.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Fixes: 6132992cdb858268af0e985727d80e4140be389c
4 years agoac/nir: fix translation of nir_op_fsign for doubles
Timothy Arceri [Thu, 11 Jan 2018 11:10:47 +0000 (22:10 +1100)]
ac/nir: fix translation of nir_op_fsign for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoac: add f64_0 to the llvm build context
Timothy Arceri [Thu, 11 Jan 2018 11:09:35 +0000 (22:09 +1100)]
ac: add f64_0 to the llvm build context

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoac/nir: fix translation of nir_op_frcp for doubles
Timothy Arceri [Thu, 11 Jan 2018 10:11:00 +0000 (21:11 +1100)]
ac/nir: fix translation of nir_op_frcp for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoac/nir: fix translation of nir_op_frsq for doubles
Timothy Arceri [Thu, 11 Jan 2018 06:04:22 +0000 (17:04 +1100)]
ac/nir: fix translation of nir_op_frsq for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoac: add f64_1 to the llvm build context
Timothy Arceri [Thu, 11 Jan 2018 06:03:36 +0000 (17:03 +1100)]
ac: add f64_1 to the llvm build context

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoradv: reset semaphores & fences on sync_file export.
Bas Nieuwenhuizen [Thu, 4 Jan 2018 01:55:39 +0000 (02:55 +0100)]
radv: reset semaphores & fences on sync_file export.

Per spec:

"Additionally, exporting a fence payload to a handle with copy transference has the same side effects
on the source fence’s payload as executing a fence reset operation. If the fence was using a
temporarily imported payload, the fence’s prior permanent payload will be restored."

And similar for semaphores:

"Additionally, exporting a semaphore payload to a handle with copy transference has the same side
effects on the source semaphore’s payload as executing a semaphore wait operation. If the
semaphore was using a temporarily imported payload, the semaphore’s prior permanent payload
will be restored."

Fixes: 42bc25a79c "radv: Advertise sync fd import and export."
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agointel: Add more Coffee Lake PCI IDs
Anuj Phogat [Fri, 5 Jan 2018 17:17:36 +0000 (09:17 -0800)]
intel: Add more Coffee Lake PCI IDs

More Coffee Lake PCI IDs have been added to the spec.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
4 years agoRevert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""
Matt Turner [Fri, 5 Jan 2018 17:46:11 +0000 (09:46 -0800)]
Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""

This reverts commit 2d0457203871c843ebfc90fb895b65a9b14cd9bb.

Acked-by: Scott D Phillips <scott.d.phillips@intel.com>
4 years agoi965/fs: Add/use functions to convert to 3src_align1 vstride/hstride
Matt Turner [Mon, 11 Dec 2017 19:44:48 +0000 (11:44 -0800)]
i965/fs: Add/use functions to convert to 3src_align1 vstride/hstride

Some cases weren't handled, such as stride 4 which is needed for 64-bit
operations. Presumably fixes the assertion failure mentioned in commit
2d0457203871 (Revert "i965/fs: Use align1 mode on ternary instructions
on Gen10+") but who can really say since the commit neglected to list
any of them!

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
4 years agoanv: Make sure state on primary is correct after CmdExecuteCommands
Alex Smith [Tue, 9 Jan 2018 16:49:02 +0000 (08:49 -0800)]
anv: Make sure state on primary is correct after CmdExecuteCommands

After executing a secondary command buffer, we need to update certain
state on the primary command buffer to reflect changes by the secondary.
Otherwise subsequent commands may not have the correct state set.

This fixes various issues (rendering errors, GPU hangs) seen after
executing secondary command buffers in some cases.

v2 (Jason Ekstrand):
 - Reset to invalid values instead of pulling from the secondary
 - Change the comment to be more descriptive

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
4 years agosvga: simplify failure code in emit_rss_vgpu9()
Brian Paul [Fri, 29 Dec 2017 17:03:43 +0000 (10:03 -0700)]
svga: simplify failure code in emit_rss_vgpu9()

No need for a goto.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agosvga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()
Brian Paul [Fri, 29 Dec 2017 17:02:10 +0000 (10:02 -0700)]
svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agosvga: add assertion in svga_queue_rs()
Brian Paul [Fri, 29 Dec 2017 16:59:02 +0000 (09:59 -0700)]
svga: add assertion in svga_queue_rs()

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agosvga: whitespace/formatting fixes in svga_state_rss.c
Brian Paul [Fri, 29 Dec 2017 16:54:26 +0000 (09:54 -0700)]
svga: whitespace/formatting fixes in svga_state_rss.c

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
4 years agoanv: Import mako templates only during execution of anv_extensions
Andres Gomez [Wed, 10 Jan 2018 21:11:51 +0000 (23:11 +0200)]
anv: Import mako templates only during execution of anv_extensions

anv_extensions usage from anv_icd was bringing the unwanted dependency
of mako templates for the latter. We don't want that since it will
force the dependency even for distributable tarballs which was not
needed until now.

Jason suggested this approach.

v2: Patch simplification (Jason).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104551
Fixes: 0ab04ba979b ("anv: Use python to generate ICD json files")
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoglsl: cleanup shader_cache header guard
Tapani Pälli [Thu, 28 Dec 2017 07:30:08 +0000 (09:30 +0200)]
glsl: cleanup shader_cache header guard

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
4 years agoanv: fix maxDescriptorSet* limits
Samuel Iglesias Gonsálvez [Wed, 10 Jan 2018 08:15:50 +0000 (09:15 +0100)]
anv: fix maxDescriptorSet* limits

"The maxDescriptorSet* limit is n times the corresponding
maxPerStageDescriptor* limit, where n is the number of shader stages
supported by the VkPhysicalDevice. If all shader stages are supported,
n = 6 (vertex, tessellation control, tessellation evaluation,
geometry, fragment, compute)."

Fixes:

dEQP-VK.api.info.device.properties

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoac: add load_patch_vertices_in() to the abi
Timothy Arceri [Wed, 10 Jan 2018 06:01:10 +0000 (17:01 +1100)]
ac: add load_patch_vertices_in() to the abi

Fixes the follow test for radeonsi nir:

tests/spec/arb_tessellation_shader/execution/quads.shader_test

Also stops 8 other tests from crashing, they now just fail e.g.

tcs-output-array-float-index-rd-after-barrier.shader_test

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
4 years agoac/nir: Sanitize location_frac for local variables.
Bas Nieuwenhuizen [Wed, 10 Jan 2018 16:05:10 +0000 (17:05 +0100)]
ac/nir: Sanitize location_frac for local variables.

If they were promoted from inputs/outputs, they could have a
non-zero value left over, which messed with our store handling.

Fixes: 06f05040eb "radv: Link shaders."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
4 years agotgsi: include struct definitions for tgsi_build declarations
Rob Herring [Mon, 8 Jan 2018 21:17:48 +0000 (15:17 -0600)]
tgsi: include struct definitions for tgsi_build declarations

Many of the functions declared in tgsi_build.h return structs (not struct
pointers). Therefore the full struct definitions are needed to avoid
warnings or errors:

In file included from src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:23:
external/mesa3d/src/gallium/auxiliary/tgsi/tgsi_build.h:47:1: error: 'tgsi_build_header' has C-linkage specified, but returns incomplete type 'struct tgsi_header' which could be incompatible with C [-Werror,-Wreturn-type-c-linkage]

This error shows up on Android builds using clang and -Werror.

Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Herring <robh@kernel.org>
4 years agoswr: Handle indirect indices in GS
George Kyriazis [Wed, 20 Dec 2017 19:56:45 +0000 (13:56 -0600)]
swr: Handle indirect indices in GS

BuilderSWR::swr_gs_llvm_fetch_input() (and consequently
 swr_gs_llvm_fetch_input()), did not handle the case where
is_vindex_indirect or is_aindex_direct is set.

Implement it, using the code in draw_llvm.c as a guideline.

Fixes the following piglit tests:
dynamic_input_array_index (crash)
gs-input-array-vec4-index-rd
vs-output-array-vec4-index-wr-before-gs

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoamd/common: use ac_build_buffer_load() for emitting UBO loads
Samuel Pitoiset [Wed, 10 Jan 2018 11:57:20 +0000 (12:57 +0100)]
amd/common: use ac_build_buffer_load() for emitting UBO loads

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoamd/common: import get_{load,store}_intr_attribs() from RadeonSI
Samuel Pitoiset [Wed, 10 Jan 2018 11:57:19 +0000 (12:57 +0100)]
amd/common: import get_{load,store}_intr_attribs() from RadeonSI

v2: move those helpers to the header and use static inline

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
4 years agodri_util: remove ALLOW_RGB10_CONFIGS option (v2)
Marek Olšák [Mon, 8 Jan 2018 16:58:27 +0000 (17:58 +0100)]
dri_util: remove ALLOW_RGB10_CONFIGS option (v2)

This is unused because it's for libGL/libEGL, not drivers.

v2: i965 was wrong, because it used dri_util instead of its own config.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
4 years agoswr/rast: switch win32 jit format to COFF
Tim Rowley [Thu, 4 Jan 2018 16:27:13 +0000 (10:27 -0600)]
swr/rast: switch win32 jit format to COFF

Allows for call-stack and exception handling for jitted functions.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: don't use 32-bit gathers for elements < 32-bits in size
Tim Rowley [Wed, 3 Jan 2018 17:58:50 +0000 (11:58 -0600)]
swr/rast: don't use 32-bit gathers for elements < 32-bits in size

Using a gather for elements less than 32-bits in size can cause
pagefaults when loading the last elements in a page-aligned-sized
buffer.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: autogenerate named structs instead of literal structs
Tim Rowley [Thu, 28 Dec 2017 23:56:03 +0000 (17:56 -0600)]
swr/rast: autogenerate named structs instead of literal structs

Results in far smaller and useful IR output.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: SIMD16 fetch shader jitter cleanup
Tim Rowley [Fri, 22 Dec 2017 19:58:08 +0000 (13:58 -0600)]
swr/rast: SIMD16 fetch shader jitter cleanup

Bake in USE_SIMD16_BUILDER code paths (for USE_SIMD16_SHADER defined),
remove USE_SIMD16_BUILDER define, remove deprecated psuedo-SIMD16 code
paths.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: shuffle header files for msvc pre-compiled header usage
Tim Rowley [Thu, 21 Dec 2017 17:01:37 +0000 (11:01 -0600)]
swr/rast: shuffle header files for msvc pre-compiled header usage

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoswr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)
Tim Rowley [Tue, 19 Dec 2017 19:39:09 +0000 (13:39 -0600)]
swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
4 years agoglsl/linker: Safely generate mask of possible locations
Ian Romanick [Sat, 6 Jan 2018 02:43:32 +0000 (18:43 -0800)]
glsl/linker: Safely generate mask of possible locations

If MaxAttribs were ever raised to 32, undefined behavior would occur.
We had already gone to the effort (albeit incorrectly) handle this in
one case, so fix them all.

CID: 1369628
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agoglsl/linker: Mark no locations as invalid instead of marking all locations
Ian Romanick [Sat, 6 Jan 2018 02:40:21 +0000 (18:40 -0800)]
glsl/linker: Mark no locations as invalid instead of marking all locations

If max_index were ever 32, the linker would have marked all 32
locations as invalid instead of marking none of them as invalid.  It's
a good thing the maximum value actually set by any driver for
MaxAttribs is 16.

Found by inspection while investigating CID 1369628.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agoglsl: Don't handle visit_stop in several ::accept methods
Ian Romanick [Sat, 6 Jan 2018 02:19:42 +0000 (18:19 -0800)]
glsl: Don't handle visit_stop in several ::accept methods

All cases where the result could be non-visit_continue would have
already returned.

CID: 401351, 12244651224466
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agoglsl: Remove unnecessary assignments to type
Ian Romanick [Sat, 6 Jan 2018 01:50:24 +0000 (17:50 -0800)]
glsl: Remove unnecessary assignments to type

None of these are necessary because result->type is the only thing used
outside the giant switch-statement.

CID: 12309831230984
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agonir: Silence unused parameter warnings
Ian Romanick [Thu, 4 Jan 2018 23:28:30 +0000 (15:28 -0800)]
nir: Silence unused parameter warnings

In file included from src/compiler/nir/nir_opt_algebraic.c:4:0:
src/compiler/nir/nir_search_helpers.h: In function ‘is_not_const’:
src/compiler/nir/nir_search_helpers.h:118:59: warning: unused parameter
‘num_components’ [-Wunused-parameter]
 is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components,
                                                           ^~~~~~~~~~~~~~
src/compiler/nir/nir_search_helpers.h:119:29: warning: unused parameter
‘swizzle ’ [-Wunused-parameter]
              const uint8_t *swizzle)
                             ^~~~~~~

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
4 years agoradv: Remove some typos.
Bas Nieuwenhuizen [Wed, 10 Jan 2018 12:01:29 +0000 (13:01 +0100)]
radv: Remove some typos.

Trivial.

4 years agoradv: Implement VK_EXT_discard_rectangles.
Bas Nieuwenhuizen [Wed, 10 Jan 2018 01:41:30 +0000 (02:41 +0100)]
radv: Implement VK_EXT_discard_rectangles.

Tested with a modified deferred demo and no regressions in a 1.0.2
mustpass run.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agoradv: Add mapping between dynamic state mask and external enum.
Bas Nieuwenhuizen [Tue, 9 Jan 2018 21:22:59 +0000 (22:22 +0100)]
radv: Add mapping between dynamic state mask and external enum.

The EXT values are really large, e.g.
VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 1000099000, so 1 << value
is not going to fit into a 32-bit mask.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agoamd/common: bump the number of available user SGPRS to 32 on GFX9
Samuel Pitoiset [Mon, 8 Jan 2018 14:19:34 +0000 (15:19 +0100)]
amd/common: bump the number of available user SGPRS to 32 on GFX9

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: remove radv_pipeline_layout::push_constant_stages field
Samuel Pitoiset [Tue, 9 Jan 2018 17:09:44 +0000 (18:09 +0100)]
radv: remove radv_pipeline_layout::push_constant_stages field

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoamd/common: do not rely on the pipeline for the push constants logic
Samuel Pitoiset [Tue, 9 Jan 2018 17:09:43 +0000 (18:09 +0100)]
amd/common: do not rely on the pipeline for the push constants logic

It makes more sense to rely on nir_intrinsic_load_push_constant
instead of the pipeline layout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv/gfx9: calculate the number of ES VGPRs for merged shaders
Samuel Pitoiset [Tue, 9 Jan 2018 15:01:10 +0000 (16:01 +0100)]
radv/gfx9: calculate the number of ES VGPRs for merged shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv/gfx9: enable LDS for GS only if the ES type is TES
Samuel Pitoiset [Tue, 9 Jan 2018 15:01:09 +0000 (16:01 +0100)]
radv/gfx9: enable LDS for GS only if the ES type is TES

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoamd/common: determine the ES type (VS or TES) for the GS on GFX9
Samuel Pitoiset [Tue, 9 Jan 2018 15:01:08 +0000 (16:01 +0100)]
amd/common: determine the ES type (VS or TES) for the GS on GFX9

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoi965/nir: lower TES PatchVerticesIn to a constant when a TCS is present
Iago Toral Quiroga [Tue, 9 Jan 2018 10:14:01 +0000 (11:14 +0100)]
i965/nir: lower TES PatchVerticesIn to a constant when a TCS is present

When a TCS is present at link time we know the number of vertices in the
patch and we can lower gl_PatchVerticesIn in the TesEval stage directly
to a constant. We already have a pass for this that we use in the
Vulkan pipeline, so we just reuse that.

Notice that the GLSL linker also implements this optimization, which
we are not removing because other drivers may still depend on it, so
this should only be useful for OpenGL SPIR-V shaders for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoglsl: remove Lower{TCS,TES}PatchVerticesIn
Iago Toral Quiroga [Mon, 8 Jan 2018 08:45:15 +0000 (09:45 +0100)]
glsl: remove Lower{TCS,TES}PatchVerticesIn

Intel was the only user and now NIR can do the lowering.

v2: do not try to handle it as a system value directly for the SPIR-V
    path. In GL we rather handle it as a uniform like we do for the
    GLSL path (Jason).

v3: drop LowerTESPatchVerticesIn as well (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoi965: lower gl_PatchVerticesIn to a uniform
Iago Toral Quiroga [Tue, 9 Jan 2018 08:29:17 +0000 (09:29 +0100)]
i965: lower gl_PatchVerticesIn to a uniform

We want this here instead of nir_lower_system_values because for
Vulkan we don't want this lowering to take place.

v2: do not try to handle it as a system value directly for the SPIR-V
    path. In GL we rather handle it as a uniform like we do for the
    GLSL path (Jason).

v3: do this also for the TessEval stage (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoi965/nir: add a helper to lower gl_PatchVerticesIn to a uniform
Iago Toral Quiroga [Mon, 8 Jan 2018 08:41:23 +0000 (09:41 +0100)]
i965/nir: add a helper to lower gl_PatchVerticesIn to a uniform

v2: do not try to handle it as a system value directly for the SPIR-V
    path. In GL we rather handle it as a uniform like we do for the
    GLSL path (Jason).

v3:
  - Remove the uniform variable, it is alwats -1 now (Jason)
  - Also do the lowering for the TessEval stage (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agor600: don't emit tes samplers/views when tes isn't active
Roland Scheidegger [Wed, 3 Jan 2018 02:23:13 +0000 (03:23 +0100)]
r600: don't emit tes samplers/views when tes isn't active

Similar to const buffers. The driver must not emit any tes-related state if tes
is disabled, since the hw slots are all shared by VS, therefore it would
overwrite them (the mesa state tracker might not do this, but it would be
perfectly legal to do so).
Nevertheless I think the dirty state tracking logic in the driver is
fundamentally flawed when tes is disabled/enabled, since it looks to me like
the VS (and TES) state would not get reemitted to the correct slots (if it's
not dirty anyway). Unless I'm missing something...
Theoretically, the overwrite problem could be solved by using non-overlapping
resource slots for TES and VS (since we're not even close to using half the
resource slots), but it wouldn't work for constant buffers nor samplers, and
for VS would still need to propagate changes to both LS and VS, so probably
not a useful idea.
Unfortunately there's zero coverage of this with piglit, since all tessellation
shader tests are just shader_runner tests, which are unsuitable for testing
any kind of state dependency tracking issues (so I can't even quickly hack
something up to proove it and fix it...).
TCS otoh is just fine - like GS it has its own hw slots.

Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: increase number of UBOs to 15
Roland Scheidegger [Wed, 3 Jan 2018 01:09:01 +0000 (02:09 +0100)]
r600: increase number of UBOs to 15

With the exception of the default tess levels only ever accessed
by the default tcs shader, the LDS_INFO const buffer was only accessed by vtx
instructions, and not through kcache. No idea why really, but use this to our
advantage by not using a constant buffer slot for it. This just requires us to
throw the default tess levels into the "normal" driver const buffer instead.
Alternatively, could acesss those constants via vtx instructions too, but then
we couldn't use a ordinary ureg prog accessing them as constants and would have
to generate that directly when compiling the default tcs shader. (Another
alternative would be to put all lds info into the ordinary driver const
buffer, albeit we'd maybe need to increase the fixed size as it can't fit
alongside the ucp since vs needs access to the lds info too.)

Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Dave Airlie <airlied@redhat.com>

4 years agor600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up consts
Roland Scheidegger [Tue, 2 Jan 2018 22:39:34 +0000 (23:39 +0100)]
r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up consts

Contrary to what the comment said, this appears to work just fine on my rv770
(tested with piglit textureSize 140 fs/vs samplerBuffer).
Dave Airlie confirmed it working on cayman too.
I have no clue though if it's actually preferrable to use it (unfortunately
we cannot get rid of the tex constants completely, as we still require them
for cube map txq).
Albeit filling in the format (1 channels or 4?) and the stuff related to mega-
or mini-fetch (what the hell is this...) is just a guess based on other usage
of vtx fetch instructions...

v2: it really needs to be done through texture cache (I botched the
testing because sb optimizations turned it automatically into tc, but
can't rely on it and isn't happening on tes).

Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: increase number of ubos by one to 14
Roland Scheidegger [Mon, 1 Jan 2018 03:20:41 +0000 (04:20 +0100)]
r600: increase number of ubos by one to 14

Ideally we'd support 16 (d3d11 requires 15, and mesa subtracts one for non-ubo
constants), but that's kind of impossible (it would be only doable if either
we'd somehow merge the mesa non-ubo constants with the driver constants, or
only use the driver constants with vtx fetch instead of through the kcache
mechanism - the latter probably wouldn't be too bad).
For now just do as the comment already said, place the gs ring (not really
a const buffer in any case) which is only ever referred to through vc fetch
clauses at index 16. Throw in a couple asserts for good measure to make sure
the hw limit isn't exceeded.

Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: set up constants needed for txq for buffers and cube maps with tes
Roland Scheidegger [Mon, 1 Jan 2018 02:04:38 +0000 (03:04 +0100)]
r600: set up constants needed for txq for buffers and cube maps with tes

We only did this for the other stages, but obviously tess eval/ctrl need it
too.
This fixes the (newly modified) piglit texturing/textureSize test when run
with tes stage and bufferSampler.

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: don't emit reloc for ring buffer out into the blue
Roland Scheidegger [Sun, 31 Dec 2017 18:21:04 +0000 (19:21 +0100)]
r600: don't emit reloc for ring buffer out into the blue

It looks like this reloc belongs to setting the constant reg, which is skipped
for gs ring.

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: hack up num_render_backends on Juniper to 8
Roland Scheidegger [Tue, 9 Jan 2018 02:28:45 +0000 (03:28 +0100)]
r600: hack up num_render_backends on Juniper to 8

Juniper really has a maximum of 4 RBEs (16 pixels). However, predication
always locks up on my HD 5750, and through experiments it looks like if we're
pretending it has a maximum of 8, with 4 disabled, it works correctly.
My conclusion would be that there's a bug (likely firmware, not hw) which
causes the predication logic to try to read 8 results out of the query buffer
instead of just 4, and since of course noone ever writes the upper 4, the
status bit is never set and hence it will wait for it forever.

Ideally this would be fixed in firmware, but I'd guess chances of that
happening are slim.
This will double the size of (occlusion) query result buffers, write the
status bit for the disabled rbs in these buffers, and will also add 8 results
together instead of just 4 when reading them back. The latter is unnecessary,
but it's probably not worth bothering - luckily num_render_backends isn't
used outside of occlusion queries, so don't need separate value for the
"real" maximum.
Also print out the enabled_rb_mask if it changed from the pre-fixed value
(which is already printed out), just in case there's some more problems
with chips which have some rbs disabled...

This fixes all the lockups with piglit nv_conditional_render tests on my
HD 5750 (all pass).

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agowinsys/radeon: fix up default enabled_rb_mask for r600
Roland Scheidegger [Tue, 9 Jan 2018 01:53:28 +0000 (02:53 +0100)]
winsys/radeon: fix up default enabled_rb_mask for r600

The logic had two fatal flaws which completely killed the default value.
1) drm will overwrite the value anyway even if the chip can't be handled
2) the default value logic is relying on num_render_backends, which was
filled in later.
Luckily noone is relying on it, but it's a bit confusing seeing the chip clock
printed out there (as hex) with R600_DEBUG=info...
(Albeit radeonsi does not appear to fix up the value. If kernels which don't
handle this query are still supported, radeonsi will still end up with a broken
enabled_rb_mask, I have no idea of the potential results of this there.)

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: fix enabled_rb_mask on eg/cm
Roland Scheidegger [Tue, 9 Jan 2018 00:38:27 +0000 (01:38 +0100)]
r600: fix enabled_rb_mask on eg/cm

For eg/cm, the r600_gb_backend_map will always be 0. This is a bug in
the drm kernel driver, as it just just never fills the information in
(it is now being fixed - the history shows it was being filled in when
the query was brand new but got lost shortly thereafter with backend_map
fixes).
This causes r600_query_hw_prepare_buffer to write the "status bit"
(just the highest bit of the occlusion query result) even for active rbes
(all but the first). This doesn't make much sense, albeit I suppose it's mostly
safe. According to the commit history, it's necessary to set these bits for
inactive rbes since otherwise predication will lock up - presumably the hw just
is waiting for the status bit to appear, which will never happen with inactive
rbes. I'd guess potentially predication could be wrong (due to not waiting for
the actual result if the status bit is already there) if this is set for
active rbes.

Discovered while trying to fix predication lockups on Juniper (needs another
patch).

Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: fix sampler indexing with texture buffers sampling
Roland Scheidegger [Tue, 2 Jan 2018 22:03:44 +0000 (23:03 +0100)]
r600: fix sampler indexing with texture buffers sampling

This fixes the new piglit test.
While here also fix up the logic for early exit of setting up driver consts.

Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Reviewed-by: Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: don't use vtx offset for load_sample_position
Roland Scheidegger [Mon, 1 Jan 2018 18:40:56 +0000 (19:40 +0100)]
r600: don't use vtx offset for load_sample_position

The offset looks bogus to me. Albeit in the end it doesn't matter, by the
looks of it offsets smaller than 4 get ignored there (not sure of the rules,
I suppose either non-dword aligned offsets never work there or the offset
must be at least aligned to the size of a single element).

Tested-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
4 years agor600: drop l2 related queries
Dave Airlie [Wed, 6 Dec 2017 23:41:35 +0000 (23:41 +0000)]
r600: drop l2 related queries

radeonsi only.

Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agor600/shader: only read back the necessary tess factor components.
Dave Airlie [Fri, 29 Dec 2017 03:14:21 +0000 (03:14 +0000)]
r600/shader: only read back the necessary tess factor components.

This just reduces the lds reads for the the tess factor emission.

Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agoFix use of alloca() without #include <c99_alloca.h>
Jon Turney [Wed, 13 Dec 2017 19:49:07 +0000 (19:49 +0000)]
Fix use of alloca() without #include <c99_alloca.h>

../../../src/mesa/main/shaderapi.c: In function ‘_mesa_ShaderBinary’:
../../../src/mesa/main/shaderapi.c:2188:9: error: implicit declaration of function ‘alloca’ [-Werror=implicit-function-declaration]

4 years agogenxml: Add missing INSTDONE_1 bits on Gen7.5+.
Kenneth Graunke [Mon, 8 Jan 2018 06:29:34 +0000 (22:29 -0800)]
genxml: Add missing INSTDONE_1 bits on Gen7.5+.

This will make aubinator_error_decode decode them properly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agointel: Apply Geminilake "Barrier Mode" workaround.
Kenneth Graunke [Tue, 2 Jan 2018 22:26:41 +0000 (14:26 -0800)]
intel: Apply Geminilake "Barrier Mode" workaround.

Apparently, Geminilake requires you to whack a chicken bit to select
either compute or tessellation mode for barriers.  The recommendation
is to switch between them at PIPELINE_SELECT time.

We may not need to do this all the time, but I don't know that it hurts
either.  PIPELINE_SELECT is already a pretty giant stall.

This appears to fix hangs in tessellation control shaders with barriers
on Geminilake.  Note that this requires a corresponding kernel change,

    drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

in order for the register write to actually happen.  Without an updated
kernel, this register write will be noop'd and the fix will not work.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
4 years agodocs: update calendar, add news and link release notes for 17.3.2
Emil Velikov [Tue, 9 Jan 2018 16:13:31 +0000 (16:13 +0000)]
docs: update calendar, add news and link release notes for 17.3.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
4 years agodocs: add sha256 checksums for 17.3.2
Emil Velikov [Tue, 9 Jan 2018 16:08:51 +0000 (16:08 +0000)]
docs: add sha256 checksums for 17.3.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 3a67ca681b326fb046b59a89d15e167bdf0c0acc)

4 years agodocs: add release notes for 17.3.2
Emil Velikov [Mon, 8 Jan 2018 21:32:27 +0000 (21:32 +0000)]
docs: add release notes for 17.3.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 0f27052e325c3617e437912d0a3acaf3e3afd786)

4 years agost/omx_bellagio: Update default intra matrix per MPEG2 spec
Indrajit Das [Fri, 5 Jan 2018 09:36:18 +0000 (04:36 -0500)]
st/omx_bellagio: Update default intra matrix per MPEG2 spec

Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
4 years agoaubinator: add support for aubinating memtrace aubs
Scott D Phillips [Tue, 28 Nov 2017 23:52:10 +0000 (15:52 -0800)]
aubinator: add support for aubinating memtrace aubs

Memtrace aubs are similar to classic aubs, with the major
difference being how command submission is serialized (as register
writes instead of a high-level submit message). Some internal
tools generate or consume only memtrace aubs.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
4 years agoaubinator: extract aubinator_init() out of the header handler function
Scott D Phillips [Tue, 28 Nov 2017 23:52:09 +0000 (15:52 -0800)]
aubinator: extract aubinator_init() out of the header handler function

A later patch will use the aubinator_init() function from the
memtrace aub header handler.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
4 years agoaubinator: honor --color option when printing the header
Scott D Phillips [Tue, 28 Nov 2017 23:52:08 +0000 (15:52 -0800)]
aubinator: honor --color option when printing the header

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>