mesa.git
3 years agomesa: remove unneeded semicolons
Grazvydas Ignotas [Sun, 14 Jan 2018 21:45:05 +0000 (23:45 +0200)]
mesa: remove unneeded semicolons

Trivial. Found by Coccinelle.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agoradeon: remove unneeded semicolons
Grazvydas Ignotas [Sun, 14 Jan 2018 21:40:25 +0000 (23:40 +0200)]
radeon: remove unneeded semicolons

Trivial. Found by Coccinelle.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agoosmesa: don't check SmoothFlag twice
Grazvydas Ignotas [Sun, 14 Jan 2018 19:52:52 +0000 (21:52 +0200)]
osmesa: don't check SmoothFlag twice

Trivial. Found by Coccinelle.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agoac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used
Samuel Pitoiset [Mon, 15 Jan 2018 13:51:45 +0000 (14:51 +0100)]
ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used

This is an optimisation that is recommended by Matt Arsenault,
and used by RadeonSI, but it's not compatible with Vulkan.

Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed
zeros flag in LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac: set fast math flags when RADV_DEBUG="unsafemath" is used
Samuel Pitoiset [Mon, 15 Jan 2018 13:51:44 +0000 (14:51 +0100)]
ac: set fast math flags when RADV_DEBUG="unsafemath" is used

When that debug option is not used, we use the default float mode
because the no signed zeros optimisation is not Vulkan compatible.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac: import lp_create_builder() from gallivm
Samuel Pitoiset [Mon, 15 Jan 2018 13:51:43 +0000 (14:51 +0100)]
ac: import lp_create_builder() from gallivm

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
Samuel Pitoiset [Thu, 11 Jan 2018 15:45:11 +0000 (16:45 +0100)]
ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6

This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with
LLVM < 6. Similar to RadeonSI codepath.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoglsl/linker: link-error using the same name in unnamed block and outside
Juan A. Suarez Romero [Tue, 16 Jan 2018 18:42:35 +0000 (19:42 +0100)]
glsl/linker: link-error using the same name in unnamed block and outside

According with OpenGL GLSL 4.20 spec, section 4.3.9, page 57:

   "It is a link-time error if any particular shader interface
    contains:
      - two different blocks, each having no instance name, and each
        having a member of the same name, or
      - a variable outside a block, and a block with no instance name,
        where the variable has the same name as a member in the block."

This means that it is a link error if for example we have a vertex
shader with the following definition.

  "layout(location=0) uniform Data { float a; float b; };"

and a fragment shader with:

  "uniform float a;"

As in both cases we refer to both uniforms as "a", and thus using
glGetUniformLocation() wouldn't know which one we mean.

This fixes KHR-GL*.shaders.uniform_block.common.name_matching.

v2: add fixed tests (Tapani)

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agoglx: fix non-dri build
Samuel Thibault [Mon, 15 Jan 2018 14:38:25 +0000 (15:38 +0100)]
glx: fix non-dri build

glXGetDriverConfig parameters do not provide a context to dynamically
check for the presence of the function, so the dispatcher directly calls
glXGetDriverConfig, but in non-dri builds dri_glx.c didn't provide
glXGetDriverConfig.

This change make it just return NULL in that case.

Fixes: 84f764a7591 "glxglvnddispatch: Add missing dispatch for GetDriverConfig
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
3 years agost/va: clear pointers for mpeg2 quantiser matrices
Indrajit Das [Wed, 10 Jan 2018 09:43:37 +0000 (15:13 +0530)]
st/va: clear pointers for mpeg2 quantiser matrices

This is to fix VA-API issues with GStreamer and MPEG2.
Since gstreamer does not pass quantiser matrices with each frame, invalid
pointers were being passed to the driver. This patch addresses the same.

Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
3 years agoradeon/vcn: update quantiser matrices only when requested
Indrajit Das [Wed, 10 Jan 2018 09:42:44 +0000 (15:12 +0530)]
radeon/vcn: update quantiser matrices only when requested

Only update them when the pointers are valid.

Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
3 years agoradeon/uvd: update quantiser matrices only when requested
Indrajit Das [Wed, 10 Jan 2018 09:40:17 +0000 (15:10 +0530)]
radeon/uvd: update quantiser matrices only when requested

Only upload them when the pointers are valid.

Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
3 years agoRevert "docs: Mark GLX_ARB_context_flush_control done"
Adam Jackson [Mon, 15 Jan 2018 18:47:24 +0000 (13:47 -0500)]
Revert "docs: Mark GLX_ARB_context_flush_control done"

This reverts commit d547e18184978affd95a72dc524ca648efbe9812.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490
Signed-off-by: Adam Jackson <ajax@redhat.com>
3 years agoRevert "gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control"
Adam Jackson [Mon, 15 Jan 2018 18:47:13 +0000 (13:47 -0500)]
Revert "gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control"

This reverts commit 0d044351b7043cd0bc94c1cb9b7a2213f8054414.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490
Signed-off-by: Adam Jackson <ajax@redhat.com>
3 years agoRevert "i965: Enable flush control"
Adam Jackson [Mon, 15 Jan 2018 18:47:01 +0000 (13:47 -0500)]
Revert "i965: Enable flush control"

This reverts commit 6ce9006d76c050663af0be61cc88c3215d6f8cea.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490
Signed-off-by: Adam Jackson <ajax@redhat.com>
3 years agoRevert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"
Samuel Pitoiset [Mon, 15 Jan 2018 12:47:18 +0000 (13:47 +0100)]
Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"

This can't work for two reasons:
- TESSINNER/TESSOUTER are shader input values, so never translated
to the intrinsic ops
- the shader info pass scans the current stage but we want to know
in TCS, if TES reads the tess factors.

This fixes 6 regressions related to
deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes

This reverts commit 5ba1a61648e2dea96f621a5886ad8b937a471ab4.

3 years agoamd/common: fix loading InstanceID for tess on < GFX9
Samuel Pitoiset [Thu, 11 Jan 2018 13:56:07 +0000 (14:56 +0100)]
amd/common: fix loading InstanceID for tess on < GFX9

InstanceID is in VGPR2, not 1.

One more failure that CTS didn't catch up...

Reported-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac/shader: gather If TES reads TESSINNER or TESSOUTER
Samuel Pitoiset [Fri, 12 Jan 2018 11:49:28 +0000 (12:49 +0100)]
ac/shader: gather If TES reads TESSINNER or TESSOUTER

This shouldn't be scanned in the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoac: remove ac_shader_variant_info::fs::output_mask
Samuel Pitoiset [Mon, 15 Jan 2018 10:46:52 +0000 (11:46 +0100)]
ac: remove ac_shader_variant_info::fs::output_mask

Unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agor600/shader: Initialize max_driver_temp_used correctly for the first time
Gert Wollny [Sun, 14 Jan 2018 17:13:31 +0000 (18:13 +0100)]
r600/shader: Initialize max_driver_temp_used correctly for the first time

Without this initialization the temp registers used in tgsi_declaration
may used random indices, and this may result in failing translation from TGSI
with an error message "GPR limit exceeded", because the random index is greater
then the allowed limit implying that the shader uses more temporary registers then
available.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
3 years agofreedreno/ir3: "soft" depth scheduling for SFU instructions
Rob Clark [Thu, 11 Jan 2018 21:08:47 +0000 (16:08 -0500)]
freedreno/ir3: "soft" depth scheduling for SFU instructions

First try with a "soft" depth, to try to schedule sfu instructions
further from their consumers, but fall back to hard depth (which might
result in stalling) if nothing else is avail to schedule.

Previously the consumer of a sfu instruction could end up scheduled
immediately after (since "hard" depth from sfu to consumer would be 0).
This works because legalize pass would insert a (ss) sync bit, but it
is sub-optimal since it would cause a stall.

Instead prioritize other instructions for 4 cycles if they would no
cause a nop to be inserted.  This minimizes the stalling.  There is a
slight penalty in general to overall # of instructions in shader (since
we could end up needing nop's later due to scheduling the "deeper" sfu
consumer later), but ends up being a wash on register pressure.

Overall this seems to be worth a 10+% gain in fps.  Increasing the
"soft" depth of sfu consumer beyond 4 helps a bit in some cases, but 4
seems to be a good trade-off between getting 99% of the gain and not
increasing instruction count of shaders too much.

It's possible a similar approach could help for tex/mem instructions,
but the (sy) sync bit seems to trigger a switch to a different thread-
group to hide memory latency (possibly with some limits depending on
number of registers used?).

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno/a5xx: work around SWAP vs TILE_MODE constraint
Rob Clark [Mon, 8 Jan 2018 18:40:22 +0000 (13:40 -0500)]
freedreno/a5xx: work around SWAP vs TILE_MODE constraint

If the blit isn't changing format, but is changing tiling, just lie and
call things ARGB (since the exact component order doesn't matter for a
tiling blit).

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno/a5xx: texture tiling
Rob Clark [Sun, 31 Dec 2017 20:01:51 +0000 (15:01 -0500)]
freedreno/a5xx: texture tiling

Overall a nice 5-10% gain for most games.  And more for things like
glmark2 texture benchmark.

There are some rough edges.  In particular, the hardware seems to only
support tiling or component swap.  (Ie. from hw PoV, ARGB/ABGR/RGBA/
BGRA are all the same format but with different component swap.)  For
tiled formats, only ARGB is possible.  This isn't a big problem for
*sampling* since we also have swizzle state there (and since
util_format_compose_swizzles() already takes into account the component
order, we didn't use COLOR_SWAP for sampling).  But it is a problem if
you try to render to a tiled BGRA (for example) surface.

The next patch introduces a workaround for blitter, so we can generate
tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render-
target case.  To handle that, I think we'd need to keep track that the
tiled format is different from the linear format, which seems like it
would get extra fun with sampler views/etc.

So for now, disabled by default, enable with FD_MESA_DEBUG=ttile.  In
practice it works fine for all the games I've tried, but makes piglit
grumpy.

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: update generated headers
Rob Clark [Wed, 3 Jan 2018 16:00:01 +0000 (11:00 -0500)]
freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agofreedreno: add screen->setup_slices() for tex layout
Rob Clark [Sun, 14 Jan 2018 13:57:29 +0000 (08:57 -0500)]
freedreno: add screen->setup_slices() for tex layout

The rules are sufficiently different for a5xx with tiled textures, so
split this out into something that can be implemented per-generation.
The a5xx specific implementation will come in a later patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
3 years agor300g: remove double assignment
Grazvydas Ignotas [Sun, 14 Jan 2018 19:31:55 +0000 (21:31 +0200)]
r300g: remove double assignment

Trivial. Found by Coccinelle.

3 years agoutil: use faster zlib's CRC32 implementaion
Grazvydas Ignotas [Fri, 29 Dec 2017 00:05:05 +0000 (02:05 +0200)]
util: use faster zlib's CRC32 implementaion

zlib provides a faster slice-by-4 CRC32 implementation than the
traditional single byte lookup one used by mesa. As most supported
platforms now link zlib unconditionally, we can easily use it.

Improvement for a 1MB buffer (avg MB/s, n=100, zlib 1.2.8):

  i5-6600K                    C2D E4500
mesa zlib                    mesa zlib
 443 1443 225% +/- 2.1%       403 1175 191% +/- 0.9%

It has been verified the calculation results stay the same after this
change.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoandroid,configure,meson: define HAVE_ZLIB
Grazvydas Ignotas [Thu, 28 Dec 2017 23:29:10 +0000 (01:29 +0200)]
android,configure,meson: define HAVE_ZLIB

The next change wants to use some optional zlib functionality, however
not all platforms currently use zlib. Based on earlier Jordan Justen's
patches and their review feedback.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agoutil/crc32: don't drop the const qualifier
Grazvydas Ignotas [Fri, 29 Dec 2017 01:48:52 +0000 (03:48 +0200)]
util/crc32: don't drop the const qualifier

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
3 years agoac: add doubles support to isign
Timothy Arceri [Sat, 13 Jan 2018 23:07:58 +0000 (10:07 +1100)]
ac: add doubles support to isign

Fixes a number of int64 piglit tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac: add i64_0 and i64_1 to llvm build context
Timothy Arceri [Sat, 13 Jan 2018 23:06:36 +0000 (10:06 +1100)]
ac: add i64_0 and i64_1 to llvm build context

These will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac/nir: fix translation of nir_op_b2i for doubles
Timothy Arceri [Fri, 12 Jan 2018 01:31:00 +0000 (12:31 +1100)]
ac/nir: fix translation of nir_op_b2i for doubles

V2: just zero-extend the 32-bit value.

Fixes a number of int64 piglet tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac: fix build error in si_shader
Mauro Rossi [Fri, 12 Jan 2018 14:47:34 +0000 (15:47 +0100)]
ac: fix build error in si_shader

assert() is replaced by unreachable(), to avoid following building error:

external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1:
error: control may reach end of non-void function [-Werror,-Wreturn-type]
}
^
1 error generated.

Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agoradv/radeonsi/nir: lower 64bit flrp
Timothy Arceri [Fri, 12 Jan 2018 00:12:09 +0000 (11:12 +1100)]
radv/radeonsi/nir: lower 64bit flrp

Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example:

generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agobroadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.
Eric Anholt [Fri, 12 Jan 2018 23:35:04 +0000 (15:35 -0800)]
broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.

Prevents potential infinite loops when a non-dispatched or discarded
channel never triggers the loop break condition.

3 years agobroadcom/vc5: Use XOR instead of SUB for execute flags comparisons.
Eric Anholt [Fri, 12 Jan 2018 23:38:04 +0000 (15:38 -0800)]
broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.

I think this should be equivalent other than power, and it's the kind of
comparison we use for nir_op_ieq.

3 years agobroadcom/vc5: Also check the update flags for avoiding DCE.
Eric Anholt [Fri, 12 Jan 2018 23:34:22 +0000 (15:34 -0800)]
broadcom/vc5: Also check the update flags for avoiding DCE.

I was trying to do a NULL-destination UF, and it got removed.

3 years agobroadcom/vc5: Fix up channel swizzling for textures on 4.x.
Eric Anholt [Fri, 12 Jan 2018 21:20:38 +0000 (13:20 -0800)]
broadcom/vc5: Fix up channel swizzling for textures on 4.x.

I had 3.x putting swizzling in the texture state only for 16-bit texture
returns, and in the shader for 32-bit.  This may be due to having mixed up
the return channel setup on 3.x back before I had moved it into the
compiler.  On 4.x, the non-border-color texwrap tests are passing nicely
with both 16 and 32-bit returns with swizzling in the texture state.

3 years agobroadcom/vc5: Port the draw-time state emission to V3D 4.1.
Eric Anholt [Fri, 12 Jan 2018 20:31:14 +0000 (12:31 -0800)]
broadcom/vc5: Port the draw-time state emission to V3D 4.1.

3 years agobroadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.
Eric Anholt [Fri, 12 Jan 2018 20:24:36 +0000 (12:24 -0800)]
broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.

Now that the actions are reused for centroid and nonperspective, give them
a more generic name.

3 years agobroadcom/vc5: Update pixel center setup for V3D 4.x.
Eric Anholt [Fri, 12 Jan 2018 20:02:17 +0000 (12:02 -0800)]
broadcom/vc5: Update pixel center setup for V3D 4.x.

The fxcd/fycd instructions now return half-integer pixel centers when not
doing sample-rate shading.

3 years agobroadcom/vc5: Print the buffer name in simulator overflow checks.
Eric Anholt [Fri, 12 Jan 2018 01:22:58 +0000 (17:22 -0800)]
broadcom/vc5: Print the buffer name in simulator overflow checks.

Revealed that I was writing past the TSDA, not the Z buffer as I expected.

3 years agobroadcom/vc5: Add support for loading varyings in V3D 4.1.
Eric Anholt [Thu, 11 Jan 2018 19:53:13 +0000 (11:53 -0800)]
broadcom/vc5: Add support for loading varyings in V3D 4.1.

The LDVARY signal now writes an arbitrary register, so I took out the
magic src register file and replaced it with an instruction with LDVARY
set so we have somewhere to hang a QFILE_TEMP destination for register
allocation.

3 years agobroadcom/vc5: Update state setup for V3D 4.1.
Eric Anholt [Wed, 10 Jan 2018 23:49:47 +0000 (15:49 -0800)]
broadcom/vc5: Update state setup for V3D 4.1.

3 years agobroadcom/vc5: Add compiler support for V3D 4.x texturing.
Eric Anholt [Wed, 10 Jan 2018 20:51:08 +0000 (12:51 -0800)]
broadcom/vc5: Add compiler support for V3D 4.x texturing.

3 years agobroadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).
Eric Anholt [Wed, 10 Jan 2018 21:56:11 +0000 (13:56 -0800)]
broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).

The V3D 3.x series of TMU writes with meaning depending on the texture
type is replaced with writes to specific registers for each texture
argument semantic.

3 years agobroadcom/vc5: Move V3D 3.3 texturing to a separate file.
Eric Anholt [Wed, 10 Jan 2018 20:48:05 +0000 (12:48 -0800)]
broadcom/vc5: Move V3D 3.3 texturing to a separate file.

V3D 4.x texturing changes enough that #ifdefs would just make a mess of
it.

3 years agobroadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.
Eric Anholt [Wed, 10 Jan 2018 20:22:38 +0000 (12:22 -0800)]
broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.

For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to
stop including V3.3 XML.

3 years agobroadcom/vc5: Set up depth formats for V3D 4.x.
Eric Anholt [Wed, 10 Jan 2018 00:02:44 +0000 (16:02 -0800)]
broadcom/vc5: Set up depth formats for V3D 4.x.

We no longer have the small depth-specific output format enum, and instead
depth is just at the end of the output image format enum.

3 years agobroadcom/vc5: Always use the RGBA8 formats for RGBX8.
Eric Anholt [Wed, 10 Jan 2018 00:09:10 +0000 (16:09 -0800)]
broadcom/vc5: Always use the RGBA8 formats for RGBX8.

The RGBX8 formats were dropped from V3D 4.x, but we don't really need them
anyway (we already handle other non-alpha formats by forcing A to 1).

3 years agobroadcom/vc5: Move the formats table to per-V3D-version compile.
Eric Anholt [Tue, 9 Jan 2018 23:46:34 +0000 (15:46 -0800)]
broadcom/vc5: Move the formats table to per-V3D-version compile.

3 years agobroadcom/vc5: Add support for V3D 4.1 CLIF dumping.
Eric Anholt [Tue, 9 Jan 2018 23:23:21 +0000 (15:23 -0800)]
broadcom/vc5: Add support for V3D 4.1 CLIF dumping.

3 years agobroadcom/vc5: Move the body of CLIF dumping to a per-version file.
Eric Anholt [Tue, 9 Jan 2018 23:13:27 +0000 (15:13 -0800)]
broadcom/vc5: Move the body of CLIF dumping to a per-version file.

I want the library's entrypoints to still be unversioned, but the actual
packet dumping needs to be per-version.

3 years agobroadcom/vc5: Use THRSW to enable multi-threaded shaders.
Eric Anholt [Mon, 8 Jan 2018 19:55:31 +0000 (11:55 -0800)]
broadcom/vc5: Use THRSW to enable multi-threaded shaders.

This is a major performance boost on all of V3D, but is required on V3D
4.x where shaders are always either 2- or 4-threaded.

3 years agobroadcom/vc5: Properly schedule the thread-end THRSW.
Eric Anholt [Tue, 9 Jan 2018 17:40:57 +0000 (09:40 -0800)]
broadcom/vc5: Properly schedule the thread-end THRSW.

This fills in the delay slots of thread end as much as we can (other than
being cautious about potential TLBZ writes).

In the process, I moved the thread end THRSW instruction creation to the
scheduler.  Once we start emitting THRSWs in the shader, we need to
schedule the thread-end one differently from other THRSWs, so having it in
there makes that easy.

3 years agobroadcom/vc5: Implement GFXH-1684 workaround.
Eric Anholt [Sat, 6 Jan 2018 01:23:13 +0000 (17:23 -0800)]
broadcom/vc5: Implement GFXH-1684 workaround.

Apparently the VPM writes need to be flushed out before we end the shader.

3 years agobroadcom/vc5: Port drawing commands to V3D 4.x.
Eric Anholt [Fri, 5 Jan 2018 07:19:08 +0000 (23:19 -0800)]
broadcom/vc5: Port drawing commands to V3D 4.x.

This required extending the CL submit ioctl, because the tile alloc/state
buffer setup has moved from the BCL to register writes.

3 years agobroadcom/vc5: Add a test for .ifb in ADD ops.
Eric Anholt [Fri, 5 Jan 2018 00:01:19 +0000 (16:01 -0800)]
broadcom/vc5: Add a test for .ifb in ADD ops.

I had a .ifb being decoded weird in sampid, so this is to check that .ifb
is fine.

3 years agobroadcom/vc5: Add the new tesselation opcodes in V3D 4.1.
Eric Anholt [Thu, 4 Jan 2018 23:41:11 +0000 (15:41 -0800)]
broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.

3 years agobroadcom/vc5: Use a physical-reg-only register class for LDVPM.
Eric Anholt [Fri, 5 Jan 2018 22:34:51 +0000 (14:34 -0800)]
broadcom/vc5: Use a physical-reg-only register class for LDVPM.

This is needed for LDVPM on V3D 4.x, but will also be needed for keeping
values out of the accumulators across THRSW.

3 years agobroadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.
Eric Anholt [Thu, 4 Jan 2018 23:35:28 +0000 (15:35 -0800)]
broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.

Now, instead of a magic write register for VPM stores we have an
instruction to do them (which means no packing of other ALU ops into it),
with the ability to reorder the VPM stores due to the offset being baked
into the instruction.

VPM loads also gain the ability to be reordered by packing the row into
the A argument.  They also no longer write to the r3 accumulator, and
instead must be stored to a physical register.

3 years agobroadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.
Eric Anholt [Thu, 11 Jan 2018 18:46:09 +0000 (10:46 -0800)]
broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.

I had all the packing code in this file at one point, but these defines
now live in qpu_pack.c.

3 years agobroadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.
Eric Anholt [Fri, 5 Jan 2018 06:47:54 +0000 (22:47 -0800)]
broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.

3 years agobroadcom/vc5: Enable the driver on V3D 4.1
Eric Anholt [Thu, 4 Jan 2018 19:33:16 +0000 (11:33 -0800)]
broadcom/vc5: Enable the driver on V3D 4.1

3 years agobroadcom/vc5: Port the simulator to support V3D 4.1
Eric Anholt [Thu, 4 Jan 2018 19:32:46 +0000 (11:32 -0800)]
broadcom/vc5: Port the simulator to support V3D 4.1

This required moving the register accesses to a separate v3dx file, since
the register definitions for each V3D version collide.  It seems that
initializing the v3d_hw from a file dictating 3.3
(v3d_simulator_wrapper.cpp) is safe, though.

3 years agobroadcom/vc5: Drop signal bit #defines.
Eric Anholt [Thu, 4 Jan 2018 19:21:33 +0000 (11:21 -0800)]
broadcom/vc5: Drop signal bit #defines.

Signals are more complicated than that, and tables ended up being better.

3 years agobroadcom/vc5: Add support for V3Dv4 signal bits.
Eric Anholt [Thu, 4 Jan 2018 05:42:33 +0000 (21:42 -0800)]
broadcom/vc5: Add support for V3Dv4 signal bits.

The WRTMUC replaces the implicit uniform loads in the first two texture
instructions.  LDVPM disappears in favor of an ALU op.  LDVARY, LDTMU,
LDTLB, and LDUNIF*RF now write to arbitrary registers, which required
passing the devinfo through to a few more functions.

3 years agobroadcom/vc5: Fix pack/unpack of vfmul input unpack flags.
Eric Anholt [Thu, 4 Jan 2018 18:34:36 +0000 (10:34 -0800)]
broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.

3 years agobroadcom/vc5: Port the RCL setup to V3D4.1.
Eric Anholt [Thu, 28 Dec 2017 22:00:15 +0000 (14:00 -0800)]
broadcom/vc5: Port the RCL setup to V3D4.1.

The TLB load/store path is rebuilt in this version.  There is no longer a
single-byte resolved store or the 3-byte extended store.  Instead, you get
to always use general loads/stores (which, honestly, was tempting even in
previous versions).

3 years agobroadcom/vc5: Fix per-tile extra clear packet.
Eric Anholt [Tue, 9 Jan 2018 22:59:19 +0000 (14:59 -0800)]
broadcom/vc5: Fix per-tile extra clear packet.

I accidentally emitted this into the RCL instead of the per-tile generic
list, so we wouldn't get tiles after the first cleared.

3 years agobroadcom/vc5: Move the TLB loads and stores to helper functions.
Eric Anholt [Wed, 3 Jan 2018 19:08:53 +0000 (11:08 -0800)]
broadcom/vc5: Move the TLB loads and stores to helper functions.

This is going to get more complicated with V3D 4.1 support, which redoes
all the TLB packets.

3 years agobroadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.
Eric Anholt [Wed, 3 Jan 2018 20:42:13 +0000 (12:42 -0800)]
broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.

To conditionally compile cl_emit() macros per V3D version, we need it to
expand to whatever V3D we're building for.  This required emitting #define
V3D_VERSION 33 in all our currently 3.3-only code.

3 years agobroadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.
Eric Anholt [Tue, 10 Oct 2017 20:25:45 +0000 (13:25 -0700)]
broadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.

This will be used by vc5 for prefixing functions and including the pack
header in v3d-version-dependent code, following the model of anv.

3 years agobroadcom/cle: Fix error path of missing a "type" in the XML.
Eric Anholt [Thu, 28 Dec 2017 21:51:36 +0000 (13:51 -0800)]
broadcom/cle: Fix error path of missing a "type" in the XML.

We try to emit a #error and continue so that you can debug the missing
type at C compile time, but were missing a couple of definitions in that
path (sigh, python).

3 years agobroadcom/vc5: Add XML for V3D v4.1 (BCM7278)
Eric Anholt [Thu, 28 Dec 2017 00:18:02 +0000 (16:18 -0800)]
broadcom/vc5: Add XML for V3D v4.1 (BCM7278)

3 years agoac: add 'const' qualifiers to the shader info pass
Samuel Pitoiset [Thu, 11 Jan 2018 21:07:25 +0000 (22:07 +0100)]
ac: add 'const' qualifiers to the shader info pass

For clarification purposes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac: remove unused ac_nir_compiler_options from gather_info_input_decl()
Samuel Pitoiset [Thu, 11 Jan 2018 21:07:24 +0000 (22:07 +0100)]
ac: remove unused ac_nir_compiler_options from gather_info_input_decl()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agonir: add a 'const' qualifier to nir_ssa_def_components_read()
Samuel Pitoiset [Thu, 11 Jan 2018 21:07:23 +0000 (22:07 +0100)]
nir: add a 'const' qualifier to nir_ssa_def_components_read()

To avoid compilation warnings and because this helper
shouldn't update anything.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoloader/dri3: Avoid freeing renderbuffers in use
Thomas Hellstrom [Thu, 11 Jan 2018 09:19:23 +0000 (10:19 +0100)]
loader/dri3: Avoid freeing renderbuffers in use

Upon reception of an event that lowered the number of active back buffers,
the code would immediately try to free all back buffers with an id equal to or
higher than the new number of active back buffers.

However, that could lead to an active or to-be-active back buffer being freed,
since the old number of back buffers was used when obtaining an idle back
buffer for use.

This lead to crashes when lowering the number of active back buffers by
transitioning from page-flipping to non-page-flipping presents.

Fix this by computing the number of active back buffers only when trying to
obtain a new back buffer.

Fixes: 15e208c4cc ("loader/dri3: Don't accidently free buffer holding new back content")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Andriy.Khulap <andriy.khulap@globallogic.com>
Tested-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
3 years agoanv: VkDescriptorSetLayoutBinding can have descriptorCount == 0
Samuel Iglesias Gonsálvez [Thu, 11 Jan 2018 10:15:30 +0000 (11:15 +0100)]
anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0

From Vulkan spec:

"descriptorCount is the number of descriptors contained in the binding,
accessed in a shader as an array. If descriptorCount is zero this
binding entry is reserved and the resource must not be accessed from
any stage via this binding within any pipeline using the set layout."

Fixes:

dEQP-VK.binding_model.descriptor_update.empty_descriptor.uniform_buffer

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
3 years agomesa: require at least 14 UBOs for GL 4.3
Roland Scheidegger [Thu, 11 Jan 2018 01:10:25 +0000 (02:10 +0100)]
mesa: require at least 14 UBOs for GL 4.3

ARB_ubo requires 12 UBOs (per stage) at least, but this limit has been
raised by GL 4.3 to 14, so don't advertize GL 4.3 without it (only checking
the vertex stage since all drivers probably have the same limit anyway for
other stages). (piglit has minmax tests for that kind of thing, but they go
only up to 3.3, so this won't really be noticed.)
I think this currently should not affect any driver - r600 until very
recently only supported 12 but now advertizes 14 too.

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agoutil: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h
Roland Scheidegger [Thu, 11 Jan 2018 00:49:00 +0000 (01:49 +0100)]
util: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h

We've seen some problems internally due to macro redefinition.
Fix this by adding HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h,
and defining it for msvc.
And avoid redefinition just in case.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
3 years agoradv: don't emit unneeded vertex state.
Dave Airlie [Wed, 10 Jan 2018 22:02:52 +0000 (08:02 +1000)]
radv: don't emit unneeded vertex state.

If the number of instances hasn't changed and we've already
emitted it, don't emit it again.

If the vertex shader is the same and the first_instance, vertex_offset
haven't changed don't emit them again.

This increases the fps in GL_vs_VK -t 1 -m -api vk from around 40
to around 60 here, it may not impact anything else.

Dieter also reported smoketest going from 1060->1200 fps.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
3 years agoradv: trim buffer load result (fixes dota2)
Dave Airlie [Thu, 11 Jan 2018 02:10:23 +0000 (02:10 +0000)]
radv: trim buffer load result (fixes dota2)

Running dota2 since the below commit crashes with an llvm assert.

Trim the vector like the other user. This possible could also be
avoided by not padding inside the load vec3->vec4.

Fixes: 41c36c4549 (amd/common: use ac_build_buffer_load() for emitting UBO loads)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
3 years agomeson: add variable for including include/GL/internal
Dylan Baker [Wed, 3 Jan 2018 20:37:34 +0000 (12:37 -0800)]
meson: add variable for including include/GL/internal

Signed-off-by: <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agomeson: define inc_gbm as empty if not otherwise assigned
Dylan Baker [Wed, 3 Jan 2018 20:33:55 +0000 (12:33 -0800)]
meson: define inc_gbm as empty if not otherwise assigned

Otherwise this could be undefined in the egl directory.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agomeson: move libsensors dependency to libgallium
Dylan Baker [Tue, 12 Dec 2017 20:25:34 +0000 (12:25 -0800)]
meson: move libsensors dependency to libgallium

This simplifies the build by removing the need to link targets against
libsensors.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
3 years agomeson: Use dependencies for nir
Dylan Baker [Tue, 12 Dec 2017 20:22:56 +0000 (12:22 -0800)]
meson: Use dependencies for nir

This creates two new internal dependencies, idep_nir_headers and
idep_nir. The former encapsulates the generation of nir_opcodes.h and
nir_builder_opcodes.h and adding src/compiler/nir as an include path.
This ensures that any target that needs nir headers will have the
includes and that the generated headers will be generated before the
target is build. The second, idep_nir, includes the first and
additionally links to libnir.

This is intended to make it easier to avoid race conditions in the build
when using nir, since the number of consumers for libnir and it's
headers are quite high.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
3 years agomeson: don't use intermediate variables that are immediately discarded
Dylan Baker [Tue, 12 Dec 2017 00:16:56 +0000 (16:16 -0800)]
meson: don't use intermediate variables that are immediately discarded

For things like:
loop
    x = func()
    list += x
end

just do:
loop
    list += func()
end

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
3 years agomeson: Use consistent style for tests
Dylan Baker [Tue, 12 Dec 2017 00:13:31 +0000 (16:13 -0800)]
meson: Use consistent style for tests

Don't use intermediate variables, use consistent whitespace.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
3 years agomeson: Use include variables
Dylan Baker [Mon, 11 Dec 2017 23:58:00 +0000 (15:58 -0800)]
meson: Use include variables

These were added after adderlib was mesonified, but it still good to use
them instead of open coding them.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
3 years agomeson: Use consistent style
Dylan Baker [Mon, 11 Dec 2017 23:56:08 +0000 (15:56 -0800)]
meson: Use consistent style

Currently the meosn build has a mix of two styles:
arg : [foo, ...
       bar],

and
arg : [
  foo, ...,
  bar,
]

For consistency let's pick one. I've picked the later style, which I
think is more readable, and is more common in the mesa code base.

v2: - fix commit message

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
3 years agoi965: Use UD types for gl_SampleID setup
Jason Ekstrand [Sat, 6 Jan 2018 02:50:14 +0000 (18:50 -0800)]
i965: Use UD types for gl_SampleID setup

We already had to switch all of the W types to UW to prevent issues
with vector immediates on gen10.  We may as well use unsigned types
everywhere.

Reviewed-by: Matt Turner <mattst88@gmail.com>
3 years agoi965/fs: Use UW types when using V immediates
Jason Ekstrand [Sat, 6 Jan 2018 02:26:58 +0000 (18:26 -0800)]
i965/fs: Use UW types when using V immediates

Gen 10 has a strange hardware bug involving V immediates with W types.
It appears that a mov(8) g2<1>W 0x76543210V will actually result in g2
getting the value {3, 2, 1, 0, 3, 2, 1, 0}.  In particular, the bottom
four nibbles are repeated instead of the top four being taken.  (A mov
of 0x00003210V yields the same result.)  This bug does not appear in any
hardware documentation as far as we can tell and the simulator does not
implement the bug either.

Commit 6132992cdb858268af0e985727d80e4140be389c was mostly a no-op
except that it changed the type of the subgroup invocation from UW to W
and caused us to tickle this bug with basically every compute shader
that uses any sort of invocation ID (which is most of them).  This is
also potentially an issue for geometry shader input pulls and SampleID
setup.  The easy solution is just to change the few places where we use
a vector integer immediate with a W type to use a UW type.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Fixes: 6132992cdb858268af0e985727d80e4140be389c
3 years agoac/nir: fix translation of nir_op_fsign for doubles
Timothy Arceri [Thu, 11 Jan 2018 11:10:47 +0000 (22:10 +1100)]
ac/nir: fix translation of nir_op_fsign for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoac: add f64_0 to the llvm build context
Timothy Arceri [Thu, 11 Jan 2018 11:09:35 +0000 (22:09 +1100)]
ac: add f64_0 to the llvm build context

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoac/nir: fix translation of nir_op_frcp for doubles
Timothy Arceri [Thu, 11 Jan 2018 10:11:00 +0000 (21:11 +1100)]
ac/nir: fix translation of nir_op_frcp for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoac/nir: fix translation of nir_op_frsq for doubles
Timothy Arceri [Thu, 11 Jan 2018 06:04:22 +0000 (17:04 +1100)]
ac/nir: fix translation of nir_op_frsq for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoac: add f64_1 to the llvm build context
Timothy Arceri [Thu, 11 Jan 2018 06:03:36 +0000 (17:03 +1100)]
ac: add f64_1 to the llvm build context

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoradv: reset semaphores & fences on sync_file export.
Bas Nieuwenhuizen [Thu, 4 Jan 2018 01:55:39 +0000 (02:55 +0100)]
radv: reset semaphores & fences on sync_file export.

Per spec:

"Additionally, exporting a fence payload to a handle with copy transference has the same side effects
on the source fence’s payload as executing a fence reset operation. If the fence was using a
temporarily imported payload, the fence’s prior permanent payload will be restored."

And similar for semaphores:

"Additionally, exporting a semaphore payload to a handle with copy transference has the same side
effects on the source semaphore’s payload as executing a semaphore wait operation. If the
semaphore was using a temporarily imported payload, the semaphore’s prior permanent payload
will be restored."

Fixes: 42bc25a79c "radv: Advertise sync fd import and export."
Reviewed-by: Dave Airlie <airlied@redhat.com>