mesa.git
4 years agobroadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.
Eric Anholt [Thu, 28 Sep 2017 20:36:54 +0000 (13:36 -0700)]
broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.

The HW will halt when you hit a HALT packet, or when you hit the end
address.  Tell CLIF if there's an end address is so that it can stop
correctly.  (There was usually a 0 byte after the CL, so it would stop
anyway).

4 years agobroadcom/vc5: Fix depth and stencil clear values.
Eric Anholt [Thu, 28 Sep 2017 18:41:31 +0000 (11:41 -0700)]
broadcom/vc5: Fix depth and stencil clear values.

I had misread the packet description: We always have a 32f depth, and a
separate u8 stencil.

4 years agobroadcom/vc5: Add missing Z16 format.
Eric Anholt [Thu, 28 Sep 2017 18:47:50 +0000 (11:47 -0700)]
broadcom/vc5: Add missing Z16 format.

We can render to and sample from it just fine.

4 years agobraodcom/vc5: Fix incorrect early Z writes in discard shaders.
Eric Anholt [Thu, 28 Sep 2017 17:39:07 +0000 (10:39 -0700)]
braodcom/vc5: Fix incorrect early Z writes in discard shaders.

Fixes glsl-fs-discard-02.

4 years agobroadcom/compiler: Set up passthrough Z when doing FS discards.
Eric Anholt [Thu, 28 Sep 2017 17:37:02 +0000 (10:37 -0700)]
broadcom/compiler: Set up passthrough Z when doing FS discards.

In order to keep early-Z from writing early in a discard shader, you need
to set the "modifies Z" bit in the shader state (which the new
prog_data.discards will indicate).  Then, in the shader we do a TLB write
to make Z passthrough happen (the QPU result is ignored, so we use a NULL
source).

4 years agobroadcom/compiler: Don't forget the discard state on TLB Z writes.
Eric Anholt [Thu, 28 Sep 2017 18:06:53 +0000 (11:06 -0700)]
broadcom/compiler: Don't forget the discard state on TLB Z writes.

We don't want to write Z for discarded fragments.

4 years agobroadcom/compiler: Use defines instead of magic values in TLB write setup.
Eric Anholt [Thu, 28 Sep 2017 17:56:47 +0000 (10:56 -0700)]
broadcom/compiler: Use defines instead of magic values in TLB write setup.

4 years agobroadcom/vc5: Add proper support for base_vertex and base_instance.
Eric Anholt [Wed, 27 Sep 2017 22:06:09 +0000 (15:06 -0700)]
broadcom/vc5: Add proper support for base_vertex and base_instance.

I had base_vertex hacked into the shader state setup like in vc4, but it's
not correct for big offsets.  Using the proper packet is easier and
hopefully means we can re-emit shader state setup less frequently.

4 years agobroadcom/xml: Add the vc5 Base Vertex/Base Instance packet.
Eric Anholt [Wed, 27 Sep 2017 22:05:14 +0000 (15:05 -0700)]
broadcom/xml: Add the vc5 Base Vertex/Base Instance packet.

This lets us do index_bias and ARB_base_instance.

4 years agobroadcom/vc5: Use supertiles and generic tile lists.
Eric Anholt [Wed, 27 Sep 2017 22:27:31 +0000 (15:27 -0700)]
broadcom/vc5: Use supertiles and generic tile lists.

This massively reduces the size of our RCL setup.  It also gets us closer
to supporting multicore platforms.

4 years agobroadcom/xml: Add a bunch more vc5 tile list management packets.
Eric Anholt [Wed, 27 Sep 2017 21:51:05 +0000 (14:51 -0700)]
broadcom/xml: Add a bunch more vc5 tile list management packets.

We're going to need these for MSAA, and to use the generic per-tile list.

4 years agobroadcom/xml: Remove vc5 base packet for tile bin/render mode config.
Eric Anholt [Wed, 27 Sep 2017 23:38:28 +0000 (16:38 -0700)]
broadcom/xml: Remove vc5 base packet for tile bin/render mode config.

These existed so I could unpack just the sub-id field to switch on in the
old manual CLIF dumper.  The new codegen handles sub-id automatically, but
only if these stub packets aren't there with an implicit sub-id=0.

4 years agobraodcom/xml: Fix a pasteo in vc5 store tile buffer general.
Eric Anholt [Wed, 27 Sep 2017 21:54:05 +0000 (14:54 -0700)]
braodcom/xml: Fix a pasteo in vc5 store tile buffer general.

4 years agobroadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.
Eric Anholt [Fri, 3 Feb 2017 00:24:13 +0000 (16:24 -0800)]
broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.

V3D 3.3 is a continuation of the 3D implementation in VC4 (v2.1 and v2.6).
V3D 3.3 introduces an MMU (no more CMA allocations) and support for
GLES3.1.  This driver is not currently conformant, though that will be a
target as soon as possible.

V3D 3.x parts use a new texture tiling layout common across many Broadcom
graphics parts including and the HVS scanout engine.  It also massively
changes the QPU instructions, introducing a common physical register file
(no more A/B split) and half-float instructions, while removing the 4x8
unorm instructions in favor of half-float for talking to fixed function
interfaces.  Because so much has changed, vc5 is implemented in a separate
gallium driver, using only the XML code-generation support from vc4.

v2: Fix tile layout for 64bpp textures.  Fix texture swizzling for 32-bit
    returns.  Fix up a bit of MRT setup.  Sync the simulator to kernel
    behavior a bit more.  Improve uniform debugging code.  Rebase on
    QIR->VIR rename.  Move texture state mostly to the CSOs.  Improve
    cache flushing on the simulator.  Fix program deletion
    use-after-frees.

Acked-by: Dave Airlie <airlied@gmail.com> (uabi plan)
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (uabi plan)
4 years agobroadcom: Add VC5 NIR compiler.
Eric Anholt [Fri, 3 Feb 2017 18:24:14 +0000 (10:24 -0800)]
broadcom: Add VC5 NIR compiler.

This is a pretty straightforward fork of VC4's NIR compiler to VC5.  The
condition codes, registers, and I/O have all changed, making the backend
hard to share, though their heritage is still recognizable.

v2: Move to src/broadcom/compiler to match intel's layout, rename more
    "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts
    with vc4, use new v3d_debug header, add compiler init/free functions,
    do texture swizzling in NIR to allow optimization.

4 years agobroadcom: Add vc5 CLIF dumping
Eric Anholt [Fri, 3 Feb 2017 00:25:12 +0000 (16:25 -0800)]
broadcom: Add vc5 CLIF dumping

This will be usable with "VC5_DEBUG=cl" on the vc5 driver to stream a CLIF
file (the Broadcom equivalent of i965's AUB) to stderr.  I haven't tested
that this is actually usable with the internal CLIF-consuming tools, but
is close enough as a baseline and is useful for visually inspecting the
command stream.

4 years agobroadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.
Eric Anholt [Fri, 3 Feb 2017 00:15:18 +0000 (16:15 -0800)]
broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.

Unlike VC4, I've defined an unpacked instruction format with pack/unpack
functions to convert to 64-bit encoded instructions.  This will let us
incrementally put together our instructions and validate them in a more
natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to.

The pack/unpack unfortuantely are written by hand.  While I could define
genxml for parts of it, there are many special cases (like operand order
of commutative binops choosing which binop is being performed!) and it
probably wouldn't come out much cleaner.

The disasm unit test ensures that we have the same assembly format as
Broadcom's internal tools, other than whitespace changes.

v2: Fix automake variable redefinition complaints, add test to .gitignore

4 years agobroadcom: Introduce a v3d_debug.h header for vc5 and broadcom Vulkan.
Eric Anholt [Fri, 1 Sep 2017 21:38:54 +0000 (14:38 -0700)]
broadcom: Introduce a v3d_debug.h header for vc5 and broadcom Vulkan.

Unlike vc4, where the compiler and gallium driver live together, for vc5
the compiler will live up in the shared broadcom directory, and need
access to the debug flags.  Define a set of debug flags and helpers there,
so it can be shared between compiler, vc5, and vulkan.

4 years agoconfigure: Add the new "vc5" driver to the list, requiring a simulator.
Eric Anholt [Fri, 18 Aug 2017 19:55:43 +0000 (12:55 -0700)]
configure: Add the new "vc5" driver to the list, requiring a simulator.

My intent is to develop the vc5 driver in-tree for some time to build the
CL generation and shader compiler code, and keep out-of-tree patches for
talking to an actual kernel driver until the kernel driver can be
stabilized on the hardware.

v2: Define a HAVE_BROADCOM_DRIVERS, like HAVE_INTEL or HAVE_AMD.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
4 years agonir: Move vc4's alpha test lowering to core NIR.
Eric Anholt [Thu, 23 Feb 2017 00:53:18 +0000 (16:53 -0800)]
nir: Move vc4's alpha test lowering to core NIR.

I've been doing this inside of vc4, but vc5 wants it as well and it may be
useful for other drivers (Intel has a related path for pre-gen6 with MRT,
and freedreno had a TGSI path for it at one point).

This required defining a common enum for the standard comparison
functions, but other lowering passes are likely to also want that enum.

v2: Add to meson.build as well.

Acked-by: Rob Clark <robdclark@gmail.com>
4 years agomesa: Alphabetize GL_MESA_tile_raster_order in the extensions list.
Eric Anholt [Tue, 10 Oct 2017 18:41:29 +0000 (11:41 -0700)]
mesa: Alphabetize GL_MESA_tile_raster_order in the extensions list.

trivial, fixes make check.

4 years agomesa: Implement a new GL_MESA_tile_raster_order extension.
Eric Anholt [Tue, 25 Jul 2017 23:13:57 +0000 (16:13 -0700)]
mesa: Implement a new GL_MESA_tile_raster_order extension.

The intent is to use this extension on vc4 to allow X11 to do overlapping
CopyArea() within a pixmap without first blitting the pixmap to a
temporary.  With associated glamor patches, improves x11perf
-copywinwin100 performance on a Raspberry Pi 3 from ~4700/sec to
~5130/sec, and is an even larger boost to uncomposited window movement
performance (most copywinwin100 copies don't overlap).

v2: Fix glIsEnabled() on the new enums.
v3: Drop the local spec since I'm upstreaming the spec.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agobroadcom/vc4: Expose PIPE_CAP_TILE_RASTER_ORDER
Eric Anholt [Thu, 27 Jul 2017 19:05:56 +0000 (12:05 -0700)]
broadcom/vc4: Expose PIPE_CAP_TILE_RASTER_ORDER

Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.

v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Split from the core gallium commit, drop some unnecessary code related
    to glBlitFramebuffer(), fix a crash with clears before state has been
    bound.

4 years agogallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.
Eric Anholt [Thu, 27 Jul 2017 19:05:56 +0000 (12:05 -0700)]
gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.

Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.

This commit introduces the core gallium support, vc4 changes will follow.

v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Drop vc4 changes from this commit, for clarity.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
4 years agobroadcom/vc4: Implement GL_ARB_texture_barrier.
Eric Anholt [Thu, 5 Oct 2017 18:08:23 +0000 (11:08 -0700)]
broadcom/vc4: Implement GL_ARB_texture_barrier.

Improves x11perf -copywinwin100 from ~2000/sec to ~4700/sec.  More
importantly, this is a prerequisite for the new GL_MESA_tile_raster_order
extension.

4 years agodocs: Update the list of used MESA GL enums.
Eric Anholt [Wed, 26 Jul 2017 23:02:07 +0000 (16:02 -0700)]
docs: Update the list of used MESA GL enums.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agodocs: Fix a typo in the old MESA_program_debug spec.
Eric Anholt [Wed, 26 Jul 2017 23:00:50 +0000 (16:00 -0700)]
docs: Fix a typo in the old MESA_program_debug spec.

Noticed that we had two 0x8bb4 in the spec while grepping to find an open
slot in the MESA enums set.  gl.xml had the right value.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agogit_sha1_gen: accept MESA_GIT_SHA1_OVERRIDE env var
Brian Paul [Mon, 9 Oct 2017 19:47:20 +0000 (13:47 -0600)]
git_sha1_gen: accept MESA_GIT_SHA1_OVERRIDE env var

If one uses a parent build script to download/build Mesa we may not
have a full git repository (maybe a tar archive) so the 'git rev-parse'
command will fail.

This updates the script to look for a MESA_GIT_SHA1_OVERRIDE env var.
If it's set, use that sha1 instead of using git rev-parse.  With this
change we can put a git hash in the GL_VERSION string even when we
don't have a git repo.

v2: incorporate Dylan's suggestions to simplify the code

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
4 years agomesa: move _mesa_half_is_negative() to half_float.h
Brian Paul [Thu, 5 Oct 2017 19:34:52 +0000 (13:34 -0600)]
mesa: move _mesa_half_is_negative() to half_float.h

v2: use !! in the function to be explicit about type conversion.  Though,
gcc generates the same code with or without the logical !!.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agomesa: move _mesa_exec_malloc/free() prototypes to their own header
Brian Paul [Thu, 5 Oct 2017 19:30:32 +0000 (13:30 -0600)]
mesa: move _mesa_exec_malloc/free() prototypes to their own header

Try to start removing things from the cluttered imports.h file.

v2: add new header to Makefile.sources

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
4 years agoi965: minor whitespace fix
Kenneth Graunke [Tue, 10 Oct 2017 17:18:04 +0000 (10:18 -0700)]
i965: minor whitespace fix

4 years agomesa: Set new renderbuffers to RGBA4 on all GLES contexts.
Eric Anholt [Mon, 1 May 2017 17:21:36 +0000 (10:21 -0700)]
mesa: Set new renderbuffers to RGBA4 on all GLES contexts.

Before we were doing RGBA4 on GLES3 only, but as of GLES2 2.0.22 it should
be RGBA4 as well.  Fixes DEQP
functional.state_query.rbo.renderbuffer_internal_format.

Tested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agomesa: Expose GL_OES_required_internalformat on GLES contexts.
Eric Anholt [Mon, 1 May 2017 16:28:33 +0000 (09:28 -0700)]
mesa: Expose GL_OES_required_internalformat on GLES contexts.

This extension is effectively a backport of GLES3's internalformat
handling to GLES 1/2.  It guarantees that sized internalformats specified
for textures and renderbuffers have at least the specified size stored.
That's a pretty minimal requirement, so I think it can be dummy_true and
exposed as a standard in Mesa.

As a side effect, it also allows GL_RGB565 to be specified as a texture
format, not just as a renderbuffer.  Mesa had previously been allowing 565
textures, which angered DEQP in the absence of this extension being
exposed.

v2: Allow 2101010rev with sized internalformats even on GLES3, citing the
    extension spec.  Extend extension checks for GLES2 contexts exposing
    with texture_float, texture_half_float, and texture_rg.
v3: Fix ALPHA/LUMINANCE/LUMINANCE_ALPHA error checking (GLES3 CTS
    failures)
v4: Mark GL_RGB10 non-color-renderable on ES, fix A/L/LA errors on GLES2
    with float formats.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agomesa: Only expose GLES's EXT_texture_type_2_10_10_10_REV if supported in HW.
Eric Anholt [Mon, 1 May 2017 16:51:01 +0000 (09:51 -0700)]
mesa: Only expose GLES's EXT_texture_type_2_10_10_10_REV if supported in HW.

Previously, we were downconverting to 8888 automatically if the hardware
didn't suport it.  However, with the advent of
GL_OES_required_internalformat, we have to actually store the
internalformats we advertise support for.  And, it seems rather
disingenuous to advertise the extension if we don't actually support it.

v2: Throw an error when using the format on ES2 without the extension present.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agovc4: Add support for 5551 textures.
Eric Anholt [Mon, 1 May 2017 18:25:06 +0000 (11:25 -0700)]
vc4: Add support for 5551 textures.

This keeps us from promoting them up to 8888, at the cost of not being
color-renderable.

4 years agogallium: Add support for 5551 with the 1-bit field in the low bit.
Eric Anholt [Mon, 1 May 2017 18:16:20 +0000 (11:16 -0700)]
gallium: Add support for 5551 with the 1-bit field in the low bit.

This is how VC4 stores 5551 textures, which we need to support for
GL_OES_required_internalformat.

v2: Extend commit message, fix svga driver build, add BE ordering from
    Roland.
v3: Rebase on PIPE_FORMAT_R10G10B10X2_UNORM addition.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v2)
4 years agomesa: Add X1B5G5R5 along with A1B5G5R5.
Eric Anholt [Mon, 1 May 2017 18:21:27 +0000 (11:21 -0700)]
mesa: Add X1B5G5R5 along with A1B5G5R5.

For supporting RGB5 in hardware with A in the low bit (vc4), we need this
format as well.

v2: Add proper _mesa_format_matches_format_and_type() support (from
    Nicolai).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
4 years agost_api: remove unused get_resource_for_egl_image
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:48 +0000 (13:58 +0200)]
st_api: remove unused get_resource_for_egl_image

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agost/dri: implement createImageFromRenderbuffer(2)
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:48 +0000 (13:58 +0200)]
st/dri: implement createImageFromRenderbuffer(2)

Tested with dEQP-EGL.functional.image.*renderbuffer* tests.

Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agoegl/dri: remove old left-overs
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:47 +0000 (13:58 +0200)]
egl/dri: remove old left-overs

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agoegl/dri: use createImageFromRenderbuffer2 when available
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:47 +0000 (13:58 +0200)]
egl/dri: use createImageFromRenderbuffer2 when available

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agoegl/dri: factor out egl_error_from_dri_image_error
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:47 +0000 (13:58 +0200)]
egl/dri: factor out egl_error_from_dri_image_error

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agodri_interface: add an error-returning version of createImageFromRenderbuffer
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:46 +0000 (13:58 +0200)]
dri_interface: add an error-returning version of createImageFromRenderbuffer

We ought to be able to distinguish between allocation errors and bad
parameters (non-existent renderbuffer object).

Bumps the version of the DRI Image extension to 17.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
4 years agost/mesa: don't clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:46 +0000 (13:58 +0200)]
st/mesa: don't clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS

Applications might pass in a buffer that is sized too large and rely
on the extra space of the buffer not being overwritten.

Fixes dEQP-GLES31.functional.state_query.internal_format.partial_query.num_sample_counts

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agou_threaded_context: fix a memory leak
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:46 +0000 (13:58 +0200)]
u_threaded_context: fix a memory leak

The uploaders can own transfers which need to be unmapped. Destroy them
before the final sync (they're not used from the driver thread anyway)
so that the transfer_unmap call is processed by the driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agodisk_cache: remove unnecessary NULL-pointer guards
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:45 +0000 (13:58 +0200)]
disk_cache: remove unnecessary NULL-pointer guards

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agodisk_cache: fix a memory leak
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:45 +0000 (13:58 +0200)]
disk_cache: fix a memory leak

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agost/mesa: whitespace fix
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:44 +0000 (13:58 +0200)]
st/mesa: whitespace fix

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agost/mesa: fix import of EGL images with non-zero level or layer
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:44 +0000 (13:58 +0200)]
st/mesa: fix import of EGL images with non-zero level or layer

In GL state, textures created from EGL images look like plain 2D textures
with a single level, so we use the existing layer_override facility and
add an analogous level_override one.

Fixes dEQP-EGL.functional.image.create.gles2_cubemap_{positive,negative}_{x,y,z}_rgba_texture

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agost/mesa: fix switching from surface-based to non-surface-based textures
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:44 +0000 (13:58 +0200)]
st/mesa: fix switching from surface-based to non-surface-based textures

This can happen with surface-based texture objects derived from EGL
images, since those aren't immutable.

Fixes tests in dEQP-EGL.functional.sharing.gles2.multithread.random.images.teximage2d.* and others

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
4 years agoglsl/linker: add check for compute shared memory size
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:43 +0000 (13:58 +0200)]
glsl/linker: add check for compute shared memory size

Unlike uniforms, the limit on shared memory size is not called out
explicitly in the list of things that cause linker errors, but presumably
that's just an oversight in the spec.

Fixes dEQP-GLES31.functional.debug.negative_coverage.{callbacks,get_error,log}.compute.exceed_shared_memory_size_limit

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
4 years agoetnaviv: update HW headers and fix provoking vertex
Lucas Stach [Fri, 29 Sep 2017 12:17:41 +0000 (14:17 +0200)]
etnaviv: update HW headers and fix provoking vertex

Now that the real meaning of the 2 bits in PA_SYSTEM_MODE is known,
we can set them according to the rasterizer state, which fixes uses
that are setting provoking vertex first.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoetnaviv: remove flat shading workaround
Lucas Stach [Thu, 8 Jun 2017 15:06:02 +0000 (17:06 +0200)]
etnaviv: remove flat shading workaround

It turned out not to be a hardware bug, but the shader compiler
emitting wrong varying component use information. With that fixed
we can turn flat shading back on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
4 years agoetnaviv: fix varying interpolation
Lucas Stach [Thu, 8 Jun 2017 15:01:40 +0000 (17:01 +0200)]
etnaviv: fix varying interpolation

It seems that newer cores don't use the PA_ATTRIBUTES to decide if the
varying should bypass the flat shading, but derive this from the component
use. This fixes flat shading on GC880+.

VARYING_COMPONENT_USE_POINTCOORD is a bit of a misnomer now, as it isn't
only used for pointcoords, but missing a better name I left it as-is.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
4 years agoetnaviv: fix bogus flush requests in transfer handling
Lucas Stach [Tue, 26 Sep 2017 16:27:55 +0000 (18:27 +0200)]
etnaviv: fix bogus flush requests in transfer handling

The logic to decide if we need to flush the GPU command stream was broken
and hard to reason about. Fix and clarify this.

Fixes the data sync subtests from piglit arb_vertex_buffer_object.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
4 years agoi965/tes: account for the fact that dvec3/4 inputs take two slots
Iago Toral Quiroga [Mon, 9 Oct 2017 12:17:43 +0000 (14:17 +0200)]
i965/tes: account for the fact that dvec3/4 inputs take two slots

When computing the total size of the URB for tessellation evaluation
inputs we were not accounting for this, and instead we were always
assuming that each input would take a single vec4 slot, which could
lead to computing a smaller read size than required. Specifically, this
is a problem when the last input is a dvec3/4 such that its XY components
are stored in the the second half of a payload register (which can happen
if the offset for the input in the URB is not 64-bit aligned because
there are 32-bit inputs mixed in) and the ZW components in the
first half of the next, as in this case we would fail to account for the
extra slot required for the ZW components.

Fixes (requires another fix in CTS currently in review):
KHR-GL45.enhanced_layouts.varying_locations
KHR-GL45.enhanced_layouts.varying_array_locations

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agoanv: fix null pointer dereference
Tapani Pälli [Mon, 9 Oct 2017 05:17:15 +0000 (08:17 +0300)]
anv: fix null pointer dereference

CID: 1419033

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
4 years agoradv: export KHR_relaxed_block_layout
Dave Airlie [Fri, 6 Oct 2017 01:28:29 +0000 (11:28 +1000)]
radv: export KHR_relaxed_block_layout

This seems to pass all the cts tests it enables.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agonv50/ir: fix 64-bit integer shifts
Ilia Mirkin [Tue, 10 Oct 2017 00:42:59 +0000 (20:42 -0400)]
nv50/ir: fix 64-bit integer shifts

TGSI was adjusted to always pass in 64-bit integers but nouveau was left
with the old semantics. Update to the new thing.

Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts)
Reported-by: Karol Herbst <karolherbst@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
4 years agoi965: silence coverity warning
Lionel Landwerlin [Thu, 5 Oct 2017 17:13:37 +0000 (18:13 +0100)]
i965: silence coverity warning

Also makes this statement a bit clearer.

CID: 1418920
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
4 years agoanv: Do not assert() on VK_ATTACHMENT_UNUSED
Józef Kucia [Mon, 9 Oct 2017 20:42:06 +0000 (22:42 +0200)]
anv: Do not assert() on VK_ATTACHMENT_UNUSED

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
4 years agospirv: Fix SpvOpAtomicISub
Józef Kucia [Mon, 9 Oct 2017 20:33:30 +0000 (22:33 +0200)]
spirv: Fix SpvOpAtomicISub

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
4 years agoglsl: tidy up IR after loop unrolling
Timothy Arceri [Thu, 21 Sep 2017 23:23:15 +0000 (09:23 +1000)]
glsl: tidy up IR after loop unrolling

c7affbf6875622a enabled GLSLOptimizeConservatively on some
drivers. The idea was to speed up compile times by running
the GLSL IR passes only once each time do_common_optimization()
is called. However loop unrolling can create a big mess and
with large loops can actually case compile times to increase
significantly due to a bunch of redundant if statements being
propagated to other IRs.

Here we make sure to clean things up before moving on.

There was no measureable difference in shader-db compile times,
but it makes compile times of some piglit tests go from a couple
of seconds to basically instant.

The shader-db results seemed positive also:

Totals:
SGPRS: 2829456 -> 2828376 (-0.04 %)
VGPRS: 1720793 -> 1721457 (0.04 %)
Spilled SGPRs: 7707 -> 7707 (0.00 %)
Spilled VGPRs: 33 -> 33 (0.00 %)
Private memory VGPRs: 3140 -> 2060 (-34.39 %)
Scratch size: 3308 -> 2180 (-34.10 %) dwords per thread
Code Size: 79441464 -> 79214616 (-0.29 %) bytes
LDS: 436 -> 436 (0.00 %) blocks
Max Waves: 558670 -> 558571 (-0.02 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
4 years agoglsl: make loop unrolling more like the nir unrolling path
Timothy Arceri [Mon, 4 Sep 2017 03:11:49 +0000 (13:11 +1000)]
glsl: make loop unrolling more like the nir unrolling path

The old code assumed that loop terminators will always be at
the start of the loop, resulting in otherwise unrollable
loops not being unrolled at all. For example the current
code would unroll:

  int j = 0;
  do {
     if (j > 5)
        break;

     ... do stuff ...

     j++;
  } while (j < 4);

But would fail to unroll the following as no iteration limit was
calculated because it failed to find the terminator:

  int j = 0;
  do {
     ... do stuff ...

     j++;
  } while (j < 4);

Also we would fail to unroll the following as we ended up
calculating the iteration limit as 6 rather than 4. The unroll
code then assumed we had 3 terminators rather the 2 as it
wasn't able to determine that "if (j > 5)" was redundant.

  int j = 0;
  do {
     if (j > 5)
        break;

     ... do stuff ...

     if (bool(i))
        break;

     j++;
  } while (j < 4);

This patch changes this pass to be more like the NIR unrolling pass.
With this change we handle loop terminators correctly and also
handle cases where the terminators have instructions in their
branches other than a break.

V2:
- fixed regression where loops with a break in else were never
  unrolled in v1.
- fixed confusing/wrong naming of bools in complex unrolling.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
4 years agoglsl: check if induction var incremented before use in terminator
Timothy Arceri [Thu, 21 Sep 2017 03:55:56 +0000 (13:55 +1000)]
glsl: check if induction var incremented before use in terminator

do-while loops can increment the starting value before the
condition is checked. e.g.

  do {
    ndx++;
  } while (ndx < 3);

This commit changes the code to detect this and reduces the
iteration count by 1 if found.

V2: fix terminator spelling

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
4 years agoglsl: don't drop instructions from unreachable terminators continue branch
Timothy Arceri [Tue, 5 Sep 2017 05:59:07 +0000 (15:59 +1000)]
glsl: don't drop instructions from unreachable terminators continue branch

These instructions will be executed on every iteration of the loop
we cannot drop them.

V2:
- move removal of unreachable terminators from the terminator list
  to the same place they are removed from the IR as suggested by
  Nicolai.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
4 years agotravis: Add a travis profile for meson dri drivers
Dylan Baker [Wed, 4 Oct 2017 00:36:17 +0000 (17:36 -0700)]
travis: Add a travis profile for meson dri drivers

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
4 years agotravis: don't run ninja test for meson
Dylan Baker [Wed, 4 Oct 2017 18:38:04 +0000 (11:38 -0700)]
travis: don't run ninja test for meson

This pulls in tons of extra dependencies because the tests are not
properly guarded.

v2: - Put this patch before the one that adds a loader/dri test for
      meson

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
4 years agomeson: build classic swrast
Dylan Baker [Wed, 4 Oct 2017 00:06:22 +0000 (17:06 -0700)]
meson: build classic swrast

This adds support for building the classic swrast implementation. This
driver has been tested with glxinfo and glxgears.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: build gbm
Dylan Baker [Thu, 28 Sep 2017 22:53:53 +0000 (15:53 -0700)]
meson: build gbm

This doesn't include egl support, just dri support.

v2: - when gbm is set to 'auto', only build if a dri driver is also
      enabled
    - Fix conditional to check for x11 modules with vulkan as well as
      with dri drivers
v3: - Set pkgconfig libraries.private value

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: Add support for configuring dri drivers directory.
Dylan Baker [Thu, 28 Sep 2017 20:59:04 +0000 (13:59 -0700)]
meson: Add support for configuring dri drivers directory.

v2: - drop with_ from dri_drivers_path variable (Eric A)
v3: - Move HAVE_X11_PLATFORM to the proper patch (Eric A)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: build glx
Dylan Baker [Fri, 22 Sep 2017 19:55:00 +0000 (12:55 -0700)]
meson: build glx

This gets GLX and the loader building. The resulting GLX and i965 have
been tested on piglit and seem to work fine. This patch leaves a lot of
todo's in it's wake, GLX is quite complicated, and the build options
involved are many, and the goal at the moment is to get dri and gallium
drivers building.

v2: - fix typo "vaule" -> "value"
    - put the not on the correct element of the conditional
    - Put correct description of dri3 option in this patch not the next
      one (Eric A)
    - fix non glvnd version (Eric A)
    - build glx tests
    - move loader include variables to this patch (Eric A)
v3: - set the version correctly for GL_LIB_NAME in libglx
v4: - set pkgconfig private fields

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: Build i965 and dri stack
Dylan Baker [Thu, 21 Sep 2017 03:11:32 +0000 (20:11 -0700)]
meson: Build i965 and dri stack

This gets pretty much the entire classic tree building, as well as
i965, including the various glapis. There are some workarounds for bugs
that are fixed in meson 0.43.0, which is due out on October 8th.

I have tested this with piglit using glx.

v2: - fix typo "vaule" -> "value"
    - use gtest dep instead of linking to libgtest (rebase error)
    - use gtest dep instead of linking against libgtest (rebase error)
    - copy the megadriver, then create hard links from that, then delete
      the megadriver. This matches the behavior of the autotools build.
      (Eric A)
    - Use host_machine instead of target_machine (Eric A)
    - Put a comment in the right place (Eric A)
    - Don't have two variables for the same information (Eric A)
    - Put pre_args at top of file in this patch (Eric A)
    - Fix glx generators in this patch instead of next (Eric A)
    - Remove -DMESON hack (Eric A)
    - add sha1_h to mesa in this patch (Eric A)
    - Put generators in loops when possible to reduce code in
      mapi/glapi/gen (Eric A)
v3: - put HAVE_X11_PLATFORM in this patch

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: de-tabularize meson_options.txt
Dylan Baker [Wed, 4 Oct 2017 23:18:34 +0000 (16:18 -0700)]
meson: de-tabularize meson_options.txt

This ends up being unworkable as more options get added, and with
description wrapped onto a new line it doesn't improve readability
anyway.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: only require libelf if building radv
Dylan Baker [Wed, 4 Oct 2017 18:36:06 +0000 (11:36 -0700)]
meson: only require libelf if building radv

And add a todo about clover, r600, and radeonsi, which also need libelf.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomeson: add nir_linking_helpers.c to libnir
Dylan Baker [Wed, 4 Oct 2017 23:50:50 +0000 (16:50 -0700)]
meson: add nir_linking_helpers.c to libnir

This was missed in a rebase, and doesn't affect radv or anv, only i965.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomake: Fix test to be meson compatible
Dylan Baker [Wed, 4 Oct 2017 23:11:34 +0000 (16:11 -0700)]
make: Fix test to be meson compatible

This has the same problem as the previous commit, generated headers and
hardcoded paths.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agomake: Don't traverse backwards through include directories.
Dylan Baker [Wed, 4 Oct 2017 22:33:18 +0000 (15:33 -0700)]
make: Don't traverse backwards through include directories.

Traversing back through includes is bad idea and should be avoided.
In the case here - indirect_size.h is located in the build directory
$(top_builddir)/src/glx/.

v3: - Update commit message with message provided by Emil

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agoeditorconfig: Add meson configuration
Dylan Baker [Sat, 30 Sep 2017 15:47:24 +0000 (08:47 -0700)]
editorconfig: Add meson configuration

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
4 years agoetnaviv: call util_query_clear_result(..) in the generic layer
Christian Gmeiner [Sun, 8 Oct 2017 20:00:07 +0000 (22:00 +0200)]
etnaviv: call util_query_clear_result(..) in the generic layer

Saves us from calling util_query_clear_result(..) in every query
type implementation.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
4 years agoetnaviv: push query active handling into generic layer
Christian Gmeiner [Sun, 8 Oct 2017 20:00:06 +0000 (22:00 +0200)]
etnaviv: push query active handling into generic layer

We want the same active handling for every query type. So lets
handle it in the generic layer.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>
4 years agor600: drop a bunch of post-cayman code. (v2)
Dave Airlie [Mon, 9 Oct 2017 03:30:02 +0000 (13:30 +1000)]
r600: drop a bunch of post-cayman code. (v2)

Now that Marek has split the two drivers apart, drop a bunch
of unnecessary code from the r600 half. There is probably a bunch
more hiding in the video code.

No piglit regressions on caicos.

v2: fix HAVE_LLVM protected code
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
4 years agoamd: move r600d_common.h into r600g
Marek Olšák [Sat, 7 Oct 2017 22:41:04 +0000 (00:41 +0200)]
amd: move r600d_common.h into r600g

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: shrink r600d_common.h and stop using it
Marek Olšák [Sat, 7 Oct 2017 22:03:10 +0000 (00:03 +0200)]
radeonsi: shrink r600d_common.h and stop using it

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: import cayman_msaa.c from drivers/radeon
Marek Olšák [Sat, 7 Oct 2017 21:33:44 +0000 (23:33 +0200)]
radeonsi: import cayman_msaa.c from drivers/radeon

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: remove r600_emit_reloc
Marek Olšák [Sat, 7 Oct 2017 21:08:33 +0000 (23:08 +0200)]
radeonsi: remove r600_emit_reloc

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: merge si_set_streamout_targets with si_common_set_streamout_targets
Marek Olšák [Sat, 7 Oct 2017 21:06:11 +0000 (23:06 +0200)]
radeonsi: merge si_set_streamout_targets with si_common_set_streamout_targets

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: add si_so_target_reference
Marek Olšák [Sat, 7 Oct 2017 21:04:25 +0000 (23:04 +0200)]
radeonsi: add si_so_target_reference

The src type is different on purpose.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: import r600_streamout from drivers/radeon
Marek Olšák [Sat, 7 Oct 2017 20:54:31 +0000 (22:54 +0200)]
radeonsi: import r600_streamout from drivers/radeon

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: add performance thresholds for CP DMA, decrease it for clears
Marek Olšák [Sat, 7 Oct 2017 18:50:16 +0000 (20:50 +0200)]
radeonsi: add performance thresholds for CP DMA, decrease it for clears

The first one isn't used yet.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: disable primitive binning on Vega10 (v2)
Marek Olšák [Thu, 5 Oct 2017 23:01:11 +0000 (01:01 +0200)]
radeonsi: disable primitive binning on Vega10 (v2)

Our driver implementation is known to decrease performance for some tests,
but we don't know if any apps and benchmarks (e.g. those tested by Phoronix)
are affected. This disables the feature just to be safe.

Set this to enable partial primitive binning:
    R600_DEBUG=dpbb
Set this to enable full primitive binning:
    R600_DEBUG=dpbb,dfsm

v2: add new debug options

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agoradeonsi: enumerize DBG flags
Marek Olšák [Sat, 7 Oct 2017 16:10:26 +0000 (18:10 +0200)]
radeonsi: enumerize DBG flags

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
4 years agodrirc: whitelist glthread for Spec Ops: The Line
Marek Olšák [Mon, 9 Oct 2017 13:42:22 +0000 (15:42 +0200)]
drirc: whitelist glthread for Spec Ops: The Line

On i7 4790k and a 280X, there is a boost of about 10% more FPS.

Nominated by John Ettedgui.

4 years agoradv: configure VGT_VERTEX_REUSE at pipeline creation
Samuel Pitoiset [Fri, 6 Oct 2017 07:53:21 +0000 (09:53 +0200)]
radv: configure VGT_VERTEX_REUSE at pipeline creation

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: do not need to zero-init ds/raster states
Samuel Pitoiset [Fri, 6 Oct 2017 07:53:20 +0000 (09:53 +0200)]
radv: do not need to zero-init ds/raster states

Already done when creating the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: remove unused fields in radv_raster_state
Samuel Pitoiset [Fri, 6 Oct 2017 07:53:19 +0000 (09:53 +0200)]
radv: remove unused fields in radv_raster_state

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: set ALPHA_TO_MASK_ENABLE at blend state init
Samuel Pitoiset [Fri, 6 Oct 2017 13:39:01 +0000 (15:39 +0200)]
radv: set ALPHA_TO_MASK_ENABLE at blend state init

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()
Samuel Pitoiset [Fri, 6 Oct 2017 13:39:00 +0000 (15:39 +0200)]
radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()

These registers don't change during the lifetime of the
command buffer, there is no need to re-emit them when
binding a new pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoradv: allow launching waves out-of-order for compute
Samuel Pitoiset [Fri, 6 Oct 2017 14:03:15 +0000 (16:03 +0200)]
radv: allow launching waves out-of-order for compute

Ported from RadeonSI, and -pro seems to enable it as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
4 years agoanv/wsi: Allocate enough memory for the entire image
Jason Ekstrand [Sat, 7 Oct 2017 21:37:50 +0000 (14:37 -0700)]
anv/wsi: Allocate enough memory for the entire image

Previously, we allocated memory for image->plane[0].surface.isl.size
which is great if there is no compression.  However, on BDW, we can do
CCS_D on X-tiled images so we also have to allocate space for the
auxiliary buffer.  This fixes hangs in some of the WSI CTS tests and
should also reduce hangs in real applications.  In particular, it fixes
the dEQP-VK.wsi.*.incremental_present.* test group.

When we hand the image off to X11 or Wayland, it will ignore the CCS
entirely which is ok because we do a resolve when it's transitioned to
VK_IMAGE_LAYOUT_PRESENT_SRC_KHR.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org