mesa.git
8 years agoglx/drisw: Move private structure declarations to a header file
Emil Velikov [Fri, 21 Feb 2014 23:09:16 +0000 (23:09 +0000)]
glx/drisw: Move private structure declarations to a header file

v2: Reff the correct file wrt copyright, spotted by Chia-I

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agomesa: check if GL_ARB_copy_image is enabled in _mesa_CopyImageSubData()
Brian Paul [Fri, 15 Aug 2014 13:40:47 +0000 (07:40 -0600)]
mesa: check if GL_ARB_copy_image is enabled in _mesa_CopyImageSubData()

Generate a GL error and return rather than crashing on a null
ctx->Driver.CopyImageSubData pointer (gallium).  This allows apitraces
with glCopyImageSubData() calls to continue rather than crash.

Plus, fix a comment typo.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/blorp_clear: Use memcpy instead of assignment to copy clear value
Neil Roberts [Thu, 14 Aug 2014 14:01:39 +0000 (15:01 +0100)]
i965/blorp_clear: Use memcpy instead of assignment to copy clear value

Similar to the problem described in 2c50212b14da27de4e3, if we copy the clear
value through a regular assignment via a floating point value, then if an
integer clear value is being used that happens to contain a signalling NaN
value then it would get converted to a quiet NaN when stored via the x87
floating-point registers. This would corrupt the integer value. Instead we
should use a memcpy to ensure the exact bit representation is preserved.

This bug can be triggered on 32-bit builds with optimisations by using an
integer clear color with a value like 0x7f817f81.

Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agor600g: Implement ARB_derivative_control
Glenn Kennard [Fri, 15 Aug 2014 08:30:58 +0000 (10:30 +0200)]
r600g: Implement ARB_derivative_control

Requires Evergreen/Cayman

marek: update release notes

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agodocs: Update relnotes for ARB_gpu_shader5
Chris Forbes [Sun, 10 Aug 2014 04:22:35 +0000 (16:22 +1200)]
docs: Update relnotes for ARB_gpu_shader5

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agodocs: Mark off ARB_gpu_shader5 for i965
Chris Forbes [Sun, 10 Aug 2014 04:08:36 +0000 (16:08 +1200)]
docs: Mark off ARB_gpu_shader5 for i965

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965: Enable ARB_gpu_shader5 on Gen7
Chris Forbes [Sun, 10 Aug 2014 02:36:25 +0000 (14:36 +1200)]
i965: Enable ARB_gpu_shader5 on Gen7

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965/fs: Add support for nonconst sampler indexing in FS visitor
Chris Forbes [Sun, 10 Aug 2014 00:12:06 +0000 (12:12 +1200)]
i965/fs: Add support for nonconst sampler indexing in FS visitor

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/fs: Add support for non-const sampler indices in generator
Chris Forbes [Sun, 10 Aug 2014 00:02:22 +0000 (12:02 +1200)]
i965/fs: Add support for non-const sampler indices in generator

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/fs: Refactor generate_tex in prep for nonconst sampler indexing
Chris Forbes [Sat, 9 Aug 2014 23:58:06 +0000 (11:58 +1200)]
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/fs: Use brw_adjust_sampler_state_pointer in fs generator too
Chris Forbes [Sat, 9 Aug 2014 23:54:47 +0000 (11:54 +1200)]
i965/fs: Use brw_adjust_sampler_state_pointer in fs generator too

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/vec4: Add support for nonconst sampler indexing in VS visitor
Chris Forbes [Sat, 9 Aug 2014 10:08:11 +0000 (22:08 +1200)]
i965/vec4: Add support for nonconst sampler indexing in VS visitor

V2: Set force_writemask_all on ADD; this *is* necessary in the VS case
too.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/vec4: Add support for non-const sampler indices in generator
Chris Forbes [Sat, 9 Aug 2014 23:42:08 +0000 (11:42 +1200)]
i965/vec4: Add support for non-const sampler indices in generator

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: Generalize sampler state pointer mangling for non-const
Chris Forbes [Sat, 9 Aug 2014 23:39:44 +0000 (11:39 +1200)]
i965: Generalize sampler state pointer mangling for non-const

For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/vec4: Refactor generate_tex in prep for non-const samplers
Chris Forbes [Sat, 9 Aug 2014 23:50:16 +0000 (11:50 +1200)]
i965/vec4: Refactor generate_tex in prep for non-const samplers

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: Extract helper function for surface state pointer adjustment
Chris Forbes [Sat, 9 Aug 2014 23:49:31 +0000 (11:49 +1200)]
i965: Extract helper function for surface state pointer adjustment

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agodocs: Mark off ARB_gpu_shader5 UBO array indexing for i965
Chris Forbes [Sun, 3 Aug 2014 00:32:10 +0000 (12:32 +1200)]
docs: Mark off ARB_gpu_shader5 UBO array indexing for i965

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965/vec4: Add visitor support for nonconst ubo block indexing
Chris Forbes [Sun, 29 Jun 2014 00:30:04 +0000 (12:30 +1200)]
i965/vec4: Add visitor support for nonconst ubo block indexing

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965/vec4: Generate indirect sends for nonconstant UBO array access
Chris Forbes [Sat, 12 Jul 2014 23:43:11 +0000 (11:43 +1200)]
i965/vec4: Generate indirect sends for nonconstant UBO array access

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965/fs: Add visitor support for nonconstant UBO indices
Chris Forbes [Sun, 18 May 2014 00:38:57 +0000 (12:38 +1200)]
i965/fs: Add visitor support for nonconstant UBO indices

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965/fs: Generate indirect sends for nonconstant UBO array accesses
Chris Forbes [Sat, 2 Aug 2014 02:27:21 +0000 (14:27 +1200)]
i965/fs: Generate indirect sends for nonconstant UBO array accesses

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965: Adjust set_message_descriptor to handle non-sends
Chris Forbes [Sun, 3 Aug 2014 00:02:25 +0000 (12:02 +1200)]
i965: Adjust set_message_descriptor to handle non-sends

We're about to be using this infrastructure to build descriptors in
src1 of non-send instructions, when preparing to do an indirect send.

Don't accidentally clobber the conditionalmod field of those
instructions with SFID bits, which aren't part of the descriptor.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965: Add low-level support for indirect sends
Chris Forbes [Sat, 2 Aug 2014 23:44:25 +0000 (11:44 +1200)]
i965: Add low-level support for indirect sends

This provides a reasonable place to enforce the hardware restriction
that indirect descriptors must be in a0.0

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoi965/fs: Add pass to rename registers to break live ranges.
Kenneth Graunke [Mon, 14 Apr 2014 22:01:37 +0000 (15:01 -0700)]
i965/fs: Add pass to rename registers to break live ranges.

The pass breaks live ranges of virtual registers by allocating new
registers when it sees an assignment to a virtual GRF it's already seen
written.

total instructions in shared programs: 4337879 -> 4335014 (-0.07%)
instructions in affected programs:     343865 -> 341000 (-0.83%)
GAINED:                                46
LOST:                                  1

[mattst88]: Make pass not break in presence of control flow.
            invalidate_live_intervals() only if progress.
            Fix up delta_x/delta_y.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
8 years agoi965: Fix INTDIV math assertions on Broadwell.
Kenneth Graunke [Fri, 15 Aug 2014 03:14:34 +0000 (20:14 -0700)]
i965: Fix INTDIV math assertions on Broadwell.

Commit c66d928f2c9fa59e162c391fbdd37df969959718 ("i965: Enable INTDIV
in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV
into two SIMD8 operations.

generate_math_gen6 takes two registers - for unary operations, we pass
ARF null for the second operand.  Prior to Broadwell, real operands were
always GRF.  But now they can be IMM as well.

So, check for != ARF instead of == GRF.

+12 piglits.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoRevert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."
Kenneth Graunke [Thu, 14 Aug 2014 19:22:16 +0000 (12:22 -0700)]
Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."

This reverts commit af13cf609f4257768ad8b80be8cec7f2e6ca8c81, which
appears to cause huge performance problems on Ivybridge.  I'd missed
that the FFTID bits are in the low byte.  The documentation doesn't
indicate that the URB write message header actually wants FFTID - it
just labels those bits as "Reserved."  But it appears necessary.

This does slightly more than revert the original change: originally,
Broadwell had separate code generation, which used MOV, and this patch
only changed it for Gen4-7.  Now that both are unified, reverting this
also makes Broadwell use OR.  Which should be fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agodocs: Mark off ARB_derivative_control for i965.
Chris Forbes [Thu, 14 Aug 2014 09:14:47 +0000 (21:14 +1200)]
docs: Mark off ARB_derivative_control for i965.

Also update 10.3 relnotes to match.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965: Enable ARB_derivative_control on Gen7+.
Chris Forbes [Thu, 14 Aug 2014 09:11:28 +0000 (21:11 +1200)]
i965: Enable ARB_derivative_control on Gen7+.

The extension says GL 4.0 is required. We'll meet the spirit
of that restriction by enabling on just those generations which will
soon support GL 4.0 (Gen7+), although it's technically supportable on
all generations.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965/fs: Support fine/coarse derivative opcodes
Chris Forbes [Thu, 14 Aug 2014 08:59:15 +0000 (20:59 +1200)]
i965/fs: Support fine/coarse derivative opcodes

The quality level (fine/coarse/dont-care) is plumbed through to the
generator as a constant in src1.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965/vec4: Assert that fine/coarse derivative ops don't appear
Chris Forbes [Thu, 14 Aug 2014 08:38:33 +0000 (20:38 +1200)]
i965/vec4: Assert that fine/coarse derivative ops don't appear

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoglsl: Mark program as using dFdy if coarse/fine variant is used
Chris Forbes [Thu, 14 Aug 2014 09:03:53 +0000 (21:03 +1200)]
glsl: Mark program as using dFdy if coarse/fine variant is used

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonv50,nvc0: add support for fine derivatives
Ilia Mirkin [Thu, 14 Aug 2014 04:17:17 +0000 (00:17 -0400)]
nv50,nvc0: add support for fine derivatives

The quadop-based method we currently use on all chipsets already
provides the fine version of the derivatives.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agomesa/st: add support for emitting fine derivative opcodes
Ilia Mirkin [Thu, 14 Aug 2014 04:09:18 +0000 (00:09 -0400)]
mesa/st: add support for emitting fine derivative opcodes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium: add opcodes/cap for fine derivative support
Ilia Mirkin [Thu, 14 Aug 2014 04:04:41 +0000 (00:04 -0400)]
gallium: add opcodes/cap for fine derivative support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
v2: Reuse opcode gaps as suggested by Marek

8 years agomesa/program: add new derivative unops to the unexpected list
Ilia Mirkin [Thu, 14 Aug 2014 06:02:56 +0000 (02:02 -0400)]
mesa/program: add new derivative unops to the unexpected list

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agoglsl: add ARB_derivative control support
Ilia Mirkin [Thu, 14 Aug 2014 03:33:04 +0000 (23:33 -0400)]
glsl: add ARB_derivative control support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
8 years agomesa: add ARB_derivative_control extension bit
Ilia Mirkin [Thu, 14 Aug 2014 03:27:21 +0000 (23:27 -0400)]
mesa: add ARB_derivative_control extension bit

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agomesa: add ARB_texture_barrier support
Ilia Mirkin [Mon, 11 Aug 2014 20:01:55 +0000 (16:01 -0400)]
mesa: add ARB_texture_barrier support

This extension is identical to NV_texture_barrier. Alias
glTextureBarrier to the existing glTextureBarrierNV and use the existing
NV_texture_barrier extension bit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agodocs: document radeonsi BPTC support, sort extensions in 10.3 release notes
Marek Olšák [Fri, 15 Aug 2014 00:01:07 +0000 (02:01 +0200)]
docs: document radeonsi BPTC support, sort extensions in 10.3 release notes

8 years agor600g: Implement BPTC texture support
Glenn Kennard [Wed, 13 Aug 2014 11:02:53 +0000 (13:02 +0200)]
r600g: Implement BPTC texture support

Requires Evergreen/Cayman

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agoi965: Rename intelValidateState to intel_update_state
Kristian Høgsberg [Thu, 7 Aug 2014 23:13:01 +0000 (16:13 -0700)]
i965: Rename intelValidateState to intel_update_state

This matches the name of the dd hook.  Also convert a couple of nearby
dd implementations to lowercase + underscore as is now the standard.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: Assign PS kernel start pointers when we decide which kernels to use
Kristian Høgsberg [Mon, 7 Jul 2014 21:43:30 +0000 (14:43 -0700)]
i965: Assign PS kernel start pointers when we decide which kernels to use

Right now we decide which kernels to use and the GRF start offsets in
one place and emit the kernel pointers later.  The logic of how to map
8, 16 and 32 kernels to kernel start pointers follows the same logic as which
GRF start offsets to use, so lets figure out these two things in one place.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
8 years agoradeonsi: implement BPTC texture support
Grigori Goronzy [Wed, 13 Aug 2014 00:39:02 +0000 (02:39 +0200)]
radeonsi: implement BPTC texture support

Passes all piglit tests.

v2: rebased

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: fix buffer invalidation of unbound texture buffer objects
Marek Olšák [Mon, 11 Aug 2014 13:06:23 +0000 (15:06 +0200)]
radeonsi: fix buffer invalidation of unbound texture buffer objects

This maintains a list of all TBOs in a pipe_context.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agor600g: implement invalidation of texture buffer objects
Marek Olšák [Mon, 11 Aug 2014 11:32:40 +0000 (13:32 +0200)]
r600g: implement invalidation of texture buffer objects

This fixes piglit spec/ARB_texture_buffer_object/data-sync.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agor600g: fix constant buffer fetches
Marek Olšák [Sun, 10 Aug 2014 18:21:21 +0000 (20:21 +0200)]
r600g: fix constant buffer fetches

Somebody forgot to do this. It was uncovered by recent st/mesa changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82139

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
8 years agor600g: clear constant buffer sizes at the beginning of CS
Marek Olšák [Thu, 31 Jul 2014 00:33:12 +0000 (02:33 +0200)]
r600g: clear constant buffer sizes at the beginning of CS

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoegl_dri2: fix EXT_image_dma_buf_import fds
Pekka Paalanen [Fri, 8 Aug 2014 13:26:28 +0000 (16:26 +0300)]
egl_dri2: fix EXT_image_dma_buf_import fds

The EGL_EXT_image_dma_buf_import specification was revised (according to
its revision history) on Dec 5th, 2013, for EGL to not take ownership of
the file descriptors.

Do not close the file descriptors passed in to eglCreateImageKHR with
EGL_LINUX_DMA_BUF_EXT target.

It is assumed, that the drivers, which ultimately process the file
descriptors, do not close or modify them in any way either. This avoids
the need to dup(), as it seems we would only need to just close the
dup'd file descriptors right after.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76188
Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agoi965: fix compiler error in union initiliazer
Pekka Paalanen [Thu, 14 Aug 2014 18:17:04 +0000 (21:17 +0300)]
i965: fix compiler error in union initiliazer

gcc 4.6.3 chokes with the following error:

brw_vec4.cpp: In member function 'int brw::vec4_visitor::setup_uniforms(int)':
brw_vec4.cpp:1496:37: error: expected primary-expression before '.' token

Apparently C++ does not do named initializers for unions, except maybe
as a gcc extension, which is not present here.

As .f is the first element of the union, just drop it. Fixes the build
error.

Signed-off-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965: Bail on FS copy propagation for scratch writes with source modifiers
Anuj Phogat [Tue, 29 Jul 2014 02:27:59 +0000 (19:27 -0700)]
i965: Bail on FS copy propagation for scratch writes with source modifiers

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965: Bail on vec4 copy propagation for scratch writes with source modifiers
Anuj Phogat [Mon, 28 Jul 2014 22:41:55 +0000 (15:41 -0700)]
i965: Bail on vec4 copy propagation for scratch writes with source modifiers

Fixes Khronos GLES3 CTS test:
dynamic_expression_array_access_vertex

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoglsl: Fixed vectorize pass vs. texture lookups.
Aras Pranckevicius [Wed, 13 Aug 2014 17:40:05 +0000 (20:40 +0300)]
glsl: Fixed vectorize pass vs. texture lookups.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82574
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agora: move declarations before code to fix MSVC build
Brian Paul [Thu, 14 Aug 2014 14:44:06 +0000 (08:44 -0600)]
ra: move declarations before code to fix MSVC build

Trivial.

8 years agosvga: remove some unneeded INLINE qualifiers
Brian Paul [Wed, 13 Aug 2014 22:30:48 +0000 (16:30 -0600)]
svga: remove some unneeded INLINE qualifiers

Trivial.

8 years agodocs/autoconf: update to better reflect reality
Emil Velikov [Wed, 13 Aug 2014 20:31:33 +0000 (21:31 +0100)]
docs/autoconf: update to better reflect reality

 * --enable-{32,64}-bit is done. Use --build and --host instead.
 * Configure does not add "-g -O2" to C{,XX}FLAGS.
 * Pkg-config has been mandatory for a while now.
 * Avoid using LDFLAGS, refer to pkg-config.
 * --with-expat is deprecated. Use pkg-config.

v2:
 * Note that CC/CXX will need to be set for multilib builds.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
8 years agoscons: do not include headers from the sources lists
Jose Fonseca [Wed, 13 Aug 2014 19:33:35 +0000 (20:33 +0100)]
scons: do not include headers from the sources lists

The SCons documentation is not explicit on the topic yet building mesa
with SCons and MSVC is known to have problems when headers are listed.
So be safe just drop them for now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82534
Tested-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoconfigure.ac: remove enable 32/64 bit hacks
Emil Velikov [Wed, 13 Aug 2014 17:05:56 +0000 (18:05 +0100)]
configure.ac: remove enable 32/64 bit hacks

These two were added ages ago, with an explicit comment "Hacks ..."
They have been insufficient for years and maintainers needed to
explicitly handle the build themselves.

Rather than lying and pretending that it works, just kill this hack and
let maintainers build things the way it should be done for their
distribution.

Document the removal in the release notes.

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoRevert "configure: Fix --enable-XX-bit flags by moving LT_INIT where it should"
Emil Velikov [Wed, 13 Aug 2014 16:55:39 +0000 (17:55 +0100)]
Revert "configure: Fix --enable-XX-bit flags by moving LT_INIT where it should"

This reverts commit 2af28040d639dddbb7c258981a00eaf3dfcbcf03.

The commit was resolving an issue where libtool will not setup the
environment correctly when one explicitly provides --enable-{32,64}-bit
at configure time. It was caused due to the "-m32,64" C{,XX}FLAGS being
set too late relative to LT_INIT.

At the same time this cases the enable_static to be incorrectly set,
amongst others leading to build issues. Rather than being smart and
trying to handle 32/64 bit build ourselves it may be better to delegate
it to the builder/maintainer. The latter should now know better which is
the correct(most appropriate) method.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82536
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82546
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
8 years agoi965: Store uniform constant values in a gl_constant_value instead of float
Neil Roberts [Mon, 11 Aug 2014 11:21:44 +0000 (12:21 +0100)]
i965: Store uniform constant values in a gl_constant_value instead of float

The brw_stage_prog_data struct previously contained an array of float pointers
to the values of parameters. These were then copied into a batch buffer to
upload the values using a regular assignment. However the float values were
also being overloaded to store integer values for integer uniforms. This can
break if x87 floating-point registers are used to do the assignment because
the fst instruction tries to fix up invalid float values. If an integer
constant happened to look like an invalid float value then it would get
altered when it was copied into the batch buffer.

This patch changes the pointers to be gl_constant_value instead so that the
assignment should end up copying without any alteration. This also makes it
more obvious that the values being stored here are overloaded for multiple
types.

There are some static asserts where the values are uploaded to ensure that the
size of gl_constant_value is the same as a float.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agost/vdpau: add device reference counting
Christian König [Wed, 13 Aug 2014 13:49:18 +0000 (15:49 +0200)]
st/vdpau: add device reference counting

This fixes an issue with flash where it tries to destroy a decoder
after already destroying the device associated with the decoder.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=82517
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agomesa: Make ARB_gpu_shader5 core-profile-only
Chris Forbes [Sun, 10 Aug 2014 04:10:29 +0000 (16:10 +1200)]
mesa: Make ARB_gpu_shader5 core-profile-only

Requires GLSL 1.50 or higher, which we only support in the core profile.

V2: Fix broken alignment

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonouveau: force luminance clear colors to have the same g/b values as r
Ilia Mirkin [Sun, 10 Aug 2014 19:13:44 +0000 (15:13 -0400)]
nouveau: force luminance clear colors to have the same g/b values as r

Fixes the LUMINANCE_ALPHA formats of fbo-clear-formats piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agoi965: Enable INTDIV in SIMD16 mode.
Kenneth Graunke [Thu, 17 Jul 2014 21:33:15 +0000 (14:33 -0700)]
i965: Enable INTDIV in SIMD16 mode.

All we need to do is decompose this to two SIMD8 instructions, like we
do in many other cases.  We even already have code for that.

I apparently just botched this last time I tried, and it was easy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965/fs: Drop "do dual source blending" generator parameter.
Kenneth Graunke [Tue, 8 Jul 2014 18:57:19 +0000 (11:57 -0700)]
i965/fs: Drop "do dual source blending" generator parameter.

When dual source blending, the visitor already stores a flag in
brw_wm_prog_data (dual_src_blend) for the state upload code to use.
The generator also receives this, so there's no need to pass an
additional flag.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agomesa/texstore: Don't use the _mesa_swizzle_and_convert if we need transfer ops
Jason Ekstrand [Wed, 13 Aug 2014 18:03:36 +0000 (11:03 -0700)]
mesa/texstore: Don't use the _mesa_swizzle_and_convert if we need transfer ops

The _mesa_swizzle_and_convert path can't do transfer ops, so we should bail
if they're needed.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agodocs: update ARB_vertex_attrib_64bit status
Dave Airlie [Thu, 14 Aug 2014 00:49:55 +0000 (10:49 +1000)]
docs: update ARB_vertex_attrib_64bit status

I started this as well on top of my fp64 stuff.

Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agodocs/GL3.txt: add GLES 3.1 section
Dave Airlie [Sun, 10 Aug 2014 23:04:47 +0000 (09:04 +1000)]
docs/GL3.txt: add GLES 3.1 section

This just cherry-pick the extensions into a list for GLES 3.1

I'm not actually sure if this list if complete or correct, maybe someone
else can tell me what I missed, and I'm not 100% sure on multi_draw_indirect.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agohud: don't overrun malloced arrays
Dave Airlie [Mon, 11 Aug 2014 02:07:06 +0000 (12:07 +1000)]
hud: don't overrun malloced arrays

==17630== Invalid read of size 4
==17630==    at 0x400AE10: memcpy (in /usr/lib/valgrind/vgpreload_memcheck-x86-linux.so)
==17630==    by 0x49024A2: u_upload_data (u_upload_mgr.c:253)
==17630==    by 0x49050E1: u_vbuf_draw_vbo (u_vbuf.c:980)
==17630==    by 0x487DE29: cso_draw_vbo (cso_context.c:1425)
==17630==    by 0x487DEA0: cso_draw_arrays (cso_context.c:1445)
==17630==    by 0x48A3B0E: hud_draw_colored_prims.constprop.6 (hud_context.c:123)
==17630==    by 0x48A4810: hud_draw (hud_context.c:266)
==17630==    by 0x48763F7: dri_flush (dri_drawable.c:483)
==17630==    by 0x4057510: dri2Flush.constprop.4 (dri2_glx.c:559)
==17630==    by 0x405789E: dri2SwapBuffers (dri2_glx.c:851)
==17630==    by 0x402C531: glXSwapBuffers (glxcmds.c:842)
==17630==    by 0x8049716: ??? (in /usr/bin/glxgears)
==17630==  Address 0x4426b2c is 4 bytes after a block of size 1,008 alloc'd
==17630==    at 0x4006B11: malloc (in /usr/lib/valgrind/vgpreload_memcheck-x86-linux.so)
==17630==    by 0x48A4CE7: hud_pane_add_graph (hud_context.c:625)
==17630==    by 0x48A68F0: hud_pipe_query_install (hud_driver_query.c:175)
==17630==    by 0x48A6A30: hud_driver_query_install (hud_driver_query.c:207)
==17630==    by 0x48A5835: hud_create (hud_context.c:791)
==17630==    by 0x48756CB: dri_create_context (dri_context.c:165)
==17630==    by 0x4871CD4: driCreateContextAttribs (dri_util.c:435)
==17630==    by 0x4871E06: driCreateNewContext (dri_util.c:464)
==17630==    by 0x4056A22: dri2_create_context (dri2_glx.c:223)
==17630==    by 0x402CF68: CreateContext (glxcmds.c:299)
==17630==    by 0x402D265: glXCreateContext (glxcmds.c:430)
==17630==    by 0x804B136: ??? (in /usr/bin/glxgears)

This is due to second vertex element being specified, and the upload
tries to fetch over the end. However the pane rendering only requires
a single vertex element, so specify only one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agomesa: fix texstore with GL_COLOR_INDEX data
Roland Scheidegger [Wed, 13 Aug 2014 17:30:48 +0000 (19:30 +0200)]
mesa: fix texstore with GL_COLOR_INDEX data

This got broken by 3dbf5bf6571e0c9d3e4febce01dea82be190d9d2.
GL_COLOR_INDEX data is still supported (in legacy contexts), but the new
texstore_swizzle path cannot handle it (and didn't detect this).
Unfortunately there's no piglit test trying to specify textures with a
GL_COLOR_INDEX source format, and I don't really understand how all the color
map stuff which is used by this works, but this caused conform failures
(with a reported mesa implementation error when trying to figure out the color
mapping).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agowinsys/radeon: fix hawaii accel_working2 comment
Andreas Boll [Wed, 13 Aug 2014 17:04:11 +0000 (19:04 +0200)]
winsys/radeon: fix hawaii accel_working2 comment

accel_working2 returns 3 if the new firmware is used.

The comment wasn't updated in v3 of commit:
36771dc winsys/radeon: fix nop packet padding for hawaii

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agor300g: Fix bug in build_loop_info()/compiler v2
Tom Stellard [Wed, 13 Aug 2014 18:37:03 +0000 (14:37 -0400)]
r300g: Fix bug in build_loop_info()/compiler v2

Fixes piglit glean "do-loop with continue and break" on RS690

It's based on Tom Stellard patch and improved to handle CMP instruction.

[v2] handle CMP instruction

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
8 years agoclover: Flush the command queue in clReleaseCommandQueue()
Tom Stellard [Fri, 8 Aug 2014 13:32:20 +0000 (09:32 -0400)]
clover: Flush the command queue in clReleaseCommandQueue()

This is required by the spec.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agoradeonsi/compute: Stop leaking the input buffer
Tom Stellard [Fri, 8 Aug 2014 13:27:34 +0000 (09:27 -0400)]
radeonsi/compute: Stop leaking the input buffer

We were leaking the input buffer used for kernel arguments and since
we were allocating it using si_upload_const_buffer() we were leaking
1 MB per kernel invocation.

CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agoradeonsi/compute: Whitespace fixes
Tom Stellard [Fri, 8 Aug 2014 14:05:44 +0000 (10:05 -0400)]
radeonsi/compute: Whitespace fixes

CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agoradeonsi/compute: Call si_pm4_free_state() after emitting compute state
Tom Stellard [Fri, 8 Aug 2014 13:38:08 +0000 (09:38 -0400)]
radeonsi/compute: Call si_pm4_free_state() after emitting compute state

This will decrement the reference count for buffers referenced in the
command stream will prevent us from leaking them.

CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agoradeonsi/compute: Update reference counts for buffers in si_set_global_binding()
Tom Stellard [Fri, 8 Aug 2014 13:30:33 +0000 (09:30 -0400)]
radeonsi/compute: Update reference counts for buffers in si_set_global_binding()

CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agoradeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
Tom Stellard [Thu, 7 Aug 2014 19:31:17 +0000 (15:31 -0400)]
radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE

CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agoradeon/compute: Fix reported values for MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE
Tom Stellard [Thu, 7 Aug 2014 19:21:59 +0000 (15:21 -0400)]
radeon/compute: Fix reported values for MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE

There is a hard limit in older kernels of 256 MB for buffer allocations,
so report this value as MAX_MEM_ALLOC_SIZE and adjust MAX_GLOBAL_SIZE
to statisfy requirements of OpenCL.

CC: "10.2" <mesa-stable@lists.freedesktop.org>
8 years agora: optimistically color only one node at a time
Connor Abbott [Fri, 1 Aug 2014 01:57:23 +0000 (18:57 -0700)]
ra: optimistically color only one node at a time

Before, when we encountered a situation where we had to optimistically
color a node, we would immediately give up and push all the remaining
nodes on the stack in the order of their index - which is a random, and
potentially not optimal, order. Instead, choose one node to
optimistically color in ra_select(), and then once we've optimistically
colored it, keep on going as normal in the hopes that we've opened up
more avenues for the normal select phase to make progress. In cases with
high register pressure, this helps make the order we push things on the
stack much better, and therefore increase the chance that we can allocate
successfully.

total instructions in shared programs: 4545447 -> 4545401 (-0.00%)
instructions in affected programs:     1353 -> 1307 (-3.40%)
GAINED:                                124
LOST:                                  6

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
8 years agora: don't consider nodes for spilling we don't need to
Connor Abbott [Fri, 1 Aug 2014 01:57:22 +0000 (18:57 -0700)]
ra: don't consider nodes for spilling we don't need to

Previously, we would consider any optimistically colored nodes for
spilling. However, spilling any optimistically colored nodes below the
node that we failed to color on the stack wouldn't help us make
progress, since it wouldn't help with allowing us to find a color for
the node currently failing to get colored. Only consider nodes
which were above the failing node on the stack for spilling, which
simplifies the logic, and comment the code better so people know what's
going on here.

No shader-db changes with BRW_MAX_GRF reduced to 90 (or with the normal
number of GRF's).

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
8 years agora: make the p, q test more efficient
Connor Abbott [Fri, 1 Aug 2014 01:57:21 +0000 (18:57 -0700)]
ra: make the p, q test more efficient

We can store the q total that pq_test() would've calculated in the node
itself, updating it when we add a node to the stack. This way, we only
have to walk the adjacency list when we push a node on the stack (i.e.
when the p, q test succeeds) instead of every time we do the p, q test.

No difference in shader-db run times, but I'm keeping this in because
the q total that it calculates will also be used in the next few commits.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
8 years agora: cleanup the public API
Connor Abbott [Fri, 1 Aug 2014 01:57:20 +0000 (18:57 -0700)]
ra: cleanup the public API

Previously, there were 3 entrypoints into parts of the actual allocator,
and an API called ra_allocate_no_spills() that called all 3. Nobody
would ever want to call any of the 3 entrypoints by themselves, so
everybody just used ra_allocate_no_spills(). So just make them static
functions, and while we're at it rename ra_allocate_no_spills() to
ra_allocate() since there's no equivalent "with spills," because the
backend is supposed to handle spilling.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agonouveau: only try to get new storage if there are any levels
Ilia Mirkin [Sun, 10 Aug 2014 15:52:55 +0000 (11:52 -0400)]
nouveau: only try to get new storage if there are any levels

This would try to allocate 0-sized bo's when the max level was below the
base level.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonouveau: add emacs dir-locals file for tabs/8-space indents
Ilia Mirkin [Sun, 10 Aug 2014 15:52:10 +0000 (11:52 -0400)]
nouveau: add emacs dir-locals file for tabs/8-space indents

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonvc0: increase GLSL level to 400 to enable ARB_gpu_shader5
Ilia Mirkin [Sun, 10 Aug 2014 00:03:50 +0000 (20:03 -0400)]
nvc0: increase GLSL level to 400 to enable ARB_gpu_shader5

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agomesa/st: enable ARB_gpu_shader5 if the reported GLSL version >= 400
Ilia Mirkin [Sun, 10 Aug 2014 00:00:20 +0000 (20:00 -0400)]
mesa/st: enable ARB_gpu_shader5 if the reported GLSL version >= 400

The ARB_gpu_shader5 extension is made up of a lot of small sub-parts.
Instead of adding PIPE_CAP's for each of these, just rely on the GLSL
version reported by the pipe driver. The remaining extensions lend
themselves naturally to being checked through a single CAP.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoandroid: add CleanSpec.mk
Emil Velikov [Mon, 4 Aug 2014 18:11:41 +0000 (19:11 +0100)]
android: add CleanSpec.mk

The file contains rules that are executed on incremental builds. This
way one can avoid doing a full clean and ensure that the new object
(library) is correctly build.

Inspired by the work of Chih-Wei Huang, from the Android-x86 project.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: megadriver_stub: prefix static libraries with libmesa_
Emil Velikov [Mon, 4 Aug 2014 18:03:44 +0000 (19:03 +0100)]
android: megadriver_stub: prefix static libraries with libmesa_

Will make it easier on us as CleanSpec.mk comes along and improves
consistency across the Android build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: loader: prefix static libraries with libmesa_*
Emil Velikov [Mon, 4 Aug 2014 17:59:58 +0000 (18:59 +0100)]
android: loader: prefix static libraries with libmesa_*

Will make it easier on us as CleanSpec.mk comes along and improves
consistency across the Android build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: dri/i9*5: remove used _INCLUDES variable
Emil Velikov [Mon, 28 Jul 2014 23:32:04 +0000 (00:32 +0100)]
android: dri/i9*5: remove used _INCLUDES variable

No longer needed as of last commit.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: drivers/dri: add $(mesa_top)/src to the includes list
Emil Velikov [Tue, 29 Jul 2014 00:21:34 +0000 (01:21 +0100)]
android: drivers/dri: add $(mesa_top)/src to the includes list

Will allow us to nuke an include or two from the drivers.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: dri: use the installed libdrm headers
Emil Velikov [Mon, 28 Jul 2014 23:27:32 +0000 (00:27 +0100)]
android: dri: use the installed libdrm headers

Saves us a few lines and brings us closer to the automake build.
Drop DRM_TOP as it's not longer used.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: gallium: use the installed libdrm headers
Emil Velikov [Mon, 28 Jul 2014 23:22:05 +0000 (00:22 +0100)]
android: gallium: use the installed libdrm headers

Saves us a few lines and brings us closer to the automake build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: loader: use the installed libdrm headers
Emil Velikov [Mon, 28 Jul 2014 23:18:11 +0000 (00:18 +0100)]
android: loader: use the installed libdrm headers

One step closer to the way we handle automake builds.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: egl/dri2: use the installed libdrm headers
Emil Velikov [Mon, 28 Jul 2014 23:16:01 +0000 (00:16 +0100)]
android: egl/dri2: use the installed libdrm headers

Trying to get rid of the hardcoded dependency of DRM_TOP which
expects that mesa is localted in /external/drm. Will

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: dri/i915: do not build an 'empty' driver
Emil Velikov [Mon, 28 Jul 2014 23:33:30 +0000 (00:33 +0100)]
android: dri/i915: do not build an 'empty' driver

The variable i915_C_FILES changed to i915_FILES with commit
34d4216e641 back in mesa 9.1/9.2. Yet we've missed to update the
the android build, essentially creating an dummy/empty driver that
can never work.

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoautomake: mesa: whitespace fixes
Emil Velikov [Fri, 1 Aug 2014 16:12:07 +0000 (17:12 +0100)]
automake: mesa: whitespace fixes

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agomesa: guard better when building with sse4.1 optimisations
Emil Velikov [Fri, 1 Aug 2014 16:06:10 +0000 (17:06 +0100)]
mesa: guard better when building with sse4.1 optimisations

When the compiler is not capable/does not accept -msse4.1 while the target
has the instruction set we'll blow up as _mesa_streaming_load_memcpy is
going to be undefined.

To make sure that never happens, wrap the runtime cpu check+caller in an
ifdef thus do not compile that hunk of the code.

Fix the android build by enabling the optimisation and adding the define
where applicable.

v2: autoconf conditionals end with "fi" rather than endif.
v3: Wrap the definition and call to intel_miptree_{un,}map_movntdqa in
if defined(USE_SSE41). Spotted by Matt.

Cc: Matt Turner <mattst88@gmail.com>
Cc: Adrian Negreanu <adrian.m.negreanu@intel.com>
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoandroid: glsl: the stlport over the limited Android STL
Emil Velikov [Mon, 28 Jul 2014 19:24:02 +0000 (20:24 +0100)]
android: glsl: the stlport over the limited Android STL

The latter lacks various functionality used by mesa/glsl.

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agoandroid: drop HAL_PIXEL_FORMAT_RGBA_{5551,4444}
Emil Velikov [Sun, 27 Jul 2014 02:27:08 +0000 (03:27 +0100)]
android: drop HAL_PIXEL_FORMAT_RGBA_{5551,4444}

Upstream Android (system/core) has dropped these formats with commit
6bac41f1bf9(get rid of HAL pixelformats 5551 and 4444) yet does not
mention why.

These formats never really worked so we're safe to drop them as well.

Identical commit is available in the android-x86 external/mesa repo

    commit 06a2d36edcd1e2247440e5800e6bf3028f37aee6
    Author: Chih-Wei Huang <cwhuang@linux.org.tw>
    Date:   Wed Sep 25 01:16:57 2013 +0800

        android: get rid of HAL pixelformats 5551 and 4444

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>