mesa.git
2 years agomeson: replace libmesa_util with idep_mesautil
Eric Engestrom [Mon, 22 Jul 2019 13:50:15 +0000 (14:50 +0100)]
meson: replace libmesa_util with idep_mesautil

This automates the include_directories and dependencies tracking so that
all users of libmesa_util don't need to add them manually.

Next commit will remove the ones that were only added for that reason.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Eric Anholt <eric@anholt.net>
Tested-by: Vinson Lee <vlee@freedesktop.org>
2 years agopan/midgard: Print texture outmod
Alyssa Rosenzweig [Fri, 2 Aug 2019 21:26:33 +0000 (14:26 -0700)]
pan/midgard: Print texture outmod

I have no idea who thought this was a good idea.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Promote all 16 uniforms
Alyssa Rosenzweig [Fri, 2 Aug 2019 15:46:44 +0000 (08:46 -0700)]
pan/midgard: Promote all 16 uniforms

Now that register spilling is in place, this is reasonable. It turns out
for some shaders, it's actually better to cap at 8 work registers and
extra >8 uniform reigsters and tolerate the spilling, since the extra
resulting threads make up for the spillage. So incidentally, the shader
that spills here is in -bterrain, which jumps from 19fps to 21fps as a
result of this change.

total instructions in shared programs: 3513 -> 3448 (-1.85%)
instructions in affected programs: 776 -> 711 (-8.38%)
helped: 20
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 3.25 x̃: 2
helped stats (rel) min: 3.57% max: 16.00% x̄: 8.37% x̃: 7.19%
95% mean confidence interval for instructions value: -4.28 -2.22
95% mean confidence interval for instructions %-change: -10.02% -6.73%
Instructions are helped.

total bundles in shared programs: 2067 -> 2024 (-2.08%)
bundles in affected programs: 515 -> 472 (-8.35%)
helped: 19
HURT: 1
helped stats (abs) min: 1 max: 6 x̄: 2.37 x̃: 2
helped stats (rel) min: 2.13% max: 17.86% x̄: 10.19% x̃: 11.11%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 3.23% max: 3.23% x̄: 3.23% x̃: 3.23%
95% mean confidence interval for bundles value: -3.01 -1.29
95% mean confidence interval for bundles %-change: -12.13% -6.91%
Bundles are helped.

total quadwords in shared programs: 3468 -> 3426 (-1.21%)
quadwords in affected programs: 764 -> 722 (-5.50%)
helped: 19
HURT: 1
helped stats (abs) min: 1 max: 5 x̄: 2.26 x̃: 2
helped stats (rel) min: 1.41% max: 12.50% x̄: 6.76% x̃: 7.14%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.08% max: 1.08% x̄: 1.08% x̃: 1.08%
95% mean confidence interval for quadwords value: -2.83 -1.37
95% mean confidence interval for quadwords %-change: -8.08% -4.65%
Quadwords are helped.

total registers in shared programs: 383 -> 360 (-6.01%)
registers in affected programs: 112 -> 89 (-20.54%)
helped: 19
HURT: 0
helped stats (abs) min: 1 max: 3 x̄: 1.21 x̃: 1
helped stats (rel) min: 12.50% max: 27.27% x̄: 20.63% x̃: 20.00%
95% mean confidence interval for registers value: -1.47 -0.95
95% mean confidence interval for registers %-change: -22.39% -18.87%
Registers are helped.

total threads in shared programs: 432 -> 451 (4.40%)
threads in affected programs: 19 -> 38 (100.00%)
helped: 11
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.73 x̃: 2
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for threads value: 1.41 2.04
95% mean confidence interval for threads %-change: 100.00% 100.00%
Threads are [helped].

total loops in shared programs: 4 -> 4 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 0 -> 4
spills in affected programs: 0 -> 4
helped: 0
HURT: 2

total fills in shared programs: 0 -> 7
fills in affected programs: 0 -> 7
helped: 0
HURT: 2

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Break mir_spill_register into its function
Alyssa Rosenzweig [Fri, 2 Aug 2019 16:06:13 +0000 (09:06 -0700)]
pan/midgard: Break mir_spill_register into its function

No functional changes, just breaks out a megamonster function and fixes
the indentation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Switch sources to an array for trinary sources
Alyssa Rosenzweig [Fri, 2 Aug 2019 22:25:02 +0000 (15:25 -0700)]
pan/midgard: Switch sources to an array for trinary sources

We need three independent sources to support indirect SSBO writes (as
well as textures with both LOD/bias and offsets). Now is a good time to
make sources just an array so we don't have to rewrite a ton of code if
we ever needed a fourth source for some reason.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Remove "r27-only" register class
Alyssa Rosenzweig [Thu, 1 Aug 2019 21:28:34 +0000 (14:28 -0700)]
pan/midgard: Remove "r27-only" register class

As far as I know, there's no such thing as a load/store op that only
takes its argument in r27. We just need to set the appropriate arg_1
field in the RA to specify other registers if we want them.

To facilitate this, various RA-related changes are needed across the
compiler ; this should also fix indirect offsets which were implicitly
interpreted as "r27-only" despite not even passing through RA yet. One
ripple effect change is switching the move insertion point and adjusting
the liveness analysis accordingly, so while this was intended as a
purely functional change, there are some shader-db changes:

total instructions in shared programs: 3511 -> 3498 (-0.37%)
instructions in affected programs: 563 -> 550 (-2.31%)
helped: 12
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.08 x̃: 1
helped stats (rel) min: 0.93% max: 5.00% x̄: 2.58% x̃: 2.33%
95% mean confidence interval for instructions value: -1.27 -0.90
95% mean confidence interval for instructions %-change: -3.23% -1.93%
Instructions are helped.

total bundles in shared programs: 2067 -> 2067 (0.00%)
bundles in affected programs: 398 -> 398 (0.00%)
helped: 7
HURT: 4
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.54% max: 10.00% x̄: 5.04% x̃: 5.56%
HURT stats (abs)   min: 1 max: 2 x̄: 1.75 x̃: 2
HURT stats (rel)   min: 2.13% max: 4.26% x̄: 3.72% x̃: 4.26%
95% mean confidence interval for bundles value: -0.95 0.95
95% mean confidence interval for bundles %-change: -5.21% 1.50%
Inconclusive result (value mean confidence interval includes 0).

total quadwords in shared programs: 3464 -> 3454 (-0.29%)
quadwords in affected programs: 1199 -> 1189 (-0.83%)
helped: 18
HURT: 4
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.03% max: 5.26% x̄: 2.44% x̃: 1.79%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 2.56% max: 2.82% x̄: 2.63% x̃: 2.56%
95% mean confidence interval for quadwords value: -0.98 0.07
Inconclusive result (value mean confidence interval includes 0).

total registers in shared programs: 383 -> 373 (-2.61%)
registers in affected programs: 56 -> 46 (-17.86%)
helped: 12
HURT: 2
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 9.09% max: 33.33% x̄: 29.58% x̃: 33.33%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 20.00% max: 50.00% x̄: 35.00% x̃: 35.00%
95% mean confidence interval for registers value: -1.13 -0.29
95% mean confidence interval for registers %-change: -35.07% -5.63%
Registers are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Handle get/set_swizzle for load/store arguments
Alyssa Rosenzweig [Fri, 2 Aug 2019 18:22:56 +0000 (11:22 -0700)]
pan/midgard: Handle get/set_swizzle for load/store arguments

Load/store's  main "argument 0" already has its swizzle handled
correctly (for stores, that is). But the tinier arguments, the compact
ones with a component select but not a full swizzle, those are not yet
handled. Let's do something about that!

2 years agopan/midgard: Fix block successors
Alyssa Rosenzweig [Fri, 2 Aug 2019 20:48:27 +0000 (13:48 -0700)]
pan/midgard: Fix block successors

Rather than an ersatz thing that sort of looks like successors but is in
fact just the source order traversal with some backward jumps hacked in
for loops... construct an actual flow graph so we can do analysis
sanely.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add helper to pack load/store registers
Alyssa Rosenzweig [Thu, 1 Aug 2019 21:14:43 +0000 (14:14 -0700)]
pan/midgard: Add helper to pack load/store registers

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Decode register/component in load/store argument
Alyssa Rosenzweig [Thu, 1 Aug 2019 21:06:19 +0000 (14:06 -0700)]
pan/midgard: Decode register/component in load/store argument

3-bits out of 8 down!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Fix REGISTER_OFFSET
Alyssa Rosenzweig [Thu, 1 Aug 2019 21:06:02 +0000 (14:06 -0700)]
pan/midgard: Fix REGISTER_OFFSET

r27 isn't the special one, usually.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Split ld/st unknown to arg_1/arg_2 fields
Alyssa Rosenzweig [Thu, 1 Aug 2019 20:29:01 +0000 (13:29 -0700)]
pan/midgard: Split ld/st unknown to arg_1/arg_2 fields

The 16-bit field can be decomposed to two independent 8-bit fields, each
representing a single (additional) argument to the load/store op,
generally used for encoding registers. Addressable registers here are
substantially limited compared to the main register in a load/store op.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agoradv: Expose VK_KHR_imageless_framebuffer.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 12:45:49 +0000 (14:45 +0200)]
radv: Expose VK_KHR_imageless_framebuffer.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv: Implement VK_KHR_imageless_framebuffer.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 12:42:50 +0000 (14:42 +0200)]
radv: Implement VK_KHR_imageless_framebuffer.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv: Store image view also outside framebuffer.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 13:22:37 +0000 (15:22 +0200)]
radv: Store image view also outside framebuffer.

So we can use it with imageless framebuffers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoradv: Store color/depth surface info in attachment info instead of framebuffer.
Bas Nieuwenhuizen [Mon, 22 Jul 2019 00:31:27 +0000 (02:31 +0200)]
radv: Store color/depth surface info in attachment info instead of framebuffer.

That way we can use it for imageless framebuffers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agopanfrost: Allocate polygon lists on-demand
Alyssa Rosenzweig [Fri, 2 Aug 2019 17:18:48 +0000 (19:18 +0200)]
panfrost: Allocate polygon lists on-demand

Rather than alloacting a huge (64MB) polygon list on context creation
and sharing it across framebuffers, we instead allocate polygon lists as
BOs (which consistently hit the cache) sized appropriately; for about a
month, we've known how to calculate the polygon list size so this has
only recently become possible.

The good news is we can render to truly massive framebuffers without
crashing and, more importantly, we eliminate the 64MB upfront overhead.
If a list that size isn't actually needed, it's not allocated.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2 years agopanfrost: Handle the bo == NULL case in panfrost_bo_[un]reference()
Boris Brezillon [Fri, 2 Aug 2019 17:18:47 +0000 (19:18 +0200)]
panfrost: Handle the bo == NULL case in panfrost_bo_[un]reference()

Allows us to pass BOs without checking if they're NULL or not.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Get rid of the skippable param in attach_vt_framebuffer()
Boris Brezillon [Fri, 2 Aug 2019 17:18:46 +0000 (19:18 +0200)]
panfrost: Get rid of the skippable param in attach_vt_framebuffer()

The only user of this function always passes true.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Don't emit a new FB desc when setting a new FB state
Boris Brezillon [Fri, 2 Aug 2019 17:18:45 +0000 (19:18 +0200)]
panfrost: Don't emit a new FB desc when setting a new FB state

The FB desc will be emitted/attached on the first draw targetting
this new FB.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Bail out early when doing a wallpaper blit
Boris Brezillon [Fri, 2 Aug 2019 17:18:44 +0000 (19:18 +0200)]
panfrost: Bail out early when doing a wallpaper blit

The wallpaper blit is a bit special in that the operation is targetting
the current FB, but the u_blitter logic creates a new surface for it
which makes util_framebuffer_state_equal() return false. In that case
we don't want a new FB descriptor to be emitted/attached, so let's just
copy the new state into ctx->pipe_framebuffer and exit the function.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Bail out early when new and current FB states are equal
Boris Brezillon [Fri, 2 Aug 2019 17:18:43 +0000 (19:18 +0200)]
panfrost: Bail out early when new and current FB states are equal

If the current FB matches the new one there's nothing to be done in
panfrost_set_framebuffer_state(). By bailing out early in that case we
avoid emitting new FB descriptors (the old ones are still valid).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Delay FB descriptor allocation
Boris Brezillon [Fri, 2 Aug 2019 17:18:42 +0000 (19:18 +0200)]
panfrost: Delay FB descriptor allocation

No need to emit SFBD/MFBD at frame invalidation. They can be emitted
when the framebuffer is attached, which saves us a potential FB desc
re-allocation if a new FB is bound after the swap.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Remove job from ctx->jobs at submission time
Boris Brezillon [Fri, 2 Aug 2019 17:18:41 +0000 (19:18 +0200)]
panfrost: Remove job from ctx->jobs at submission time

This guarantees that new draws targetting the same framebuffer will
get a new job instance.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Make ctx->job useful
Boris Brezillon [Fri, 2 Aug 2019 17:18:40 +0000 (19:18 +0200)]
panfrost: Make ctx->job useful

ctx->job is supposed to serve as a cache to avoid an hash table lookup
everytime we access the job attached to the currently bound FB, except
it was never assigned to anything but NULL.

Fix that by adding the missing assignment in panfrost_get_job_for_fbo().
Also add a missing NULL assignment in the ->set_framebuffer_state()
path.

While at it, add extra assert()s to make sure ctx->job is consistent.

Fixes: 59c9623d0a75 ("panfrost: Import job data structures from v3d")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agoac/nir,radv: Optimize bounds check for 64 bit CAS.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 10:40:17 +0000 (12:40 +0200)]
ac/nir,radv: Optimize bounds check for 64 bit CAS.

When the application does not ask for robust buffer access.

Only implemented the check in radv.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agogallivm: fix issue with AtomicCmpXchg wrapper on llvm 3.5-3.8
Roland Scheidegger [Tue, 30 Jul 2019 21:35:49 +0000 (23:35 +0200)]
gallivm: fix issue with AtomicCmpXchg wrapper on llvm 3.5-3.8

These versions still need wrapper but already have both success and
failure ordering.
(Compile tested on llvm 3.3, 3.7, 3.8.)

v2: don't duplicate whole function (suggested by Brian).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111102

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2 years agoutil: Handle differences in pthread_setname_np
Matt Turner [Wed, 31 Jul 2019 21:44:39 +0000 (14:44 -0700)]
util: Handle differences in pthread_setname_np

There are a lot of unfortunate differences in the implementation of this
function. NetBSD and Mac OS X in particular require different arguments.

https://stackoverflow.com/questions/2369738/how-to-set-the-name-of-a-thread-in-linux-pthreads/7989973#7989973
provides for a good overview of the differences.

Fixes: 9c411e020d1 ("util: Drop preprocessor guards for glibc-2.12")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111264
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
[Eric: use DETECT_OS_* instead of PIPE_OS_*]
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoutil/os_time: use detect_os.h to uncouple from gallium
Eric Engestrom [Thu, 1 Aug 2019 21:38:00 +0000 (22:38 +0100)]
util/os_time: use detect_os.h to uncouple from gallium

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoutil/u_debug: use detect_os.h
Eric Engestrom [Thu, 1 Aug 2019 21:36:30 +0000 (22:36 +0100)]
util/u_debug: use detect_os.h

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoutil/os_misc: use detect_os.h to start uncoupling from gallium
Eric Engestrom [Thu, 1 Aug 2019 21:33:05 +0000 (22:33 +0100)]
util/os_misc: use detect_os.h to start uncoupling from gallium

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoutil/os_memory: use detect_os.h to uncouple it from gallium
Eric Engestrom [Thu, 1 Aug 2019 15:55:39 +0000 (16:55 +0100)]
util/os_memory: use detect_os.h to uncouple it from gallium

While at it, remove p_compiler.h as well as it is unused.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agogallium: deduplicate os detection logic by using detect_os.h
Eric Engestrom [Thu, 1 Aug 2019 13:58:52 +0000 (14:58 +0100)]
gallium: deduplicate os detection logic by using detect_os.h

This allows us to avoid having to rename all the PIPE_OS_* at once while
still making sure PIPE_OS_* and DETECT_OS_* are always in sync.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agogallium/utils: drop PIPE_SUBSYSTEM_WINDOWS_USER
Eric Engestrom [Thu, 1 Aug 2019 21:49:05 +0000 (22:49 +0100)]
gallium/utils: drop PIPE_SUBSYSTEM_WINDOWS_USER

This is basically just an alias for PIPE_OS_WINDOWS.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoscons: rename PIPE_SUBSYSTEM_EMBEDDED to EMBEDDED_DEVICE
Eric Engestrom [Thu, 1 Aug 2019 20:45:25 +0000 (21:45 +0100)]
scons: rename PIPE_SUBSYSTEM_EMBEDDED to EMBEDDED_DEVICE

It has nothing to do with the PIPE_SUBSYSTEM_* stuff from gallium.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agogallium: remove never-used PIPE_SUBSYSTEM_DRI
Eric Engestrom [Thu, 1 Aug 2019 14:02:15 +0000 (15:02 +0100)]
gallium: remove never-used PIPE_SUBSYSTEM_DRI

PIPE_SUBSYSTEM_DRI was introduced in dacfef158943665fc0d1 ("gallium: New
configuration header.") 11 years ago, and was never used.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoutil: fix typo in comment
Eric Engestrom [Thu, 1 Aug 2019 14:01:54 +0000 (15:01 +0100)]
util: fix typo in comment

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agoutil: introduce detect_os.h
Eric Engestrom [Thu, 1 Aug 2019 13:48:26 +0000 (14:48 +0100)]
util: introduce detect_os.h

Mostly copied from src/gallium/include/pipe/p_config.h, so I kept its
copyright and authorship.

Other than the obvious rename, the big difference is that these are
always defined, to be used as `#if DETECT_OS_LINUX`.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agofreedreno/batch: fix dependency loop detection
Rob Clark [Wed, 31 Jul 2019 19:30:24 +0000 (12:30 -0700)]
freedreno/batch: fix dependency loop detection

We can have a scenario like:

  A -> B
  A -> C -> B

When adding the A->C dependency, it doesn't really matter that C depends
on something that A depends on, that isn't a necessary condition for a
dependency loop.

Instead what we want to know is that nothing C depends on, directly or
indirectly, depends on A.  We can detect this by recursively OR'ing the
dependents_mask of C and all it's dependencies.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: add missing flush/invalidates for blit
Rob Clark [Tue, 30 Jul 2019 16:34:53 +0000 (09:34 -0700)]
freedreno/a6xx: add missing flush/invalidates for blit

Various things we were missing for multiple blits in a single batch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/a6xx: skip tiles with no geometry
Rob Clark [Sat, 27 Jul 2019 16:00:37 +0000 (09:00 -0700)]
freedreno/a6xx: skip tiles with no geometry

If no clear, and no geometry according to VSC_STATE[pipe] we can skip
the tile entirely.  If there is a fast-clear, we can't skip restore
(clear) or resolve IBs, but we can still skip draw IB.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a6xx: VSC overflow detection/handling
Rob Clark [Fri, 26 Jul 2019 16:55:14 +0000 (09:55 -0700)]
freedreno/a6xx: VSC overflow detection/handling

Check VSC_SIZE/VSC_SIZE2 regs from cmdstream to detect overflow, and
skip use of VSC visibility stream when overflow is detected, to avoid
GPU hangs.  This is done w/ introduction of some CP_REG_TEST/
CP_COND_REG_EXEC packet pairs.

In addition, eventually (after a frame or two) detect the condition and
resize the VSC buffers until overflow no longer happens.

Note that this significantly reduces the initial size of the VSC
buffers, backing out a previous hack to make them 16x larger than
what should be typically required (the previous "solution" for
VSC overflow).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a6xx: remove USE/IGNORE_VISIBILITY draw patching
Rob Clark [Fri, 26 Jul 2019 16:05:58 +0000 (09:05 -0700)]
freedreno/a6xx: remove USE/IGNORE_VISIBILITY draw patching

Seems this isn't needed anymore on a6xx to control whether visibility
stream is used.  And it would be hard to deal with if it was, for
disabling use of VSC stream in draw pass.  So just remove it and
simplify things.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/a6xx: cleanup "blit_mem"
Rob Clark [Thu, 25 Jul 2019 23:34:25 +0000 (16:34 -0700)]
freedreno/a6xx: cleanup "blit_mem"

Rename to "control_mem", and switch to using a struct to manage the
layout, rather than just ad-hoc hard-coded offsets.

For recovering from VSC stream overflow, we'll need to add more, but
best to clean it up first.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno: refresh tile debug
Rob Clark [Wed, 24 Jul 2019 21:28:10 +0000 (14:28 -0700)]
freedreno: refresh tile debug

Fix some #ifdef'd bitrot, and get rid of #ifdef so it doesn't bitrot
again.

And add a prints for per-tile state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno: update registers
Rob Clark [Thu, 25 Jul 2019 22:25:22 +0000 (15:25 -0700)]
freedreno: update registers

Pull in some updates of VSC regs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/gmem: small cleanup
Rob Clark [Thu, 25 Jul 2019 20:40:02 +0000 (13:40 -0700)]
freedreno/gmem: small cleanup

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno/drm: convert ring_pool to child_pool
Rob Clark [Mon, 29 Jul 2019 18:48:06 +0000 (11:48 -0700)]
freedreno/drm: convert ring_pool to child_pool

Worth another couple percent at driver2

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/drm: remove idx_lock
Rob Clark [Mon, 29 Jul 2019 17:27:18 +0000 (10:27 -0700)]
freedreno/drm: remove idx_lock

Since it ends up contended, it is a bit of a bottleneck for workloads
with high driver overhead.  Worth nearly +10% at gfxbench driver2.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno/batch: always update last_fence
Rob Clark [Sun, 28 Jul 2019 17:04:25 +0000 (10:04 -0700)]
freedreno/batch: always update last_fence

Not all flush paths come thru fd_context_flush(), so we should also set
last_fence in the batch flush path.  This avoids some no-op flushes just
to get a fence.  For example when pctx->flush_resource() triggers a
flush.

We should probably keep the last_fence update in fd_context_flush() as
well to handle deferred flush case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agofreedreno: drop unused fd_fence_ref param
Rob Clark [Tue, 30 Jul 2019 15:12:46 +0000 (08:12 -0700)]
freedreno: drop unused fd_fence_ref param

The pscreen param was just there to satisfy pipe_screen::fence_reference

But some of the internal uses passed NULL for screen.  Which is a bit
ugly.  Instead drop the param and add a shim function to plug into the
screen.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agopan/midgard: Print invert modifier
Alyssa Rosenzweig [Fri, 26 Jul 2019 21:59:00 +0000 (14:59 -0700)]
pan/midgard: Print invert modifier

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Flip conditionals
Alyssa Rosenzweig [Fri, 26 Jul 2019 21:25:25 +0000 (14:25 -0700)]
pan/midgard: Flip conditionals

We would like to flip ops to have a constant in the second place to
enable inlining of the constant.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add bitwise src/invert fusing
Alyssa Rosenzweig [Fri, 26 Jul 2019 20:32:54 +0000 (13:32 -0700)]
pan/midgard: Add bitwise src/invert fusing

De Morgan's Laws and some special ops basically.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Add .not propagation pass
Alyssa Rosenzweig [Fri, 26 Jul 2019 20:14:55 +0000 (13:14 -0700)]
pan/midgard: Add .not propagation pass

Essentially .pos propagation but for bitwise.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Fuse invert into bitwise ops
Alyssa Rosenzweig [Fri, 26 Jul 2019 20:08:54 +0000 (13:08 -0700)]
pan/midgard: Fuse invert into bitwise ops

We use the new invert flag to produce ops like inand.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agofreedreno: a2xx: implement texture tiling
Jonathan Marek [Thu, 1 Aug 2019 18:41:44 +0000 (14:41 -0400)]
freedreno: a2xx: implement texture tiling

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: a2xx: use nir_lower_alu_to_scalar instead of lowering pass
Jonathan Marek [Thu, 1 Aug 2019 19:52:58 +0000 (15:52 -0400)]
freedreno: a2xx: use nir_lower_alu_to_scalar instead of lowering pass

nir_lower_alu_to_scalar can now be used to only lower certain ops, so we
don't need the custom pass. And we can lower fall_equal/fany_nequal with
lower_vector_cmp instead.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: a2xx: fix HW binning for batches with >256K vertices
Jonathan Marek [Thu, 1 Aug 2019 19:22:47 +0000 (15:22 -0400)]
freedreno: a2xx: fix HW binning for batches with >256K vertices

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: a2xx: fix fneg/fabs/fsat opcodes
Jonathan Marek [Thu, 1 Aug 2019 18:43:12 +0000 (14:43 -0400)]
freedreno: a2xx: fix fneg/fabs/fsat opcodes

Previously we would get a fmov with modifiers, but now that mov has no type
these opcodes need to be supported.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: a2xx: fix order of NIR opts
Jonathan Marek [Thu, 1 Aug 2019 18:38:18 +0000 (14:38 -0400)]
freedreno: a2xx: fix order of NIR opts

int_to_float needs to come after bool_to_float, and lower_to_source_mods
needs to come after both, since they don't deal wih source mods.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: a2xx: fix non-etc1 cubemaps
Jonathan Marek [Thu, 1 Aug 2019 18:36:41 +0000 (14:36 -0400)]
freedreno: a2xx: fix non-etc1 cubemaps

Not sure how this happened, but apparently all cubemaps need swapped XY.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: a2xx: fix fast clear not being used for Z24X8 buffers
Jonathan Marek [Thu, 1 Aug 2019 16:50:03 +0000 (12:50 -0400)]
freedreno: a2xx: fix fast clear not being used for Z24X8 buffers

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agofreedreno: align renderonly scanout buffers
Jonathan Marek [Thu, 1 Aug 2019 16:42:33 +0000 (12:42 -0400)]
freedreno: align renderonly scanout buffers

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2 years agogitlab-ci: just build all the tools
Eric Engestrom [Thu, 1 Aug 2019 22:32:34 +0000 (23:32 +0100)]
gitlab-ci: just build all the tools

This line was mistakenly added while there is already a `-D tools=all`
a few lines below.

Fixes: f60defa72d5d20d99e3a ("gitlab-ci: Add a shader-db run using v3d on drm-shim.")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2 years agoi965/clear: clear_value better precision
Sergii Romantsov [Fri, 12 Jul 2019 13:46:45 +0000 (16:46 +0300)]
i965/clear: clear_value better precision

Test-case with depth-clear 0.5 and format
MESA_FORMAT_Z24_UNORM_X8_UINT fails due inconsistent
clear-value of 0.4999997.
Maybe its better to improve?

CC: Jason Ekstrand <jason.ekstrand@intel.com>
Fixes: 0ae9ce0f29ea (i965/clear: Quantize the depth clear value based on the format)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111113
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2 years agoradv: fix image_has_{cmask,fmask}() helpers
Samuel Pitoiset [Fri, 2 Aug 2019 11:55:01 +0000 (13:55 +0200)]
radv: fix image_has_{cmask,fmask}() helpers

The driver should now rely on cmask_offset because CMASK can be
disabled by the driver for some reasons (eg. mipmaps). Apply the
same change for FMASK, although it should be useless.

Fixes: ad1bc8621df ("radv: remove radv_get_image_fmask_info()")
Fixes: 10d08da52c6 ("radv/gfx10: add missing dcc_tile_swizzle tweak")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: remove radv_get_image_fmask_info()
Samuel Pitoiset [Thu, 1 Aug 2019 15:59:56 +0000 (17:59 +0200)]
radv: remove radv_get_image_fmask_info()

It's unnecessary to duplicate fields in another struct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: add missing dcc_tile_swizzle tweak
Samuel Pitoiset [Thu, 1 Aug 2019 13:45:11 +0000 (15:45 +0200)]
radv/gfx10: add missing dcc_tile_swizzle tweak

Fixes: c90f46700dd ("radv/gfx10: mask DCC tile swizzle by alignment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: remove radv_get_image_cmask_info()
Samuel Pitoiset [Thu, 1 Aug 2019 15:59:55 +0000 (17:59 +0200)]
radv: remove radv_get_image_cmask_info()

It's unnecessary to duplicate fields in another struct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: only account for tile_swizzle for color surfaces with DCC
Samuel Pitoiset [Thu, 1 Aug 2019 13:45:10 +0000 (15:45 +0200)]
radv: only account for tile_swizzle for color surfaces with DCC

It's 0 for depth surfaces with TC compat HTILE enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv: Enable VK_KHR_shader_atomic_int64
Bas Nieuwenhuizen [Fri, 2 Aug 2019 00:16:23 +0000 (02:16 +0200)]
radv: Enable VK_KHR_shader_atomic_int64

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoac/nir: Implement LLVM9 64-bit buffer compare & exchange.
Bas Nieuwenhuizen [Fri, 2 Aug 2019 10:01:34 +0000 (12:01 +0200)]
ac/nir: Implement LLVM9 64-bit buffer compare & exchange.

LLVM 9 does not have a 64-bit buffer compswap intrinsic, so this
extracts the ptr, does a bound check and then uses a cmpxchg LLVM
instruction.

Not ideal, but the earliest release we're going to get a proper
intrinsic is LLVM 10.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2 years agoRevert "ac/nir: handle negate modifier"
Connor Abbott [Fri, 2 Aug 2019 09:14:50 +0000 (11:14 +0200)]
Revert "ac/nir: handle negate modifier"

This reverts commit bfea7e4d2965269bff8f1f6449cb99c312fd7384.

2 years agoRevert "ac/nir: handle abs modifier"
Connor Abbott [Fri, 2 Aug 2019 09:14:08 +0000 (11:14 +0200)]
Revert "ac/nir: handle abs modifier"

This reverts commit d3c80733cdfe8552b2f447ec8ed62465d0f2af1a.

These were only appearing due to memory corruption.

2 years agoiris: bump compat profile support to 4.6
Timothy Arceri [Fri, 28 Jun 2019 04:55:20 +0000 (14:55 +1000)]
iris: bump compat profile support to 4.6

All of the current piglit compat profile tests pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agoegl: fix OpenGL 3.1 context creation
Timothy Arceri [Fri, 2 Aug 2019 01:38:45 +0000 (11:38 +1000)]
egl: fix OpenGL 3.1 context creation

>From the EGL_KHR_create_context spec:

   "* If OpenGL 3.1 is requested, the context returned may implement
       any of the following versions:

         * Version 3.1. The GL_ARB_compatibility extension may or may
           not be implemented, as determined by the implementation.
         * The core profile of version 3.2 or greater."

Fixes CTS tests:

    dEQP-EGL.functional.create_context_ext.gl_31.rgb888_depth_stencil
    dEQP-EGL.functional.create_context_ext.robust_gl_31.rgb888_depth_stencil
    dEQP-EGL.functional.create_context_ext.gl_31.rgb888_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.robust_gl_31.rgb888_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.gl_31.rgba8888_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.gl_31.rgb888_no_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.robust_gl_31.rgba8888_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.robust_gl_31.rgb888_no_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.gl_31.rgba8888_no_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.robust_gl_31.rgba8888_no_depth_no_stencil
    dEQP-EGL.functional.create_context_ext.gl_31.rgba8888_depth_stencil
    dEQP-EGL.functional.create_context_ext.robust_gl_31.rgba8888_depth_stencil

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2 years agonir/find_array_copies: Reject copies with mismatched type
Connor Abbott [Wed, 31 Jul 2019 09:32:30 +0000 (11:32 +0200)]
nir/find_array_copies: Reject copies with mismatched type

When we detect a scalar/vector copy through load_deref/store_deref, we
have to be careful since those can bitcast an int to a float and
vice-versa even though copy_deref can't.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111251
Fixes: 156306e5e62 ("nir/find_array_copies: Handle wildcards and overlapping copies")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agoradv: re-apply "Optimize rebinding the same descriptor set."
Samuel Pitoiset [Fri, 2 Aug 2019 07:56:32 +0000 (09:56 +0200)]
radv: re-apply "Optimize rebinding the same descriptor set."

This makes it cheaper to just change the dynamic offsets with
the same descriptor sets.

This optimization has been reverted a while back because of
random GPU hangs on GFX9, no it looks fine, at least CTS no longer
hangs on GFX9 and it doesn't hang on GFX10 as well.

It fixes a performance problem with Wolfenstein Youngblood.

Suggested-by: Philip Rebohle <philip.rebohle@tu-dortmund.de>
2 years agoradv/gfx10: use the correct target machine for Wave32
Samuel Pitoiset [Thu, 1 Aug 2019 08:43:44 +0000 (10:43 +0200)]
radv/gfx10: use the correct target machine for Wave32

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders
Samuel Pitoiset [Thu, 1 Aug 2019 08:43:42 +0000 (10:43 +0200)]
radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders

It can be enabled with RADV_PERFTEST=gewave32.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agoradv/gfx10: add Wave32 support for fragment shaders
Samuel Pitoiset [Thu, 1 Aug 2019 08:43:41 +0000 (10:43 +0200)]
radv/gfx10: add Wave32 support for fragment shaders

It can be enabled with RADV_PERFTEST=pswave32.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2 years agogallium: Implement GL_EXT_shader_samples_identical via a new capability
Kenneth Graunke [Wed, 31 Jul 2019 22:47:34 +0000 (15:47 -0700)]
gallium: Implement GL_EXT_shader_samples_identical via a new capability

This exposes the textureSamplesIdenticalEXT function in GLSL.

We enable it for iris and radeonsi, because their compilers already
have support for this.  Tested on Intel Kabylake and AMD Vega 64.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2 years agointel/tools: Fix aubinator_viewer build.
Kenneth Graunke [Fri, 2 Aug 2019 06:36:41 +0000 (23:36 -0700)]
intel/tools: Fix aubinator_viewer build.

This functions was recently renamed and not all callers were updated.

Fixes: 086c486a75f ("intel/device: rename gen_get_device_info")
2 years agointel/ir: Fix CFG corruption in opt_predicated_break().
Francisco Jerez [Tue, 23 Jul 2019 23:17:07 +0000 (16:17 -0700)]
intel/ir: Fix CFG corruption in opt_predicated_break().

Specifically the optimization of a conditional BREAK + WHILE sequence
into a conditional WHILE seems pretty broken.  The list of successors
of "earlier_block" (where the conditional BREAK was found) is emptied
and then re-created with the same edges for no apparent reason.  On
top of that the list of predecessors of the block immediately after
the WHILE loop is emptied, but only one of the original edges will be
added back, which means that potentially several blocks that still
have it on their list of successors won't be on its list of
predecessors anymore, causing all sorts of hilarity due to the
inconsistency in the control flow graph.

The solution is to remove the code that's removing valid edges from
the CFG.  cfg_t::remove_block() will already clean up after itself.
The assert in bblock_t::combine_with() also needs to be removed since
we will be merging a block with multiple children into the first one
of them.

Found the issue on a hardware enabling branch originally, but
apparently somebody reproduced the same problem independently on
master in the meantime.

Fixes: d13bcdb3a9f ("i965/fs: Extend predicated break pass to predicate WHILE.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111009
Cc: jiradet.jd@gmail.com
Cc: Sergii Romantsov <sergii.romantsov@globallogic.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Paul Chelombitko <qamonstergl@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2 years agointel/device: make internal functions private
Mark Janes [Tue, 30 Jul 2019 00:38:42 +0000 (17:38 -0700)]
intel/device: make internal functions private

The device info initializer makes several fuctions internal:

  - handling of device override
  - updating topology from kernel information

The implementation file is slightly reordered due to the renamed
functions being static.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/device: rename gen_get_device_info
Mark Janes [Thu, 25 Jul 2019 22:57:30 +0000 (15:57 -0700)]
intel/device: rename gen_get_device_info

Rename the original device info initialization routine so callers
don't mistakenly call the wrong one:

  gen_get_device_info_from_fd:

      Queries kernel for full device info, including topology
      details.

  gen_get_device_info_from_pci_id:

      Partially initializes device info based on PCI ID lookup, when
      the kernel is not available.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/tools: use device info initializer
Mark Janes [Thu, 25 Jul 2019 21:31:40 +0000 (14:31 -0700)]
intel/tools: use device info initializer

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoanv: use initialization routine for gen_device_info
Mark Janes [Thu, 25 Jul 2019 17:40:55 +0000 (10:40 -0700)]
anv: use initialization routine for gen_device_info

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoiris/screen: use initialization routine for gen_device_info
Mark Janes [Wed, 24 Jul 2019 22:21:36 +0000 (15:21 -0700)]
iris/screen: use initialization routine for gen_device_info

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoi965: Move device info initialization to common code
Mark Janes [Wed, 24 Jul 2019 20:48:03 +0000 (13:48 -0700)]
i965: Move device info initialization to common code

With perf queries, initializing the device info is much more complex
than just getting a PCI ID and calling gen_get_device_info.  This commit
adds a new gen_get_device_info_from_fd helper in common code which does
all of the requisite kernel queries to get device info including all of
the topology information.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agoi965/perf: verify kernel support before registering OA metrics
Mark Janes [Wed, 31 Jul 2019 23:16:50 +0000 (16:16 -0700)]
i965/perf: verify kernel support before registering OA metrics

When gen_device_info updates the topology in it's initializer, the
kernel queries will fail silently.  Iris and anv have minimum
kernel requirements that support the queries.  i965 must verify kernel
support before reporting OA metrics.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agointel/common: provide common ioctl routine
Mark Janes [Thu, 25 Jul 2019 17:50:36 +0000 (10:50 -0700)]
intel/common: provide common ioctl routine

i965 links against libdrm for drmIoctl, but anv and iris both
re-implement this routine to avoid the dependency.

intel/dev also needs an ioctl wrapper, so lets share the same
implementation everywhere.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2 years agopanfrost: Remove unused argument
Alyssa Rosenzweig [Thu, 1 Aug 2019 15:10:03 +0000 (08:10 -0700)]
panfrost: Remove unused argument

A relic from when we didn't have an online compiler, hah.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Handle MESA_SHADER_COMPUTE in compile callback
Alyssa Rosenzweig [Wed, 31 Jul 2019 22:52:04 +0000 (15:52 -0700)]
panfrost: Handle MESA_SHADER_COMPUTE in compile callback

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopan/midgard: Use standard list traversal to find initial tag
Alyssa Rosenzweig [Wed, 31 Jul 2019 22:49:30 +0000 (15:49 -0700)]
pan/midgard: Use standard list traversal to find initial tag

Fixes a hang (and abort) on empty shaders, which you shouldn't have
anyway but better safe than sorry. DCE going on the fritz is no reason
to freeze the system.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Use gl_shader_stage directly for compiles
Alyssa Rosenzweig [Wed, 31 Jul 2019 22:49:13 +0000 (15:49 -0700)]
panfrost: Use gl_shader_stage directly for compiles

No need to add a third set of enums to the mix.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Emit "draw" info for compute jobs
Alyssa Rosenzweig [Wed, 31 Jul 2019 22:32:18 +0000 (15:32 -0700)]
panfrost: Emit "draw" info for compute jobs

Important fields relating to shader state and UBOs are filled out from
this (misnomer) function.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Feed compute shaders into the compiler
Alyssa Rosenzweig [Wed, 31 Jul 2019 22:31:23 +0000 (15:31 -0700)]
panfrost: Feed compute shaders into the compiler

The path for compute shader compiles resembles the graphic shader
compile path, although it is substantially simpler as we don't need any
shader keying.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2 years agopanfrost: Expose compute shaders as panfrost_shader_variants
Alyssa Rosenzweig [Wed, 31 Jul 2019 22:20:00 +0000 (15:20 -0700)]
panfrost: Expose compute shaders as panfrost_shader_variants

Whether variants are packed by graphics or compute is irrelevant.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>