mesa.git
21 months agoetnaviv: drm: Don't miscalculate timeout
Guido Günther [Wed, 22 Jan 2020 10:43:11 +0000 (11:43 +0100)]
etnaviv: drm: Don't miscalculate timeout

The current code overflows (s * 1000000000) for s >= 5 but that is
e.g. used in etna_bo_cpu_prep.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>

21 months agoegl: Fix _eglPointerIsDereferencable w/o mincore()
Alexander van der Grinten [Sun, 15 Dec 2019 10:25:37 +0000 (11:25 +0100)]
egl: Fix _eglPointerIsDereferencable w/o mincore()

On platforms without mincore(), _eglPointerIsDereferencable()
currently just checks whether p != NULL. This is not sufficient:
In the Wayland platform code (i.e., in get_wl_surface_proxy()),
_eglPointerIsDereferencable() is called on the version field
of `struct wl_egl_window` which is 3 on current versions of
Wayland. This causes a segfault when trying to dereference p.

Fix this behavior by assuming that the first page of the
process is never dereferencable.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>

21 months agoegl/android: fix buffer_count for applications setting max count
Tapani Pälli [Tue, 21 Jan 2020 11:01:51 +0000 (13:01 +0200)]
egl/android: fix buffer_count for applications setting max count

Problem with previous solution was that it did not take account that
some applications may set a max count for buffers. Therefore we need to
query both min and max and clamp our setting based on that.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2373
Fixes: be08e6a4496 ("egl/android: Restrict minimum triple buffering for android color_buffers")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3480>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3480>

21 months agoaco: Fix signedness compare warning.
Timur Kristóf [Tue, 21 Jan 2020 14:34:23 +0000 (15:34 +0100)]
aco: Fix signedness compare warning.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>

21 months agoaco: Fix maybe-uninitialized warnings.
Timur Kristóf [Tue, 21 Jan 2020 12:49:00 +0000 (13:49 +0100)]
aco: Fix maybe-uninitialized warnings.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>

21 months agoaco: Fix -Wstringop-overflow warnings in aco_span.
Timur Kristóf [Tue, 21 Jan 2020 12:43:13 +0000 (13:43 +0100)]
aco: Fix -Wstringop-overflow warnings in aco_span.

GCC does not understand how aco_span works.
This patch fixes it by casting the aco_span's this pointer
to uintptr_t rather than to a char pointer, effectively
telling GCC not to try to figure it out.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>

21 months agoradeon: Fix multiple definition error with radeon_debug
Timur Kristóf [Tue, 21 Jan 2020 15:36:54 +0000 (16:36 +0100)]
radeon: Fix multiple definition error with radeon_debug

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>

21 months agogallium: Fix a couple of multiple definition warnings.
Timur Kristóf [Tue, 21 Jan 2020 15:12:16 +0000 (16:12 +0100)]
gallium: Fix a couple of multiple definition warnings.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>

21 months agor600: Move get_pic_param to radeon_vce.c
Timur Kristóf [Tue, 21 Jan 2020 15:08:21 +0000 (16:08 +0100)]
r600: Move get_pic_param to radeon_vce.c

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>

21 months agoradeon: Move si_get_pic_param to radeon_vce.c
Timur Kristóf [Tue, 21 Jan 2020 15:04:33 +0000 (16:04 +0100)]
radeon: Move si_get_pic_param to radeon_vce.c

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>

21 months agointel/compiler: Fix array bounds warning on GCC 10.
Timur Kristóf [Tue, 21 Jan 2020 16:58:31 +0000 (17:58 +0100)]
intel/compiler: Fix array bounds warning on GCC 10.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
21 months agoturnip: Add support for non-zero (still constant) UBO buffer indices.
Eric Anholt [Wed, 22 Jan 2020 00:56:34 +0000 (16:56 -0800)]
turnip: Add support for non-zero (still constant) UBO buffer indices.

This was actually all ready to go at this point, and just needed to
increment by the value.

Fixes dEQP-VK.binding_model.shader_access.primary_cmd_buf.uniform_buffer.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3504>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3504>

21 months agoturnip: fix array/matrix varyings
Jonathan Marek [Sun, 15 Dec 2019 23:56:47 +0000 (18:56 -0500)]
turnip: fix array/matrix varyings

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>

21 months agoturnip: remove tu_sort_variables_by_location
Jonathan Marek [Sun, 15 Dec 2019 23:55:39 +0000 (18:55 -0500)]
turnip: remove tu_sort_variables_by_location

nir_assign_io_var_locations already does sorting.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>

21 months agofreedreno/ir3: allow inputs with the same location
Jonathan Marek [Sun, 15 Dec 2019 23:54:26 +0000 (18:54 -0500)]
freedreno/ir3: allow inputs with the same location

turnip can have multiple inputs with the same location, and different
location_frac.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>

21 months agogitlab-ci: Skip ext_timer_query/time-elapsed
Matt Turner [Tue, 21 Jan 2020 23:23:39 +0000 (15:23 -0800)]
gitlab-ci: Skip ext_timer_query/time-elapsed

This test's result is unpredictable, so it may occasionally pass when we
expect it to fail, thus causing the CI pipeline to fail.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3498>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3498>

21 months agointel/compiler: Test compaction on Gen <= 12
Matt Turner [Wed, 6 Nov 2019 18:14:45 +0000 (10:14 -0800)]
intel/compiler: Test compaction on Gen <= 12

With the previous commits we can now enable the unit test on Gen <= 12.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Validate fuzzed instructions
Matt Turner [Tue, 12 Nov 2019 00:11:34 +0000 (16:11 -0800)]
intel/compiler: Validate fuzzed instructions

... before giving them to the instruction compactor.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Add unit tests for new EU validation checks
Matt Turner [Fri, 3 Jan 2020 20:59:32 +0000 (12:59 -0800)]
intel/compiler: Add unit tests for new EU validation checks

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Validate some instruction word encodings
Matt Turner [Thu, 2 Jan 2020 22:44:16 +0000 (14:44 -0800)]
intel/compiler: Validate some instruction word encodings

Specifically, execution size, register file, and register type. I did
not add validation for vertical stride and width because I don't believe
it's possible to have an otherwise valid instruction with an invalid
vertical stride or width, due to all of the other regioning
restrictions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Factor out brw_validate_instruction()
Matt Turner [Mon, 11 Nov 2019 23:19:07 +0000 (15:19 -0800)]
intel/compiler: Factor out brw_validate_instruction()

In order to fuzz test instructions, we first need to do some sanity
checking first. Factoring out this function allows us an easy way to
validate a single instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Handle invalid compacted immediates
Matt Turner [Wed, 6 Nov 2019 18:05:48 +0000 (10:05 -0800)]
intel/compiler: Handle invalid compacted immediates

16-bit immediates need to be replicated through the 32-bit immediate
field, so we should never see one that isn't.

This does happen however in the fuzzer unit test, so returning false
allows the fuzzer to reject this case.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Handle invalid inputs to brw_reg_type_to_*()
Matt Turner [Thu, 2 Jan 2020 22:57:56 +0000 (14:57 -0800)]
intel/compiler: Handle invalid inputs to brw_reg_type_to_*()

Necessary to handle these cases when we test fuzzed instructions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Split hw_type tables
Matt Turner [Tue, 7 Jan 2020 08:27:23 +0000 (00:27 -0800)]
intel/compiler: Split hw_type tables

Previously we were sharing tables between generations that were nearly
identical (i.e., Gen8 3-src adds HF support) and used a small bit of
code to handle the differences. This is kind of a mess if you want to
reject 64-bit types on platforms that don't support 64-bit types, so
split the tables, allowing each generation's table to list exactly what
it supports.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Add a INVALID_{,HW_}REG_TYPE macros
Matt Turner [Mon, 6 Jan 2020 21:17:49 +0000 (13:17 -0800)]
intel/compiler: Add a INVALID_{,HW_}REG_TYPE macros

Since the enum brw_reg_type is packed, comparisons with -1 don't work
directly, necessitating the cast. Add a macro to avoid this confusion.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Add NF some more places
Matt Turner [Thu, 2 Jan 2020 22:54:34 +0000 (14:54 -0800)]
intel/compiler: Add NF some more places

Necessary to handle these cases when we test fuzzed instructions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Limit compaction unit tests to specific gens
Matt Turner [Wed, 6 Nov 2019 18:13:24 +0000 (10:13 -0800)]
intel/compiler: Limit compaction unit tests to specific gens

Two of the tests emit instructions with MRF destinations, and MRFs
aren't present on Gen7+. I think we were just lucky that this didn't
cause a problem earlier since we were running the tests on Gen7-9.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Don't disassemble align1 3-src operands on Gen < 10
Matt Turner [Tue, 21 Jan 2020 18:44:59 +0000 (10:44 -0800)]
intel/compiler: Don't disassemble align1 3-src operands on Gen < 10

Since the platforms don't support align1 3-src instructions, the
contents of these operands are not going to be meaningful. Just don't
print them to avoid hitting some assertions in brw_inst functions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Split has_64bit_types into float/int
Matt Turner [Mon, 13 Jan 2020 19:17:27 +0000 (11:17 -0800)]
intel/compiler: Split has_64bit_types into float/int

Gen7 has 64-bit floats but not 64-bit ints.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Extract GEN_* macros into separate file
Matt Turner [Thu, 31 Oct 2019 17:27:48 +0000 (10:27 -0700)]
intel/compiler: Extract GEN_* macros into separate file

Will be used by the instruction compaction unit test.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/compiler: Use ARRAY_SIZE()
Matt Turner [Thu, 16 Jan 2020 22:22:14 +0000 (14:22 -0800)]
intel/compiler: Use ARRAY_SIZE()

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

21 months agointel/fs: Don't emit control barrier if only one thread is used
Caio Marcelo de Oliveira Filho [Tue, 14 Jan 2020 20:03:22 +0000 (12:03 -0800)]
intel/fs: Don't emit control barrier if only one thread is used

When there's only one hardware thread (i.e. the dispatch width greater
or equal to the workgroup size), there's no need to use a barrier to
ensure all the invocations reach the same point in the shader, because
they are already running lock-step.

Results for SKL running Iris for shader-db tests with compute shaders

    total sends in shared programs: 18361 -> 18339 (-0.12%)
    sends in affected programs: 904 -> 882 (-2.43%)
    helped: 9
    HURT: 0
    helped stats (abs) min: 1 max: 5 x̄: 2.44 x̃: 2
    helped stats (rel) min: 0.84% max: 21.43% x̄: 7.82% x̃: 2.67%
    95% mean confidence interval for sends value: -3.31 -1.58
    95% mean confidence interval for sends %-change: -14.67% -0.97%
    Sends are helped.

Shaders from Aztec Ruins, Car Chase, Manhattan and DeusEx are helped.

Results for ICL and TGL are similar to SKL.

Results for BDW are similar to SKL except for DeusEx shader that has a
workgroup size 16 but in BDW picks the SIMD8.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>

21 months agointel/fs: Don't emit fence for shared memory if only one thread is used
Caio Marcelo de Oliveira Filho [Tue, 31 Dec 2019 09:01:27 +0000 (01:01 -0800)]
intel/fs: Don't emit fence for shared memory if only one thread is used

When there's only one hardware thread (i.e. the dispatch width greater
or equal to the workgroup size), there's no need to synchronize shared
memory access (SLM) since all the requests from a single thread are
already synchronized.  In such case, we just add a scheduling fence.

To be able to identify that case for all platforms, move the handling
of platforms prior to Gen11 (which don't have a separate SLM fence)
after the optimization.

Results for SKL running Iris for shader-db tests with compute shaders

    total sends in shared programs: 18395 -> 18361 (-0.18%)
    sends in affected programs: 938 -> 904 (-3.62%)
    helped: 9
    HURT: 0
    helped stats (abs) min: 1 max: 5 x̄: 3.78 x̃: 4
    helped stats (rel) min: 1.56% max: 26.32% x̄: 10.33% x̃: 2.60%
    95% mean confidence interval for sends value: -4.85 -2.71
    95% mean confidence interval for sends %-change: -19.12% -1.54%
    Sends are helped.

Shaders from Aztec Ruins, Car Chase, Manhattan and DeusEx are helped.

Results for ICL and TGL are similar to SKL.

Results for BDW are similar to SKL except for DeusEx shader that has a
workgroup size 16 but in BDW picks the SIMD8.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>

21 months agointel/fs: Add workgroup_size() helper
Caio Marcelo de Oliveira Filho [Tue, 14 Jan 2020 20:22:47 +0000 (12:22 -0800)]
intel/fs: Add workgroup_size() helper

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>

21 months agointel/fs: Add FS_OPCODE_SCHEDULING_FENCE
Caio Marcelo de Oliveira Filho [Thu, 2 Jan 2020 23:27:58 +0000 (15:27 -0800)]
intel/fs: Add FS_OPCODE_SCHEDULING_FENCE

Like a SHADER_OPCODE_MEMORY_FENCE but doesn't doesn't generate any
assembly code.

Will be used when the compiler shouldn't reorder certain instructions
but there's no need to generate code for the HW to do it -- as the
ordering will be guaranteed by other means.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>

21 months agogallium: check all planes' pipe formats in case of multi-samplers
Dongwon Kim [Wed, 15 Jan 2020 04:01:41 +0000 (20:01 -0800)]
gallium: check all planes' pipe formats in case of multi-samplers

Current code only checks whether first plane's format is supported
in case YUV format sampling is done by sampling each plane separately.
It would be safer to check other planes' as well.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2863>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2863>

21 months agoanv: Drop some workarounds that are no longer necessary
Kenneth Graunke [Fri, 17 Jan 2020 00:35:00 +0000 (16:35 -0800)]
anv: Drop some workarounds that are no longer necessary

These workarounds are no longer required by 10th Gen hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>

21 months agoiris: Drop some workarounds which are no longer necessary
Kenneth Graunke [Fri, 17 Jan 2020 00:34:10 +0000 (16:34 -0800)]
iris: Drop some workarounds which are no longer necessary

These workarounds are no longer required by 10th Gen hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>

21 months agoturnip: Disable UBWC on images used as storage images.
Eric Anholt [Thu, 16 Jan 2020 00:58:21 +0000 (16:58 -0800)]
turnip: Disable UBWC on images used as storage images.

The closed GL driver doesn't use UBWC on any storage images.  It does tile
mostly (skipping tiling on writeonly images, it seems), but for freedreno
we've been enabling tiling in all cases and it's fine.  We do need to
disable UBWC, as tests fail otherwise and just plugging in the equivalent
UBWC regs like we were setting up a texture isn't enough.

Fixes dEQP-VK.image.atomic_operations.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>

21 months agoturnip: Add limited support for storage images.
Eric Anholt [Mon, 9 Dec 2019 21:31:35 +0000 (13:31 -0800)]
turnip: Add limited support for storage images.

So far this doesn't handle the texture state-based storage image access
loads, and doesn't support descriptor arrays (same as SSBOs).  The texture
side is more tricky, since we have another remapping table to work around.

This is enough to get some of dEQP-VK.image.atomic_operations.* working.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>

21 months agoturnip: Refactor the intrinsic lowering.
Eric Anholt [Thu, 19 Dec 2019 00:30:37 +0000 (16:30 -0800)]
turnip: Refactor the intrinsic lowering.

Too many things in one function, split them out based on the intrinsic.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>

21 months agoturnip: Fix some whitespace around binary operators.
Eric Anholt [Fri, 20 Dec 2019 00:47:08 +0000 (16:47 -0800)]
turnip: Fix some whitespace around binary operators.

Conforms to mesa style and the rest of turnip.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>

21 months agoradeonsi: Drop PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS.
Eric Anholt [Mon, 6 Jan 2020 23:13:04 +0000 (15:13 -0800)]
radeonsi: Drop PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS.

Now that we don't expose TGSI, we can stop exposing the flag.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>

21 months agor300: Remove a bunch of default handling of pipe caps.
Eric Anholt [Mon, 6 Jan 2020 23:01:36 +0000 (15:01 -0800)]
r300: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.
The exception is the texel/gather offsets and stream output
components, which will not be exposed since we don't expose the
corresponding GLSL version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>

21 months agor600: Remove a bunch of default handling of pipe caps.
Eric Anholt [Mon, 6 Jan 2020 22:56:46 +0000 (14:56 -0800)]
r600: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>

21 months agoradeonsi: Remove a bunch of default handling of pipe caps.
Eric Anholt [Mon, 6 Jan 2020 22:52:57 +0000 (14:52 -0800)]
radeonsi: Remove a bunch of default handling of pipe caps.

u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>

21 months agoanv: don't report error with other vendor DRM devices
Lionel Landwerlin [Tue, 21 Jan 2020 16:19:18 +0000 (18:19 +0200)]
anv: don't report error with other vendor DRM devices

Enumeration should just skip unsupported DRM devices.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 34c8621c3b37 ("anv: Allow enumerating multiple physical devices")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2386
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3481>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3481>

21 months agofreedreno: Stop scattered remapping of SSBOs/images to IBOs.
Eric Anholt [Fri, 20 Dec 2019 22:02:55 +0000 (14:02 -0800)]
freedreno: Stop scattered remapping of SSBOs/images to IBOs.

Just make it be all SSBOs then all storage images.  The remapping table
was there to make it so that the big gap present from gallium's atomic
lowering would get cleaned up, but that's no longer case.  The table has
made it very hard to support Vulkan storage images, so it's time for it to
go.

This does mean that an SSBO/IBO that is only loaded (or size-queried) will
now occupy a slot in the table where it wouldn't before.  This seems like
a minor cost compared to being able to drop this much logic.

With the remapping table gone, SSBO array handling for turnip just falls
out.

Fixes many array cases of
dEQP-VK.binding_model.shader_access.primary_cmd_buf.storage_buffer.*

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca> (turnip)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>

21 months agocompiler: Add a note about how num_ssbos works in the program info.
Eric Anholt [Mon, 30 Dec 2019 20:01:25 +0000 (12:01 -0800)]
compiler: Add a note about how num_ssbos works in the program info.

These numbers are always confusing, and it's particularly so for this
field where it has a different meaning in different info structs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>

21 months agonir: Drop the ssbo_offset to atomic lowering.
Eric Anholt [Fri, 20 Dec 2019 21:52:06 +0000 (13:52 -0800)]
nir: Drop the ssbo_offset to atomic lowering.

The arguments passed in were:
- prog->info.num_ssbos
- prog->nir->info.num_ssbos
- arbitrary values for standalone compilers

The num_ssbos should match between the prog's info and prog->nir's info
until this lowering happens.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>

21 months agogallium: Pack the atomic counters just above the SSBOs.
Eric Anholt [Fri, 20 Dec 2019 21:30:04 +0000 (13:30 -0800)]
gallium: Pack the atomic counters just above the SSBOs.

We carve out half the SSBO space for atomics, and we were just binding
them way up there.  freedreno was then using a remapping table to map the
sparse buffer index back down, since space in the descriptor array is a
shared resource that may limit parallelism.  That remapping table
generated inside of the ir3 compiler is getting thoroughly in the way of
implementing vulkan descriptor sets.

We will be able to get rid of the freedreno's remapping table, and
hopefully save shared resources on other hardware, by packing the atomics
tightly above the SSBOs (like i965 does).  We already rebind the shader
buffers on program change if either the old or new program has SSBOs or
ABOs, so this doesn't necessarily increase the program state change cost
(the only cost increase I can come up with is if you're using the same
atomic counter without rebinding it across changes of programs with
varying SSBO counts, meaning it would now bounce around index space).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>

21 months agomesa: Make atomic lowering put atomics above SSBOs.
Eric Anholt [Fri, 20 Dec 2019 17:02:07 +0000 (09:02 -0800)]
mesa: Make atomic lowering put atomics above SSBOs.

Gallium arbitrarily (it seems) put atomics below SSBOs, resulting in a
bunch of extra index management, and surprising shader code when you would
see your SSBOs up at index 16.  It makes a lot more sense to see atomics
converted to SSBOs appear as magic high numbers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>

21 months agoturnip: Refactor linkage state setup.
Eric Anholt [Fri, 20 Dec 2019 22:26:44 +0000 (14:26 -0800)]
turnip: Refactor linkage state setup.

As I touch this for descriptor set reworks, I don't want to have to update
it twice.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>

21 months agonouveau/nvc0: add extern keyword to nvc0_miptree_vtbl.
Timur Kristóf [Tue, 21 Jan 2020 16:11:22 +0000 (17:11 +0100)]
nouveau/nvc0: add extern keyword to nvc0_miptree_vtbl.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
21 months agoanv: initialize clear_color_is_zero_one
Tapani Pälli [Tue, 21 Jan 2020 14:48:11 +0000 (16:48 +0200)]
anv: initialize clear_color_is_zero_one

Fixes following valgrind warning:

   ==12508== Conditional jump or move depends on uninitialised value(s)
   ==12508==    at 0x2CCD8B79: cmd_buffer_begin_subpass (genX_cmd_buffer.c:4599)
   ==12508==    by 0x2CCDA72B: gen9_CmdBeginRenderPass (genX_cmd_buffer.c:5275)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3487>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3487>

21 months agopanfrost/midgard: Print the actual source register for store operations
Boris Brezillon [Mon, 20 Jan 2020 21:00:48 +0000 (22:00 +0100)]
panfrost/midgard: Print the actual source register for store operations

Store operation use r26/r27 but have a word->reg set to 0 or 1 (base is
r26). Let's take this base offset into account in
print_load_store_instr().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3482>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3482>

21 months agopanfrost: Add pandecode entries for ASTC/ETC formats
Alyssa Rosenzweig [Thu, 16 Jan 2020 15:43:03 +0000 (10:43 -0500)]
panfrost: Add pandecode entries for ASTC/ETC formats

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>

21 months agopanfrost: Add ASTC texture formats
Icecream95 [Sat, 11 Jan 2020 06:19:45 +0000 (19:19 +1300)]
panfrost: Add ASTC texture formats

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>

21 months agopanfrost: Add ETC1/ETC2 texture formats
Icecream95 [Sat, 11 Jan 2020 07:00:38 +0000 (20:00 +1300)]
panfrost: Add ETC1/ETC2 texture formats

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>

21 months agopanfrost: Rework linear<--->tiled conversions
Alyssa Rosenzweig [Wed, 15 Jan 2020 18:15:01 +0000 (13:15 -0500)]
panfrost: Rework linear<--->tiled conversions

There's a lot going on here (it's a ton of commits squashed together
since otherwise this would be impossible to review...)

1. We have a fast path for linear->tiled for whole (aligned) tiles, but we
have to use a slow path for unaligned accesses. We can get a pretty
major win for partial updates by using this slow path simply on the
borders of the update region, and then hit the fast path for the
tile-aligned interior. This does require some shuffling.

2. Mark the LUTs constant, which allows the compiler to inline them,
which pairs well with loop unrolling (eliminating the memory accesses
and just becoming some immediates.. which are not as immediate on
aarch64 as I'd like..)

3. Add fast path for bpp1/2/8/16. These use the same algorithm and we
have native types for them, so may as well get the fast path.

4. Drop generic path for bpp != 1/2/8/16, since these formats are
generally awful and there's no way to tile them efficienctly and
honestly there's not a good reason too either. Lima doesn't support any
of these formats; Panfrost can make the opinionated choice to make them
linear.

5. Specialize the unaligned routines. They don't have to be fully
generic, they just can't assume alignment. So now they should be nearly
as fast as the aligned versions (which get some extra tricks to be even
faster but the difference might be neglible on some workloads).

6. Specialize also for the size of the tile, to allow 4x4 tiling as well
as 16x16 tiling. This allows compressed textures to be efficiently tiled
with the same routines (so we add support for tiling ASTC/ETC textures
while we're at it)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> #lima on Mali400
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>

21 months agopanfrost,lima: De-Galliumize tiling routines
Alyssa Rosenzweig [Tue, 14 Jan 2020 17:52:02 +0000 (12:52 -0500)]
panfrost,lima: De-Galliumize tiling routines

There's an implicit dependence on Gallium here that will add more
complexity than needed when testing/optimizing out of driver as well as
potentially Vulkanizing. We don't need a full pipe_box, just the x/y/w/h
properties directly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> #lima on Mali400
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>

21 months agopanfrost: Compile tiling routines with -O3
Alyssa Rosenzweig [Tue, 14 Jan 2020 17:27:47 +0000 (12:27 -0500)]
panfrost: Compile tiling routines with -O3

These are major hot spots for panfrost and lima; better let the compiler
do its thing even on debug builds.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> #lima on Mali400
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>

21 months agoradv: Remove syncobj_handle variable in header.
Bas Nieuwenhuizen [Tue, 21 Jan 2020 10:49:55 +0000 (11:49 +0100)]
radv: Remove syncobj_handle variable in header.

I strongly suspect it was supposed to be a typedef. However, used
nowhere, we should remove it.

Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2385
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3479>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3479>

21 months agogitlab-ci/lava: add pipeline information in the lava job name
Neil Armstrong [Tue, 15 Oct 2019 13:22:07 +0000 (15:22 +0200)]
gitlab-ci/lava: add pipeline information in the lava job name

In order to have more informations in the LAVA jobs list, add the
current pipeline URL and commit ref name in the LAVA job name.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2337>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2337>

21 months agogallium/gallivm: enable linking lp_bld_printf function with C++ code
Jan Zielinski [Mon, 20 Jan 2020 12:57:36 +0000 (13:57 +0100)]
gallium/gallivm: enable linking lp_bld_printf function with C++ code

To enable linking functions declared in lp_bld_printf.h file with C++,
we need to add appropriate macros to the header.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3470>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3470>

21 months agoiris: Fix value of out-of-bounds accesses for vertex attributes
Danylo Piliaiev [Wed, 15 Jan 2020 16:56:42 +0000 (18:56 +0200)]
iris: Fix value of out-of-bounds accesses for vertex attributes

Having VERTEX_BUFFER_STATE.BufferSize greater than the size of
a bound vertex buffer allows shader to read uninitialized vertex
attributes from BO, instead of allowing hardware to return zeroes
on out-of-bounds access.

OpenGL spec "6.4 Effects of Accessing Outside Buffer Bounds" says:

"Robust buffer access can be enabled by creating a context with robust access
 enabled through the window system binding APIs. When enabled, any command
 unable to generate a GL error as described above, such as buffer object accesses
 from the active program, will not read or modify memory outside of the data
 store of the buffer object and will not result in GL interruption or termination.
 Out-of-bounds reads may return values from within the buffer object or zero
 values."

Fixes three webgl tests:
 conformance/rendering/out-of-bounds-array-buffers.html
 conformance2/rendering/out-of-bounds-index-buffers-after-copying.html
 conformance2/rendering/element-index-uint.html

See #1996

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3427>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3427>

21 months agoci: Re-enable CI for lima on mali450
Vasily Khoruzhick [Thu, 19 Dec 2019 06:15:11 +0000 (22:15 -0800)]
ci: Re-enable CI for lima on mali450

Amend fails and skips lists basing on lists from Andreas Baierl,
shard mali400 job across two devices since it takes close to 10min
and rename jobs to lima-mali400-test and lima-mali450-test.

Also don't set MESA_GLES_VERSION_OVERRIDE=3.0 for lima since we don't support
GLES 3.0 and lower DEQP_PARALLEL to 3 for jobs on H3.

Keep mali400 jobs disabled atm since they take too much time to complete
and we also get some unexplicable failures in dEQP-GLES2.functional.default_vertex_attrib.*

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>

21 months agoci: lava: pass CI_NODE_INDEX and CI_NODE_TOTAL to lava jobs
Vasily Khoruzhick [Fri, 17 Jan 2020 03:37:32 +0000 (19:37 -0800)]
ci: lava: pass CI_NODE_INDEX and CI_NODE_TOTAL to lava jobs

deqp-runner.sh uses it to determine whether we split job across multiple
devices and if we do what's the node index.

With this change we now can set 'parallel: N' in job description if we want
to split the job.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>

21 months agoturnip: fix invalid VK_ERROR_OUT_OF_POOL_MEMORY
Hyunjun Ko [Fri, 17 Jan 2020 07:23:03 +0000 (07:23 +0000)]
turnip: fix invalid VK_ERROR_OUT_OF_POOL_MEMORY

When VK_DESCRIPTOR_TYPE_SAMPLER is provided, it doesn't need to be
counted as a buffer count. Otherwise it leads to mismatch of allocated
buffer size, hitting VK_ERROR_OUT_OF_POOL_MEMORY finally.

Fixes: c39afe68f0390d45130c1317b3b7e65f55542c36
Also fixes amber tests:
./tests/cases/address_modes_float.amber
./tests/cases/address_modes_int.amber
./tests/cases/magfilter_linear.amber
./tests/cases/magfilter_nearest.amber

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
21 months agoclover: Initialize Asm Parsers
Jan Vesely [Sun, 19 Jan 2020 02:27:01 +0000 (21:27 -0500)]
clover: Initialize Asm Parsers

Fixes piglits that use ADMGCN inline assembly:
program@execute@calls
program@execute@amdgcn-mubuf-negative-vaddr

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
21 months agoanv: Allow enumerating multiple physical devices
Jason Ekstrand [Sat, 18 Jan 2020 05:52:50 +0000 (23:52 -0600)]
anv: Allow enumerating multiple physical devices

Instead of having a single physical device in anv_instance, have a
linked list of them.  What we have now works today because we our GPUs
are build into the CPU and so you're guaranteed to only ever have one of
them.  One day, that will change and we want ANV to be ready.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Re-arrange physical_device_init
Jason Ekstrand [Sat, 18 Jan 2020 05:48:12 +0000 (23:48 -0600)]
anv: Re-arrange physical_device_init

This commit simply moves fetching the device info and checking if ANV
supports the device a bit higher up.  This way we fail earlier and it'll
make error checking easier in the next commit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Drop separate chipset_id fields
Jason Ekstrand [Sat, 18 Jan 2020 05:45:31 +0000 (23:45 -0600)]
anv: Drop separate chipset_id fields

This already exists in gen_device_info.  There's no reason to keep
duplicate copies.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Move the physical device dispatch table to anv_instance
Jason Ekstrand [Sat, 18 Jan 2020 05:17:48 +0000 (23:17 -0600)]
anv: Move the physical device dispatch table to anv_instance

We don't actually have genX versions of any physical device level
commands so we don't need the trampoline versions and we don't need to
have a separate table per physical device.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Drop the instance pointer from anv_device
Jason Ekstrand [Sat, 18 Jan 2020 05:05:13 +0000 (23:05 -0600)]
anv: Drop the instance pointer from anv_device

There are very few times when we actually want to fetch the instance
from the anv_device.  We can put up with a bit of pain there in exchange
for strongly discouraging people from doing this in general.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Stop allocating WSI event fences off the instance
Jason Ekstrand [Sat, 18 Jan 2020 05:03:41 +0000 (23:03 -0600)]
anv: Stop allocating WSI event fences off the instance

Fixes: 16eb390834d "anv: add VK_EXT_display_control to anv driver [v5]"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Take a device in anv_perf_warn
Jason Ekstrand [Sat, 18 Jan 2020 04:57:35 +0000 (22:57 -0600)]
anv: Take a device in anv_perf_warn

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Take an anv_device in vk_errorf
Jason Ekstrand [Sat, 18 Jan 2020 04:43:06 +0000 (22:43 -0600)]
anv: Take an anv_device in vk_errorf

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoanv: Add an anv_physical_device field to anv_device
Jason Ekstrand [Sat, 18 Jan 2020 04:23:30 +0000 (22:23 -0600)]
anv: Add an anv_physical_device field to anv_device

Having to always pull the physical device from the instance has been
annoying for almost as long as the driver has existed.  It also won't
work in a world where we ever have more than one physical device.  This
commit adds a new field called "physical" to anv_device and switches
every location where we use device->instance->physicalDevice to use the
new field instead.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>

21 months agoradeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling
Marek Olšák [Thu, 9 Jan 2020 01:21:04 +0000 (20:21 -0500)]
radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling

Only non-indexed triangle lists and strips are supported. This increases
performance if there is something to cull.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: rewrite late alloc computation
Marek Olšák [Thu, 9 Jan 2020 21:09:47 +0000 (16:09 -0500)]
radeonsi/gfx10: rewrite late alloc computation

- Use conservative late alloc when the number of CUs <= 6.
- Move the late alloc GS register to the GS shader state, so that it can be
  tuned for NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoac: add helper ac_build_triangle_strip_indices_to_triangle
Marek Olšák [Fri, 10 Jan 2020 00:12:36 +0000 (19:12 -0500)]
ac: add helper ac_build_triangle_strip_indices_to_triangle

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: implement NGG culling for 4x wave32 subgroups
Marek Olšák [Mon, 30 Dec 2019 19:23:16 +0000 (14:23 -0500)]
radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: move GE_PC_ALLOC setting to shader states
Marek Olšák [Tue, 24 Dec 2019 18:50:06 +0000 (13:50 -0500)]
radeonsi/gfx10: move GE_PC_ALLOC setting to shader states

The value is not changed. I just use a different way to compute it.

The value will vary with NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: don't initialize VGPRs not used by NGG passthrough
Marek Olšák [Sat, 4 Jan 2020 02:16:22 +0000 (21:16 -0500)]
radeonsi/gfx10: don't initialize VGPRs not used by NGG passthrough

v2: TES doesn't use the GS PrimitiveID

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: merge main and pos/param export IF blocks into one if possible
Marek Olšák [Fri, 3 Jan 2020 22:07:38 +0000 (17:07 -0500)]
radeonsi/gfx10: merge main and pos/param export IF blocks into one if possible

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: export primitives at the beginning of VS/TES
Marek Olšák [Fri, 3 Jan 2020 21:59:20 +0000 (16:59 -0500)]
radeonsi/gfx10: export primitives at the beginning of VS/TES

This decreases VGPR usage and will allow us to merge some IF blocks
in shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: move s_sendmsg gs_alloc_req to the beginning of shaders
Marek Olšák [Fri, 3 Jan 2020 21:20:40 +0000 (16:20 -0500)]
radeonsi/gfx10: move s_sendmsg gs_alloc_req to the beginning of shaders

This will allow us to merge some IF blocks in shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: correct VS PrimitiveID implementation for NGG
Marek Olšák [Fri, 6 Dec 2019 01:46:30 +0000 (20:46 -0500)]
radeonsi/gfx10: correct VS PrimitiveID implementation for NGG

We didn't use the correct LDS pointer, though it probably doesn't matter,
because I think that nothing else is using LDS here.

This commit makes it consistent with all other esgs_ring use.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi/gfx10: update comments and remove invalid TODOs
Marek Olšák [Tue, 24 Dec 2019 00:42:46 +0000 (19:42 -0500)]
radeonsi/gfx10: update comments and remove invalid TODOs

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoac: add ac_build_readlane without optimization barrier
Marek Olšák [Thu, 2 Jan 2020 23:41:26 +0000 (18:41 -0500)]
ac: add ac_build_readlane without optimization barrier

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoac: add prefix bitcount functions
Marek Olšák [Mon, 30 Dec 2019 19:08:45 +0000 (14:08 -0500)]
ac: add prefix bitcount functions

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi: turn an assertion into return in si_nir_store_output_tcs
Marek Olšák [Sat, 18 Jan 2020 00:55:13 +0000 (19:55 -0500)]
radeonsi: turn an assertion into return in si_nir_store_output_tcs

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi: fix doubles and int64
Marek Olšák [Fri, 17 Jan 2020 23:37:35 +0000 (18:37 -0500)]
radeonsi: fix doubles and int64

Fixes: 57bd73e2296 - radeonsi: remove llvm_type_is_64bit
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoradeonsi: don't invoke decompression inside internal launch_grid
Marek Olšák [Sat, 18 Jan 2020 02:24:14 +0000 (21:24 -0500)]
radeonsi: don't invoke decompression inside internal launch_grid

Decompress resources properly but don't do it inside launch_grid
to prevent recursion.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
21 months agoradeonsi: clean up how internal compute dispatches are handled
Marek Olšák [Sat, 18 Jan 2020 02:23:12 +0000 (21:23 -0500)]
radeonsi: clean up how internal compute dispatches are handled

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
21 months agoRevert "radeonsi: unbind image before compute clear"
Marek Olšák [Sat, 18 Jan 2020 00:19:43 +0000 (19:19 -0500)]
Revert "radeonsi: unbind image before compute clear"

This reverts commit 3a527eda7ceee37643f948bfcf05285c5aa3a4d6.

It's incorrect.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
21 months agoaco: implement nir_intrinsic_load_barycentric_at_sample on GFX6
Samuel Pitoiset [Thu, 16 Jan 2020 16:03:43 +0000 (17:03 +0100)]
aco: implement nir_intrinsic_load_barycentric_at_sample on GFX6

GFX6 doesn't have FLAT instructions which means we have to emit
a 64-bit MUBUF load.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>

21 months agoaco: add new addr64 bit to MUBUF instructions on GFX6-GFX7
Samuel Pitoiset [Thu, 16 Jan 2020 16:02:44 +0000 (17:02 +0100)]
aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7

According to the different ISA docs (and to LLVM), this bit seems
to only exists on GFX6-GFX7.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>

21 months agoaco: do not use the vec3 variant for loads on GFX6
Samuel Pitoiset [Thu, 16 Jan 2020 13:44:02 +0000 (14:44 +0100)]
aco: do not use the vec3 variant for loads on GFX6

GFX6 only supports vec3 with load/store format.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>