meson: move wayland_drm_protocol generation to wayland-drm

These files are needed by both vulkan wayland-wsi and by egl
wayland-wsi, since the XML file is in src/egl/wayland/wayland-drm and we
can include this directory in such a way that it will be loaded before
egl and vulkan this allows us to avoid multiple calls to the same
generator.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-and-Tested-by: Eric Engestrom <eric@engestrom.ch>

meson: Don't allow glx to be built without platform_x11

Previously this failed to change with_glx to disabled from auto if
platform_x11 was unset or if no opengl apis were being built.

v2: - swap conditional positions

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-and-Tested-by: Eric Engestrom <eric@engestrom.ch>

meson: bump libdrm_amdgpu requirement to 2.4.85

fixes: b60372570323243ec73 ("configure.ac: Bump libdrm_amdgpu version to 2.4.85.")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

nir: Print the components referenced for split or packed shader in/outs.

Having 4 variables all called "gl_in_TexCoord0@n" isn't very informative,
much better to see:

decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0 (VARYING_SLOT_VAR0.x, 1, 0)
decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@0 (VARYING_SLOT_VAR0.y, 1, 0)
decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@1 (VARYING_SLOT_VAR0.z, 1, 0)
decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@2 (VARYING_SLOT_VAR0.w, 1, 0)

v2: Handle arrays and structs better (by Timothy)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

nir: Add a safety check that we don't remove dead I/O vars after lowering.

The pass only looks at var load/store intrinsics, not input load/store
intrinsics, so assert that we don't see the other type.

v2: Adjust comment indentation.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: disable implicit sync for radv allocated bos v3

Implicit sync kicks in when a buffer is used by two different amdgpu
contexts simultaneously. Jobs that use explicit synchronization
mechanisms end up needlessly waiting to be scheduled for long periods
of time in order to achieve serialized execution.

This patch disables implicit synchronization for all radv allocations
except for wsi bos. The only systems that require implicit
synchronization are DRI2/3 and PRIME.

v2: mark wsi bos as RADV_MEM_IMPLICIT_SYNC
v3: Add drm version check (Bas)

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: factor out radv_alloc_memory

This allows us to pass extra parameters to the memory allocation
operation that are not defined in the vulkan spec. This is useful for
internal usage.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: Expose VK_EXT_global_priority

Expose the extension string as supported

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: don't skip PS/VS partial flush

This patch helps lower high priority compute latency. Found by
bisecting a perf regression on computeparticles with high priority
compute queues enabled.

Reverting this micro-optimization doesn't seem to have any negative
effect on performance on Dota2 or ssao.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: Implement VK_EXT_global_priority

This extension allows the caller to change a queue's system wide
priority. This is useful for applications with specific
latency constraints.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: hardcode shader WAVE_LIMIT to the maximum value

This is part of a cooperative scheduling approach used by radv. All
drivers in the stack must opt-in to resource arbitration, otherwise GL
based apps will be able to ignore system priorities.

We always hardcode the field to its maximum value, instead of attempting
to calculate an approximate usage. In testing, there were no benefits to
using anything other than the maximum.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: hardcode shader WAVE_LIMIT to the maximum value

When WAVE_LIMIT is set, a submission will opt-in for SPI based resource
scheduling. Because this mechanism is cooperative, we must ensure that
all submissions have this field set, otherwise they will bypass resource
arbitration.

We always hardcode the field to its maximum value, instead of attempting
to calculate an approximate usage. In testing, there were no benefits to
using anything other than the maximum.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

vulkan: update headers & registry to VK 1.0.63

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

configure.ac: Bump libdrm_amdgpu version to 2.4.85.

For VK_EXT_global_priority in radv.

Acked-by: Andres Rodriguez <andresx7@gmail.com>

broadcom/vc5: Use SETMSF to handle discards.

A bit of spec text suggested that (like vc4) condition codes should be
used for discards, and the simulator was fine with it, but the 7268
disagrees and you have to use SETMSF instead or the color comes through.
Fixes glsl-fs-discard-01 and many of the interpolation-with-clipping
tests.

broadcom/vc5: Set the snorm/unorm packing functions to be lowered.

We don't have native instructions for them, so set up the lowering.  Once
we support the bfi instructions that get generated, they should start
actually working.

broadcom/vc5: Fix pasteo that broke vertex texturing.

We weren't ever filling in the texture state record, so we'd dereference
NULL from the shader.

broadcom/vc5: Move default attribute value setup to the CSO and fix them.

I was generating some stub values to bring the driver up, but fill them in
properly now.  We now set 1.0 or 1u as appropriate, and thanks to being in
their own BO it fixes piglit failures on the 7268 (where our 4-byte
alignment was insufficient).

Fixes const-packHalf2x16.shader_test

broadcom/vc5: Move most of the shader state attribute record to the CSO.

This should reduce our draw-time overhead, and puts the code where it
should go long term.

broadcom/vc5: Fix build failure frm nir_shader::stage removal.

Fixes: 59fb59ad54d3 ("nir: Get rid of nir_shader::stage")

i965/fs: Use align1 mode on ternary instructions on Gen10+

Align1 mode offers some nice features over align16, like access to more
data types and the ability to use a 16-bit immediate. This patch does
not start using any new features. It just emits ternary instructions in
align1 mode.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add align1 ternary instruction emission support

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add align1 ternary instruction disassembler support

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add align1 ternary instruction-word support

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add align1 ternary instruction support to conversion functions

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add align1 ternary instruction field encodings

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add functions to abstract access to 3src register types

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Rename brw_inst's functions that access the 3src register type

Put hw_ in the name so that it's clear these are the hardware encodings.

Similar to commit 9fb832332868 ("i965: Rename brw_inst's functions that
access the register type")

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Rename brw_inst 3src functions in preparation for align1

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Print subreg in units of type-size on ternary instructions

The instruction word contains SubRegNum[4:2] so it's in units of dwords
(hence the * 4 to get it in terms of bytes). Before this patch, the
subreg would have been wrong for DF arguments.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add functions for brw_reg_type <-> hw 3src type

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Move brw_reg_type_is_floating_point to brw_reg_type.h

I'm going to call this from brw_inst.h, and I don't want to have to
include all of brw_reg.h.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

nir: Get rid of nir_shader::stage

It's redundant with nir_shader::info::stage.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

radv: use optimal packet order for draws

Ported from RadeonSI. The time where shaders are idle should
be shorter now. This can give a little boost, like +6% with
the dynamicubo Vulkan demo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add radv_emit_shaders_prefetch()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add radv_emit_shader_prefetch()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

st/mesa: correct a u_vbuf comment

trivial.

etnaviv: fix implicit conversion warning

Galliums query_type used in APIs is unsigned.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: enable occlusion query if GPU supports it

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: add support for occlusion queries

Passes most occlusion query piglits. The following piglits are broken:
- spec@arb_occlusion_query@occlusion_query_meta_fragments
- spec@arb_occlusion_query@occlusion_query_meta_save
- spec@arb_occlusion_query2@render

v1 -> v2:
 - use one sample provider for all occlusion queries tyes
 - add comment about 'magic' value 0x1DF5E76

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: add basic infrastructure for hw queries

No hardware query is supported yet.

v1 -> v2
 - removed query_type from strcut etna_hw_sample_provider

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: update headers from rnndb

Update to etna_viv commit 6c9c706.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

relnotes/17.3: EGL_IMG_context_priority is now implemented

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Report supported context priorities to EGL/DRI

Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to
report the available DRM_I915_GEM_CONTEXT_SETPARAM options based on the
per-client default context. The kernel will validate the request to change
the property, so we get an accurate reflection of available support
(based on kernel version and privilege) and we should only have to do it
once during screen setup -- although the SETPARAM should be fast, they
are still an ioctl each.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass the EGL/DRI context priority through to the kernel

Decode the EGL/DRI priority enum into the [-1023, 1023] range as
interpreted by the kernel and call DRM_I915_GEM_CONTEXT_SETPARAM to
adjust the priority. We use 0 as the default medium priority (also the
kernel default) and so only need adjust up or down. By only doing the
adjustment if not setting to medium, we can faithfully report any error
whilst setting without worrying about kernel version.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Record the presence of the kernel scheduler

Mention to the debug log if the kernel scheduler is enabled; and in
particular if it has preemption enabled.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Sync i915_drm.h from kernel for IMG_context_priority

Pulling in changes up to

    kernel commit ac14fbd460d0ec16e7750e40dcd8199b0ff83d0a
    Author: Chris Wilson <chris@chris-wilson.co.uk>
    Date:   Tue Oct 3 21:34:53 2017 +0100

drm/i915/scheduler: Support user-defined priorities

and including the fixup from

    kernel commit 822a4b673284672af697ccd66e8795f8a712a90d
    Author: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Date:   Fri Oct 6 13:45:59 2017 +0300

drm/i915: Don't use BIT() in UAPI section

for implementing IMG_context_priority.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

egl,dri: Propagate context priority hint to driver->CreateContext

Jump through the layers of abstraction between egl and dri in order to
feed the context priority attribute through to the backend. This
requires us to read the value from the base _egl_context, convert it to
a DRI attribute, parse it again in the generic context creator before
passing it to the driver as a function parameter.

In order to not require us to pass back the actual value of the context
priority after creation, we impose that drivers should report the
available set of priorities during screen setup (and then they may chose
to fail if given an invalid value as that should have been checked at
the user boundary.)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Ben Widawsky <ben@bwidawsk.net> # i915/i965
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

egl: Support IMG_context_priority

IMG_context_priority
https://www.khronos.org/registry/egl/extensions/IMG/EGL_IMG_context_priority.txt

    "This extension allows an EGLContext to be created with a priority
    hint. It is possible that an implementation will not honour the
    hint, especially if there are constraints on the number of high
    priority contexts available in the system, or system policy limits
    access to high priority contexts to appropriate system privilege
    level. A query is provided to find the real priority level assigned
    to the context after creation."

The extension adds a new eglCreateContext attribute for choosing a
priority hint. This stub parses the attribute and copies into the base
struct _egl_context, and hooks up the query similarly.

Since the attribute is purely a hint, I have no qualms about the lack of
implementation before reporting back the value the user gave!

v2: Remember to set the default ContextPriority value to medium.
v3: Use the driRendererQuery interface to probe the backend for
supported priority values and use those to mask the EGL interface.
v4: Treat the priority attrib as a hint and gracefully mask any requests
not supported by the driver, the EGLContext will remain at medium
priority.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rob Clark <robdclark@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Emil Velikov <emli.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: don't flush the VS when srcStageMask == TOP_OF_PIPE_BIT

The Vulkan specification says:

   "... an execution dependency with only VK_PIPELINE_STAGE_TOP_OF_-
    PIPE_BIT in the source stage mask will effectively not wait for
    any prior commands to complete."

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: mark total_count as MAYBE_UNUSED in CmdSet{Viewport,Scissor}

Fixes two compilation warnings in release build. Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: rename radv_cmd_buffer_flush_state() to radv_draw()

Similar to the dispatch codepath.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: emit primitive restart from radv_emit_draw_registers()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add radv_emit_draw_registers()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: refactor indirect draws (+count buffer) with radv_draw_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: refactor indirect draws with radv_draw_info

Indirect draws with a count buffer will be refactored in a
separate patch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: refactor simple and indexed draws with radv_draw_info

Similar to the dispatch compute logic but for draw calls. For
convenience, indirect draws will be converted in a separate
patch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it

Only on CIK and later. We should only update VGT_INDEX_TYPE but
it seems easier to re-emit all the index buffer packets.

Fixes: 966d66f28f (radv: do not re-emit the index buffer for every draw call)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: clear the dirty flags in the corresponding emit helpers

This will allow us to fix the VGT_INDEX_TYPE issue properly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: rename RADV_CMD_DIRTY_RENDER_TARGETS to RADV_CMD_DIRTY_FRAMEBUFFER

To be consistent with the emit function name.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: move DB_COUNT_CONTROL initialization to si_emit_config()

CLEAR_STATE will initialize DB_COUNT_CONTROL to 0 for CIK+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

i965/vec4: remove setting default LOD in the backend

It is already done in NIR.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

i965/fs: remove setting default LOD in the backend

It is already done in NIR.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

nir: set default lod to texture opcodes that needed it but don't provide it

v2:
- Use helper to add a new source to the texture instruction.

v3:
- Use nir_tex_instr_src_index() to simplify the patch (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radv: enable GS on GFX9

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: calculate and emit GFX9 GS registers to pipeline state.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Fix up GS input vgprs.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Add loading from LDS for merged GS.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Add ES output to LDS for GFX9.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Add merged GS function.

[airlied: merged fixup + and fixed up a couple more bits].

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Only emit TES when it exists.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Use control shader presence for detecting tess.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: fixup tess eval shader when combined.

This fixes some access to the tess eval shader when it's combined
with geometry on gfx9.

This is a review of Bas's commit:
radv: Prevent crashing by accessing TES for VGT reuse depth.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Set VGT_GS_MODE properly for gfx9

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: ensure correct outinfo is picked.

This struct used to rely on being in a union, it isn't anymore,
so we have to pick the correct outinfo struct now.

This should fix a regression since the union became a struct.

dEQP-VK.tessellation.geometry_interaction.point_size.vertex_set_geometry_set

Fixes: 6078a3bd51 (ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

swr: Rework scratch space allocation

Remove allocation of > 2kbyte buffers into context memory in
swr_copy_to_scatch_space() (which is used to copy small vertex/index buffers
and shader constants to a scratch space to be used by the upcoming draw.)

Large shader constant allocations need to be done in the circular scratch
buffer instead of context memory, because their values persist across
render calls.

Also lower SCRATCH_SINGLE_ALLOCATION_LIMIT to 8k, since allocations of larger
buffers will get too large for the circular scratch space.

Fixes render issues with CEI Ensight.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radv: Enable tessellation shaders for  GFX9.

It mostly works now.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: init full exec mask for merged shaders.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: drop unused r600_htile_info.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix CLEAR_STATE packet length.

Looking at shader traces I noticed some registers were missing,
one of them was being eaten by the wrong clear state length.

Fixes: 4f42ea4dc (radv: use CLEAR_STATE for initializing some registers)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

meson: don't build gallium dri target if gallium is disabled

Otherwise -Dgallium-drivers= will cause libmesa_gallium to be built and
the megadriver install script to attempt to install drivers without any
actual drivers being built.

fixes: 66f97f6640f5316b36177fd1053f0027eb6ec6cc ("meson: build radeonsi")
Reported-by: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

radv: copy indirect lowering settings from radeonsi

It looks the original indirect mask was probably copied from
ANV.

Sascha Willems demo results:

tessellation ~4000 -> ~4200 fps

V2: continue lowering local indirects due to llvm deficiencies.

Tested-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: stop redundant setting of active_stages

We already set it when above in the nir compilation loop.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac: move some code out of loop in store_tcs_output()

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Modify rsrc1/rsrc2 generation for merged tess.

No OC_LDS_EN for HS, and the included LS vgpr_comp_cnt is at
a different offset.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Set correct registers for merged shader rings.

We need different regs to end up in s0/s1.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add GFX9 HS emitting code.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Remove remaining hard coded references to VS.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Update GFX9 user data regs for GS/tess.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add code to compile merged shaders.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Add LS-HS input VGPR workaround.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Compile the bodies of multiple shaders.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Expand user SGPR descriptions a bit.

To prevent VS/TCS collisions in merged shaders.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Don't write to the dynamic HS word on GFX9.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Add function creation for merged LS+HS.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Make scan_shader_output_decl less dependent on the context.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Change interface to allow multiple source shaders.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: Add HS calling convention.

Needed for GFX9 merged shaders.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac: Parse the new HS RSRC1 register.

Reviewed-by: Dave Airlie <airlied@redhat.com>